Rev Author Line No. Line
4918 kaklik 1 --------------------------------------------
2 -- wrapper for the iserdes_ddr and pack_data
3 --
4 library ieee;
5 use ieee.std_logic_1164.all;
6  
7 library UNISIM;
8 use UNISIM.vcomponents.all;
9  
10 entity myserdes_ddr_wrapper is
11 generic
12 (-- width of the data for the system
13 sys_w : integer := 1;
14 -- width of the data for the device
15 dev_w : integer := 8);
16 port (
17  
18 -- CLOCK:
19 clk_in : in std_logic;
20 clk_in_div : in std_logic;
21  
22 -- PADS IN:
23 data_in_from_pins_p : in std_logic;
24 data_in_from_pins_n : in std_logic;
25  
26 data_in_to_device : out std_logic_vector( dev_w - 1 downto 0 );
27  
28 bitslip : in std_logic;
29  
30 rst_in : in std_logic );
31  
32 end myserdes_ddr_wrapper;
33  
34 architecture behavioral of myserdes_ddr_wrapper is
35  
36 component myserdes_ddr is
37 generic
38 (-- width of the data for the system
39 sys_w : integer := 1;
40 -- width of the data for the device
41 dev_w : integer := 8);
42 port
43 (
44 -- From the system into the device
45 DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0);
46 DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0);
47 DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0);
48  
49 BITSLIP : in std_logic; -- Bitslip module is enabled in NETWORKING mode
50 -- User should tie it to '0' if not needed
51  
52 -- Clock and reset signals
53 CLK_IN : in std_logic; -- Fast clock from IOB, after IBUFGDS and BUFIO
54 CLK_DIV_IN : in std_logic; -- Divided fast clock from IBUFGDS and BUFR
55  
56 IO_RESET : in std_logic); -- Reset signal for IO circuit
57 end component;
58  
59 -- data in signal:
60 signal s_data_in_from_pins_p : std_logic_vector( sys_w-1 downto 0 );
61 signal s_data_in_from_pins_n : std_logic_vector( sys_w-1 downto 0 );
62  
63 begin
64  
65 -- convert std_logic to std_logic_vector
66 s_data_in_from_pins_n(0) <= data_in_from_pins_n;
67 s_data_in_from_pins_p(0) <= data_in_from_pins_p;
68  
69 -- instantiate the myserdes_ddr
70 myserdes_ddr_inst : myserdes_ddr
71 port map (
72 DATA_IN_FROM_PINS_P => s_data_in_from_pins_p, DATA_IN_FROM_PINS_N => s_data_in_from_pins_n,
73 DATA_IN_TO_DEVICE => data_in_to_device,
74 BITSLIP => bitslip, CLK_IN => clk_in, CLK_DIV_IN => clk_in_div, IO_RESET => rst_in );
75  
76  
77 end architecture;
78