Rev Author Line No. Line
4918 kaklik 1 library ieee;
2 use ieee.std_logic_1164.all;
3  
4 library UNISIM;
5 use UNISIM.vcomponents.all;
6  
7 library sychro1;
8 library utilities;
9 library comm;
10  
11 library kakona;
12 use kakona.kakona_package.all;
13  
14 entity xilly_toplevel is
15  
16 port (
17 -- FMC & other ports:
18  
19 -- local oscillator to be divided
20 IN_CLK_LO_N : IN std_logic;
21 IN_CLK_LO_P : IN std_logic;
22 -- divided clock
23 OUT_CLK_LO_DIVIDED_N : OUT std_logic;
24 OUT_CLK_LO_DIVIDED_P : OUT std_logic;
25  
26 -- input data:
27 -- clock:
28 IN_CLK_FOR_DATA_P : IN std_logic;
29 IN_CLK_FOR_DATA_N : IN std_logic;
30 -- frame signal:
31 IN_FRAME_FOR_DATA_N : IN std_logic;
32 IN_FRAME_FOR_DATA_P : IN std_logic;
33  
34 -- data from ADCs:
35 IN_DATA_ADC_P : IN std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS - 1 downto 0 );
36 IN_DATA_ADC_N : IN std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS - 1 downto 0 );
37  
38 -- our LEDs:
39 GPIO_LED2 : OUT std_logic_vector(3 DOWNTO 0);
40  
41 -- SPI communication block:
42 OUT_SPI_N_CE : OUT std_logic_vector( C_NUM_INPUT_ADC_MODULES-1 downto 0 );
43 OUT_SPI_DOUT : OUT std_logic;
44 OUT_SPI_CLK : OUT std_logic;
45  
46 -- test:
47 --OUT_TEST1 : OUT std_logic;
48  
49 -- dummy inputs due to incorrect soldering -- pins are hardconnected to ground.
50 IN_DUMMY : IN std_logic_vector( 1 downto 0 );
51  
52 -- GPIO_DIP_SWITCH:
53 GPIO_DIP_SW : IN std_logic_vector( 7 downto 0 );
54  
55 -- original xillybus-only ports:
56 PCIE_PERST_B_LS : IN std_logic;
57 PCIE_REFCLK_N : IN std_logic;
58 PCIE_REFCLK_P : IN std_logic;
59 PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
60 PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
61 GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
62 PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
63 PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0));
64 end xilly_toplevel;
65  
66 architecture behavioral of xilly_toplevel is
67  
68 component multiplexer_from_fifos
69 generic
70 ( G_NUM_CHANNELS : natural := 2; -- number of channels
71 G_DATA_WIDTH : natural := 32 -- data width of individual packets
72 );
73 port (
74  
75 clk : in std_logic;
76 rst : in std_logic;
77  
78 -- input side
79 i_data : in std_logic_vector( G_DATA_WIDTH*G_NUM_CHANNELS - 1 downto 0 );
80 i_valid : in std_logic_vector( G_NUM_CHANNELS - 1 downto 0 );
81 o_rden : out std_logic_vector( G_NUM_CHANNELS - 1 downto 0 );
82  
83 -- output side
84 o_data : out std_logic_vector( G_DATA_WIDTH - 1 downto 0 );
85 o_valid : out std_logic;
86 i_full : in std_logic
87  
88 );
89 end component;
90  
91 COMPONENT fifo_32x512_walmostfull
92 PORT (
93 clk : IN STD_LOGIC;
94 srst : IN STD_LOGIC;
95 din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 wr_en : IN STD_LOGIC;
97 rd_en : IN STD_LOGIC;
98 dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 full : OUT STD_LOGIC;
100 empty : OUT STD_LOGIC;
101 valid : OUT STD_LOGIC;
102 prog_full : OUT STD_LOGIC
103 );
104 END COMPONENT;
105  
106 component bitslip_compensation
107 port (
108  
109 clk : in std_logic;
110 rst : in std_logic;
111  
112 i_data : in std_logic_vector( 15 downto 0 );
113 i_valid : in std_logic;
114  
115 o_bitslip : out std_logic;
116 o_bitslip_done : out std_logic;
117 o_bitslip_drop_byte : out std_logic;
118 o_bitslip_failed : out std_logic
119  
120 );
121 end component;
122  
123 component iserdes_clock_generator
124 port
125 (
126 -- Clock and reset signals
127 CLK_IN_P : in std_logic; -- Differential fast clock from IOB
128 CLK_IN_N : in std_logic;
129 CLK_OUT : out std_logic; -- Fast clock output (synchronous to data)
130 CLK_DIV_OUT : out std_logic; -- Slow clock output
131  
132 CLK_RESET : in std_logic); -- Reset signal for Clock circuit
133  
134 end component;
135  
136  
137 component xillybus
138 port (
139 PCIE_PERST_B_LS : IN std_logic;
140 PCIE_REFCLK_N : IN std_logic;
141 PCIE_REFCLK_P : IN std_logic;
142 PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
143 PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
144 GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
145 PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
146 PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0);
147 bus_clk : OUT std_logic;
148 quiesce : OUT std_logic;
149 user_r_control_r_rden : OUT std_logic;
150 user_r_control_r_empty : IN std_logic := '0';
151 user_r_control_r_data : IN std_logic_vector(31 DOWNTO 0) := ( others => '0' );
152 user_r_control_r_eof : IN std_logic := '0';
153 user_r_control_r_open : OUT std_logic;
154 user_w_control_w_wren : OUT std_logic;
155 user_w_control_w_full : IN std_logic := '0';
156 user_w_control_w_data : OUT std_logic_vector(31 DOWNTO 0);
157 user_w_control_w_open : OUT std_logic;
158 user_r_data1_r_rden : OUT std_logic;
159 user_r_data1_r_empty : IN std_logic;
160 user_r_data1_r_data : IN std_logic_vector(31 DOWNTO 0);
161 user_r_data1_r_eof : IN std_logic;
162 user_r_data1_r_open : OUT std_logic;
163 user_w_data1_w_wren : OUT std_logic;
164 user_w_data1_w_full : IN std_logic;
165 user_w_data1_w_data : OUT std_logic_vector(31 DOWNTO 0);
166 user_w_data1_w_open : OUT std_logic;
167 user_r_data2_r_rden : OUT std_logic;
168 user_r_data2_r_empty : IN std_logic := '0';
169 user_r_data2_r_data : IN std_logic_vector(31 DOWNTO 0) := ( others => '0' );
170 user_r_data2_r_eof : IN std_logic := '0';
171 user_r_data2_r_open : OUT std_logic;
172 user_w_data2_w_wren : OUT std_logic;
173 user_w_data2_w_full : IN std_logic := '0';
174 user_w_data2_w_data : OUT std_logic_vector(31 DOWNTO 0);
175 user_w_data2_w_open : OUT std_logic);
176 end component;
177  
178 component xilly_userlogiccmp_wrapper
179 port (
180 i_clk : in std_logic;
181 i_rst : in std_logic;
182  
183 user_r_control_r_rden : in std_logic := '0';
184 user_r_control_r_empty : out std_logic := '1';
185 user_r_control_r_data : out std_logic_vector(31 DOWNTO 0);
186  
187 user_w_control_w_wren : in std_logic := '0';
188 user_w_control_w_full : out std_logic := '0';
189 user_w_control_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' );
190  
191 user_r_data1_r_rden : in std_logic := '0';
192 user_r_data1_r_empty : out std_logic := '1';
193 user_r_data1_r_data : out std_logic_vector(31 DOWNTO 0);
194  
195 user_w_data1_w_wren : in std_logic := '0';
196 user_w_data1_w_full : out std_logic := '0';
197 user_w_data1_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' );
198  
199 user_r_data2_r_rden : in std_logic := '0';
200 user_r_data2_r_empty : out std_logic := '1';
201 user_r_data2_r_data : out std_logic_vector(31 DOWNTO 0);
202  
203 user_w_data2_w_wren : in std_logic := '0';
204 user_w_data2_w_full : out std_logic := '0';
205 user_w_data2_w_data : in std_logic_vector(31 DOWNTO 0) := ( others => '0' )
206 );
207 end component;
208  
209 signal bus_clk : std_logic;
210 signal quiesce : std_logic;
211  
212 signal user_r_control_r_rden : std_logic;
213 signal user_r_control_r_empty : std_logic;
214 signal user_r_control_r_data : std_logic_vector(31 DOWNTO 0);
215 --signal user_r_control_r_eof : std_logic;
216 signal user_r_control_r_open : std_logic;
217 signal user_w_control_w_wren : std_logic;
218 signal user_w_control_w_full : std_logic;
219 signal user_w_control_w_data : std_logic_vector(31 DOWNTO 0);
220 signal user_w_control_w_open : std_logic;
221  
222 signal user_r_data1_r_rden : std_logic;
223 signal user_r_data1_r_empty : std_logic;
224 signal user_r_data1_r_data : std_logic_vector(31 DOWNTO 0);
225 --signal user_r_data1_r_eof : std_logic;
226 signal user_r_data1_r_open : std_logic;
227 signal user_w_data1_w_wren : std_logic;
228 signal user_w_data1_w_full : std_logic;
229 signal user_w_data1_w_data : std_logic_vector(31 DOWNTO 0);
230 signal user_w_data1_w_open : std_logic;
231  
232 signal user_r_data2_r_rden : std_logic;
233 signal user_r_data2_r_empty : std_logic;
234 signal user_r_data2_r_data : std_logic_vector(31 DOWNTO 0);
235 --signal user_r_data2_r_eof : std_logic;
236 signal user_r_data2_r_open : std_logic;
237 signal user_w_data2_w_wren : std_logic;
238 signal user_w_data2_w_full : std_logic;
239 signal user_w_data2_w_data : std_logic_vector(31 DOWNTO 0);
240 signal user_w_data2_w_open : std_logic;
241  
242 -- reset signal from xillybus. '1' when no device is open
243 signal s_reset : std_logic;
244  
245  
246 -- generated clock from ADC by iserdes_clock_generator:
247 signal s_iserdes_clk : std_logic;
248 signal s_iserdes_clk_div : std_logic;
249  
250 -- Frame signal
251 signal s_data16_to_bitslip : std_logic_vector( 15 downto 0 );
252 signal s_data16_to_bitslip_valid : std_logic;
253 signal s_bitslip : std_logic;
254 signal s_bitslip_done : std_logic;
255 signal s_bitslip_drop_byte : std_logic;
256 signal s_bitslip_failed : std_logic;
257  
258 signal s_bitslip_regged : std_logic;
259 signal s_bitslip_drop_byte_regged : std_logic;
260  
261 -- from all ADC processing blocks:
262 signal s_from_processing_blocks_data : std_logic_vector( (C_NUM_INPUT_ADC_DATA_PORTS+1)*32 - 1 downto 0 ); -- +1 is space for output from frame
263 signal s_from_processing_blocks_valid : std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS+1 - 1 downto 0 );
264 signal s_from_processing_blocks_rden : std_logic_vector( C_NUM_INPUT_ADC_DATA_PORTS+1 - 1 downto 0 );
265  
266 -- from multiplexer:
267 signal s_from_multiplexer_data : std_logic_vector( 31 downto 0 );
268 signal s_from_multiplexer_valid : std_logic;
269 signal s_from_multiplexer_full : std_logic;
270  
271 -- SPI communication module:
272 signal s_spi_done : std_logic;
273  
274 -- GPIO_DIP_SW register
275 signal s_gpio_dip_sw : std_logic_vector( 7 downto 0 );
276  
277 signal s_valid_for_bitslip_processing : std_logic;
278  
279 begin
280  
281 -- Xillybus instantiation:
282 xillybus_ins : xillybus
283 port map (
284 -- Ports related to /dev/xillybus_control_r
285 -- FPGA to CPU signals:
286 user_r_control_r_rden => user_r_control_r_rden,
287 user_r_control_r_empty => user_r_control_r_empty,
288 user_r_control_r_data => user_r_control_r_data,
289 user_r_control_r_eof => '0',
290 user_r_control_r_open => user_r_control_r_open,
291  
292 -- Ports related to /dev/xillybus_control_w
293 -- CPU to FPGA signals:
294 user_w_control_w_wren => user_w_control_w_wren,
295 user_w_control_w_full => user_w_control_w_full,
296 user_w_control_w_data => user_w_control_w_data,
297 user_w_control_w_open => user_w_control_w_open,
298  
299 -- Ports related to /dev/xillybus_data1_r
300 -- FPGA to CPU signals:
301 user_r_data1_r_rden => user_r_data1_r_rden,
302 user_r_data1_r_empty => user_r_data1_r_empty,
303 user_r_data1_r_data => user_r_data1_r_data,
304 user_r_data1_r_eof => '0',
305 user_r_data1_r_open => user_r_data1_r_open,
306  
307 -- Ports related to /dev/xillybus_data1_w
308 -- CPU to FPGA signals:
309 user_w_data1_w_wren => user_w_data1_w_wren,
310 user_w_data1_w_full => user_w_data1_w_full,
311 user_w_data1_w_data => user_w_data1_w_data,
312 user_w_data1_w_open => user_w_data1_w_open,
313  
314 -- Ports related to /dev/xillybus_data2_r
315 -- FPGA to CPU signals:
316 user_r_data2_r_rden => user_r_data2_r_rden,
317 user_r_data2_r_empty => user_r_data2_r_empty,
318 user_r_data2_r_data => user_r_data2_r_data,
319 user_r_data2_r_eof => '0',
320 user_r_data2_r_open => user_r_data2_r_open,
321  
322 -- Ports related to /dev/xillybus_data2_w
323 -- CPU to FPGA signals:
324 user_w_data2_w_wren => user_w_data2_w_wren,
325 user_w_data2_w_full => user_w_data2_w_full,
326 user_w_data2_w_data => user_w_data2_w_data,
327 user_w_data2_w_open => user_w_data2_w_open,
328  
329 -- General signals
330 PCIE_PERST_B_LS => PCIE_PERST_B_LS,
331 PCIE_REFCLK_N => PCIE_REFCLK_N,
332 PCIE_REFCLK_P => PCIE_REFCLK_P,
333 PCIE_RX_N => PCIE_RX_N,
334 PCIE_RX_P => PCIE_RX_P,
335 GPIO_LED => GPIO_LED,
336 PCIE_TX_N => PCIE_TX_N,
337 PCIE_TX_P => PCIE_TX_P,
338 bus_clk => bus_clk,
339 quiesce => quiesce
340 );
341  
342 s_reset <= '0' when user_r_control_r_open = '1' or
343 user_w_control_w_open = '1' or
344 user_r_data1_r_open = '1' or
345 user_w_data1_w_open = '1' or
346 user_r_data2_r_open = '1' or
347 user_w_data2_w_open = '1' or
348 s_gpio_dip_sw(0) = '0' else
349 '1';
350  
351 -- register the gpio_dip_sw(0) with the 125MHz clock:
352 registers_for_gpio0 : process( bus_clk )
353 begin
354 if( rising_edge( bus_clk ) ) then
355 s_gpio_dip_sw(0) <= gpio_dip_sw(0);
356 s_gpio_dip_sw(2) <= gpio_dip_sw(2); -- used for SPI confifuration block that is clocked with bus_clk
357 end if;
358 end process;
359  
360 -- register the gpio_dip_sw(1) with the clk_div clock:
361 registers_for_gpio1 : process( s_iserdes_clk_div )
362 begin
363 if( rising_edge( s_iserdes_clk_div ) ) then
364 s_gpio_dip_sw(1) <= gpio_dip_sw(1);
365 end if;
366 end process;
367  
368  
369 -- xilly_userlogiccmp_wrapper instantiation:
370 xilly_userlogiccmp_wrapper_inst : xilly_userlogiccmp_wrapper
371 port map (
372 i_clk => bus_clk,
373 i_rst => s_reset,
374  
375 user_r_control_r_rden => user_r_control_r_rden,
376 user_r_control_r_empty => user_r_control_r_empty,
377 user_r_control_r_data => user_r_control_r_data,
378  
379 user_w_control_w_wren => user_w_control_w_wren,
380 user_w_control_w_full => user_w_control_w_full,
381 user_w_control_w_data => user_w_control_w_data,
382  
383 user_r_data1_r_rden => user_r_data1_r_rden,
384 user_r_data1_r_empty => user_r_data1_r_empty,
385 user_r_data1_r_data => user_r_data1_r_data,
386  
387 user_w_data1_w_wren => user_w_data1_w_wren,
388 user_w_data1_w_full => user_w_data1_w_full,
389 user_w_data1_w_data => user_w_data1_w_data,
390  
391 -- user_r_data2_r_rden => user_r_data2_r_rden,
392 -- user_r_data2_r_empty => user_r_data2_r_empty,
393 -- user_r_data2_r_data => user_r_data2_r_data,
394  
395 -- user_w_data2_w_wren => user_w_data2_w_wren,
396 -- user_w_data2_w_full => user_w_data2_w_full,
397 -- user_w_data2_w_data => user_w_data2_w_data
398  
399 user_r_data2_r_rden => open,
400 user_r_data2_r_empty => open,
401 user_r_data2_r_data => open,
402  
403 user_w_data2_w_wren => open,
404 user_w_data2_w_full => open,
405 user_w_data2_w_data => open
406  
407 );
408  
409  
410  
411  
412  
413  
414  
415 -- tie outputs:
416  
417 --OUT_TEST1 <= '0';
418  
419  
420  
421  
422 GPIO_LED2(0) <= s_bitslip_done;
423 GPIO_LED2(1) <= s_bitslip_failed;
424 GPIO_LED2(2) <= s_bitslip_drop_byte_regged;
425 GPIO_LED2(3) <= s_bitslip_regged;
426  
427 ddd : process( s_iserdes_clk_div )
428 begin
429 if( rising_edge( s_iserdes_clk_div ) ) then
430 if( s_reset = '1' ) then
431 s_bitslip_regged <= '0';
432 s_bitslip_drop_byte_regged <= '0';
433 else
434 s_bitslip_regged <= s_bitslip_regged or s_bitslip;
435 s_bitslip_drop_byte_regged <= s_bitslip_drop_byte_regged or s_bitslip_drop_byte;
436 end if;
437 end if;
438 end process;
439  
440 -----------------------------------------------------------------------------------------------
441 -- DATA PROCESSING:
442  
443 -- Clock generator:
444 iserdes_clock_generator_inst : iserdes_clock_generator
445 port map (
446 CLK_IN_P => IN_CLK_FOR_DATA_P, CLK_IN_N => IN_CLK_FOR_DATA_N,
447 CLK_OUT => s_iserdes_clk, CLK_DIV_OUT => s_iserdes_clk_div, CLK_RESET => '0' );
448  
449 -- FRAME signal processing block:
450 frame_processing_block_inst : entity work.processing_block
451 port map (
452 clk_iserdes_in => s_iserdes_clk, clk_iserdes_in_div => s_iserdes_clk_div, clk_global => bus_clk,
453 rst => s_reset,
454 bitslip => s_bitslip, bitslip_done => s_bitslip_done, bitslip_drop_byte => s_bitslip_drop_byte,
455 in_data_p => IN_FRAME_FOR_DATA_P, in_data_n => IN_FRAME_FOR_DATA_N,
456 in_data_swap_pn => C_FRAME_WIRES_SWAPPED_PN,
457 in_output_counting => s_gpio_dip_sw(1),
458  
459 o_iserdes_output => s_data16_to_bitslip,
460 o_iserdes_output_valid => s_data16_to_bitslip_valid,
461  
462 o_data => s_from_processing_blocks_data( 31 downto 0 ),
463 o_valid => s_from_processing_blocks_valid( 0 ),
464 i_rden => s_from_processing_blocks_rden( 0 )
465 );
466  
467 -- bitslip processing:
468 s_valid_for_bitslip_processing <= s_data16_to_bitslip_valid and s_spi_done;
469  
470 bitslip_compensation_inst : bitslip_compensation
471 port map (
472 clk => s_iserdes_clk_div, rst => s_reset,
473 i_data => s_data16_to_bitslip, i_valid => s_valid_for_bitslip_processing,
474 o_bitslip => s_bitslip, o_bitslip_done => s_bitslip_done, o_bitslip_drop_byte => s_bitslip_drop_byte, o_bitslip_failed => s_bitslip_failed );
475  
476 -- ADCs signal processing blocks:
477 adc_proc_block_gen : for i in 0 to C_NUM_INPUT_ADC_DATA_PORTS - 1 generate
478 adc_processing_block_inst : entity work.processing_block
479 port map (
480 clk_iserdes_in => s_iserdes_clk, clk_iserdes_in_div => s_iserdes_clk_div, clk_global => bus_clk,
481 rst => s_reset,
482 bitslip => s_bitslip, bitslip_done => s_bitslip_done, bitslip_drop_byte => s_bitslip_drop_byte,
483 in_data_p => IN_DATA_ADC_P(i), in_data_n => IN_DATA_ADC_N(i),
484 in_data_swap_pn => C_DATA_WIRES_SWAPPED_PN(i),
485 in_output_counting => '0',
486  
487 o_iserdes_output => open, o_iserdes_output_valid => open,
488  
489 o_data => s_from_processing_blocks_data( 32*(i+1+1) - 1 downto 32*(i+1) ), -- i+1, because 31 downto 0 is used by the FRAME result
490 o_valid => s_from_processing_blocks_valid( i + 1 ),
491 i_rden => s_from_processing_blocks_rden( i + 1 )
492 );
493 end generate;
494  
495 -- multiplexer:
496 multiplexer_from_fifos_inst : multiplexer_from_fifos
497 generic map (
498 G_NUM_CHANNELS => C_NUM_INPUT_ADC_DATA_PORTS + 1,
499 G_DATA_WIDTH => 32 )
500 port map (
501 clk => bus_clk, rst => s_reset,
502  
503 i_data => s_from_processing_blocks_data, i_valid => s_from_processing_blocks_valid,
504 o_rden => s_from_processing_blocks_rden,
505  
506 o_data => s_from_multiplexer_data, o_valid => s_from_multiplexer_valid, i_full => s_from_multiplexer_full
507 );
508  
509 -- interface to xillybus:
510 -- FIFO_OUT instantiation:
511 data2_frame_fifo_out_inst : fifo_32x512_walmostfull
512 port map (
513 clk => bus_clk, srst => s_reset,
514 din => s_from_multiplexer_data, wr_en => s_from_multiplexer_valid, full => open, prog_full => s_from_multiplexer_full,
515 dout => user_r_data2_r_data, rd_en => user_r_data2_r_rden, empty => user_r_data2_r_empty, valid => open );
516  
517 -----------------------------------------------------------------------------------------------
518 -- LO - Local Oscillator division module:
519  
520 -- TODO: not tested: addition of the CE input. Will the ADCs configure themselves without CLOCK?
521 lo_divider_wrapper_inst : entity work.lo_divider_wrapper
522 generic map ( G_DIVISOR => 30 )
523 port map (
524 IN_CLK_LO_N => IN_CLK_LO_N, IN_CLK_LO_P => IN_CLK_LO_P, in_clk_enable => '1',
525 OUT_CLK_LO_DIVIDED_N => OUT_CLK_LO_DIVIDED_N, OUT_CLK_LO_DIVIDED_P => OUT_CLK_LO_DIVIDED_P );
526  
527 -----------------------------------------------------------------------------------------------
528 -- SPI MASTER COMMUNICATION MODULE
529  
530 spi_transmitter_wrapper_inst : entity work.spi_transmitter_wrapper
531 generic map(
532 G_DATA1 => C_SPI_ADC_DATA1,
533 G_DATA2 => C_SPI_ADC_DATA2,
534 G_NUM_BITS_PACKET => C_SPI_ADC_LENGTH,
535 G_NUM_PACKETS => C_SPI_ADC_PACKETS,
536 G_NUM_BITS_PAUSE => C_SPI_ADC_PAUSE )
537 port map(
538 i_clk125 => bus_clk, i_reset => s_reset, i_data_selector => s_gpio_dip_sw(2),
539 o_done => s_spi_done,
540 OUT_SPI_N_CE => OUT_SPI_N_CE, OUT_SPI_DOUT => OUT_SPI_DOUT, OUT_SPI_CLK => OUT_SPI_CLK );
541  
542 end architecture;
543