Rev Author Line No. Line
4918 kaklik 1 -- Provides information about the firmware.
2 -- This block is written as a generic memory that sends data based on the requested address.
3 --
4 -- Generally this block is connected to the 'control' interface in the userlogiccmp_forxilly block and the user interacts with it using the 'control' files.
5 -- The information_data package should contain several mandatory constants as well as the contents of the memory. Generally, the first four 32-bit-tuples are occupied by a unique GUID that identifies the firmware.
6  
7 library ieee;
8 use ieee.std_logic_1164.all;
9 use ieee.numeric_std.all;
10  
11 library utilities;
12 use utilities.utilities.all;
13  
14 library information;
15 use information.information_data.all;
16  
17 ----------------------------------------------------------------
18 -- NOTE: No range check on the i_data requested address.
19  
20 entity information_block is
21  
22 port (
23  
24 clk : in std_logic;
25 rst : in std_logic;
26  
27 -- Input side:
28 i_data : in std_logic_vector( 31 downto 0 );
29 i_valid : in std_logic;
30 o_enable : out std_logic;
31  
32 -- Output side:
33 o_data : out std_logic_vector( 31 downto 0 );
34 o_valid : out std_logic;
35 i_enable : in std_logic
36  
37 );
38  
39 end entity;
40  
41 architecture rtl of information_block is
42  
43 -- data in buffer
44 signal buffer_valid : std_logic;
45 signal buffer_data : std_logic_vector( o_data'range );
46 -- data from the memory
47 signal mem_valid : std_logic;
48 signal mem_data : std_logic_vector( o_data'range );
49  
50 signal oo_valid : std_logic;
51  
52 signal addr : unsigned( log2( C_INFO_NUMDATA ) - 1 downto 0 );
53 --signal i_valid_d : std_logic;
54  
55 constant C_RESVAL : std_logic_vector( C_INFO_BITWIDTH -1 downto 0 ) := ( others => '0' );
56  
57 -- Memory content:
58 subtype t_memdata is t_twodim_stdlogic( C_INFO_NUMDATA - 1 downto 0, C_INFO_BITWIDTH - 1 downto 0 );
59 constant C_MEMDATA : t_memdata := stdlogicvector_to_twodim( C_INFO_DATA, C_INFO_NUMDATA, C_INFO_BITWIDTH );
60  
61 begin
62  
63 o_enable <= i_enable;
64 o_valid <= oo_valid and i_enable;
65  
66 o_data <= buffer_data when buffer_valid = '1' else
67 mem_data;
68 oo_valid <= buffer_valid when buffer_valid = '1' else
69 mem_valid;
70  
71 valid_handling: process( clk )
72 begin
73 if( rising_edge(clk) ) then
74 mem_valid <= i_valid;
75 end if;
76 end process;
77  
78 addr <= unsigned( i_data( addr'range ) );
79  
80 -- inferred bram:
81 inferred_bram_inst : entity utilities.inferred_bram
82 generic map(
83 G_RAM_CONTENT => C_MEMDATA,
84 G_WIDTH => C_INFO_BITWIDTH,
85 G_SIZE => C_INFO_NUMDATA,
86 G_RESVAL_A => C_RESVAL
87 )
88 port map(
89 i_clka => clk,
90 i_ena => '1',
91 i_wea => '0',
92 i_resa => '0',
93 i_addra => addr,
94 i_dataa => ( C_INFO_BITWIDTH - 1 downto 0 => '0' ),
95 o_dataa => mem_data
96 );
97  
98 outp_data : process( clk )
99 begin
100 if( rising_edge(clk) ) then
101 if( rst = '1' ) then
102 buffer_valid <= '0';
103 else
104  
105 if( i_enable = '1' ) then
106 buffer_valid <= '0';
107 elsif( buffer_valid = '0' ) then
108 buffer_valid <= mem_valid;
109 buffer_data <= mem_data;
110 end if;
111  
112 end if;
113 end if;
114 end process;
115  
116  
117 end architecture;