Rev Author Line No. Line
4918 kaklik 1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4  
5 library UNISIM;
6 use UNISIM.vcomponents.all;
7  
8 entity clock_divider is
9 generic (
10 G_DIVISOR : positive := 2
11 );
12 port (
13  
14 i_clk : in std_logic;
15 i_rst : in std_logic;
16  
17 o_clk : out std_logic
18  
19 );
20 end entity clock_divider;
21  
22 architecture behavioral of clock_divider is
23  
24 subtype t_counter is natural range 0 to ( G_DIVISOR - 1 );
25 signal s_counter : t_counter := 0;
26  
27 constant C_COUNTER : t_counter := G_DIVISOR / 2 - 1;
28  
29 signal s_clk_divided : std_logic;
30 attribute clock_signal : string;
31 attribute clock_signal of s_clk_divided : signal is "yes";
32  
33 begin
34  
35 assert ( G_DIVISOR > 1 ) report "The divisor should be greater than 1" severity failure;
36  
37 counting : process( i_clk )
38 begin
39 if( rising_edge(i_clk) ) then
40 if( i_rst = '1' ) then
41 s_counter <= 0;
42 s_clk_divided <= '0';
43 else
44 if( s_counter = t_counter'high ) then
45 s_counter <= 0;
46 s_clk_divided <= '0';
47 else
48 s_counter <= s_counter + 1;
49 if( s_counter = C_COUNTER ) then
50 s_clk_divided <= '1';
51 end if;
52 end if;
53 end if;
54 end if;
55 end process counting;
56  
57 BUFR_inst : BUFR
58 generic map (
59 BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
60 SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6"
61 port map (
62 O => o_clk, -- Clock buffer output
63 CE => '1', -- Clock enable input
64 CLR => '0', -- Clock buffer reset input
65 I => s_clk_divided -- Clock buffer input
66 );
67  
68 end architecture;