Rev Author Line No. Line
4918 kaklik 1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4  
5 entity up_counter_stdlv is
6 generic (
7 G_BITS : positive := 8;
8 G_MIN_NUMBER : std_logic_vector;
9 G_MAX_NUMBER : std_logic_vector
10  
11 );
12 port (
13  
14 i_clk : in std_logic;
15 i_rst : in std_logic;
16  
17 -- Count when this input is '1'
18 i_valid : in std_logic;
19  
20 -- Output the actual number
21 o_data : out std_logic_vector( G_BITS-1 downto 0 );
22 o_carry : out std_logic := '0'
23  
24 );
25 end up_counter_stdlv;
26  
27 architecture rtl of up_counter_stdlv is
28  
29 signal number : std_logic_vector( G_BITS-1 downto 0 );
30  
31 begin
32  
33 o_data <= number;
34  
35 counter : process( i_clk )
36 begin
37  
38 if( rising_edge( i_clk ) ) then
39  
40 o_carry <= '0';
41  
42 if( i_rst = '1' ) then
43 number <= G_MIN_NUMBER;
44 elsif( i_valid = '1' ) then
45 -- count up:
46 if( number = G_MAX_NUMBER ) then
47 number <= G_MIN_NUMBER;
48 o_carry <= '1';
49 else
50 number <= std_logic_vector( unsigned(number) + to_unsigned(1,G_BITS) );
51 end if;
52 end if;
53  
54 end if;
55 end process;
56  
57 end architecture;