Rev Author Line No. Line
4918 kaklik 1 library ieee;
2 use ieee.std_logic_1164.all;
3  
4 library fifo_related;
5  
6 entity xilly_userlogiccmp_wrapper is
7 port (
8 i_clk : in std_logic;
9 i_rst : in std_logic;
10  
11 user_r_control_r_rden : in std_logic;
12 user_r_control_r_empty : out std_logic := '1';
13 user_r_control_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' );
14  
15 user_w_control_w_wren : in std_logic;
16 user_w_control_w_full : out std_logic := '0';
17 user_w_control_w_data : in std_logic_vector(31 DOWNTO 0);
18  
19 user_r_data1_r_rden : in std_logic;
20 user_r_data1_r_empty : out std_logic := '1';
21 user_r_data1_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' );
22  
23 user_w_data1_w_wren : in std_logic;
24 user_w_data1_w_full : out std_logic := '0';
25 user_w_data1_w_data : in std_logic_vector(31 DOWNTO 0);
26  
27 user_r_data2_r_rden : in std_logic;
28 user_r_data2_r_empty : out std_logic := '1';
29 user_r_data2_r_data : out std_logic_vector(31 DOWNTO 0) := ( others => '0' );
30  
31 user_w_data2_w_wren : in std_logic;
32 user_w_data2_w_full : out std_logic := '0';
33 user_w_data2_w_data : in std_logic_vector(31 DOWNTO 0)
34 );
35 end entity;
36  
37 architecture behavioral of xilly_userlogiccmp_wrapper is
38  
39 component user_logic_cmp
40 port (
41 i_clk : in std_logic;
42 i_rst : in std_logic;
43  
44 -- data1 interface:
45 i_data1in_data : in std_logic_vector( 31 downto 0 );
46 i_data1in_valid : in std_logic;
47 o_data1in_enable : out std_logic;
48 o_data1out_data : out std_logic_vector( 31 downto 0 );
49 o_data1out_valid : out std_logic;
50 i_data1out_enable : in std_logic;
51  
52 -- data2 interface:
53 i_data2in_data : in std_logic_vector( 31 downto 0 );
54 i_data2in_valid : in std_logic;
55 o_data2in_enable : out std_logic := '1';
56 o_data2out_data : out std_logic_vector( 31 downto 0 );
57 o_data2out_valid : out std_logic := '0';
58 i_data2out_enable : in std_logic;
59  
60 -- control interface:
61 i_controlin_data : in std_logic_vector( 31 downto 0 );
62 i_controlin_valid : in std_logic;
63 o_controlin_enable : out std_logic := '1';
64 o_controlout_data : out std_logic_vector( 31 downto 0 );
65 o_controlout_valid : out std_logic := '0';
66 i_controlout_enable : in std_logic
67 );
68 end component;
69  
70 component fifo_32x512
71 port (
72 clk: IN std_logic;
73 srst: IN std_logic;
74 din: IN std_logic_vector(31 downto 0) := ( others => '0' );
75 wr_en: IN std_logic := '0';
76 rd_en: IN std_logic;
77 dout: OUT std_logic_vector(31 downto 0);
78 valid: OUT std_logic;
79 full: OUT std_logic;
80 empty: OUT std_logic
81 );
82 end component;
83  
84 -- data1 signals
85 signal s_data1_ffin2fte_data : std_logic_vector( 31 downto 0 );
86 signal s_data1_ffin2fte_rden : std_logic;
87 signal s_data1_ffin2fte_empty : std_logic;
88  
89 signal s_data1_fte2ul_data : std_logic_vector( 31 downto 0 );
90 signal s_data1_fte2ul_valid : std_logic;
91 signal s_data1_fte2ul_enable : std_logic;
92  
93 signal s_data1_ul2ffout_data : std_logic_vector( 31 downto 0 );
94 signal s_data1_ul2ffout_valid : std_logic;
95 signal s_data1_ul2ffout_enable : std_logic;
96 signal s_data1_ul2ffout_full : std_logic;
97  
98 -- data2 signals
99 signal s_data2_ffin2fte_data : std_logic_vector( 31 downto 0 );
100 signal s_data2_ffin2fte_rden : std_logic;
101 signal s_data2_ffin2fte_empty : std_logic;
102  
103 signal s_data2_fte2ul_data : std_logic_vector( 31 downto 0 );
104 signal s_data2_fte2ul_valid : std_logic;
105 signal s_data2_fte2ul_enable : std_logic;
106  
107 signal s_data2_ul2ffout_data : std_logic_vector( 31 downto 0 );
108 signal s_data2_ul2ffout_valid : std_logic;
109 signal s_data2_ul2ffout_enable : std_logic;
110 signal s_data2_ul2ffout_full : std_logic;
111  
112 -- control signals
113 signal s_control_ffin2fte_data : std_logic_vector( 31 downto 0 );
114 signal s_control_ffin2fte_rden : std_logic;
115 signal s_control_ffin2fte_empty : std_logic;
116  
117 signal s_control_fte2ul_data : std_logic_vector( 31 downto 0 );
118 signal s_control_fte2ul_valid : std_logic;
119 signal s_control_fte2ul_enable : std_logic;
120  
121 signal s_control_ul2ffout_data : std_logic_vector( 31 downto 0 );
122 signal s_control_ul2ffout_valid : std_logic;
123 signal s_control_ul2ffout_enable : std_logic;
124 signal s_control_ul2ffout_full : std_logic;
125  
126 begin
127  
128 ------------------------------------------------------
129  
130 --data1_gen : if( C_USES_DATA1_INTERFACE = '1' ) generate
131 -- FIFO_IN instantiation:
132 data1_fifo_in_inst : fifo_32x512
133 port map (
134 clk => i_clk, srst => i_rst,
135 din => user_w_data1_w_data, wr_en => user_w_data1_w_wren, full => user_w_data1_w_full,
136 dout => s_data1_ffin2fte_data, rd_en => s_data1_ffin2fte_rden, empty => s_data1_ffin2fte_empty,
137 valid => open );
138  
139 -- FIFO_to_enable instantiation:
140 data1_fifo_to_enable_inst : entity fifo_related.fifo_to_enable
141 port map (
142 clk => i_clk, reset => i_rst,
143 din => s_data1_ffin2fte_data, rden => s_data1_ffin2fte_rden, empty => s_data1_ffin2fte_empty,
144 data => s_data1_fte2ul_data, valid => s_data1_fte2ul_valid, enable => s_data1_fte2ul_enable );
145  
146 -- FIFO_OUT instantiation:
147 data1_fifo_out_inst : fifo_32x512
148 port map (
149 clk => i_clk, srst => i_rst,
150 din => s_data1_ul2ffout_data, wr_en => s_data1_ul2ffout_valid, full => s_data1_ul2ffout_full,
151 dout => user_r_data1_r_data, rd_en => user_r_data1_r_rden, empty => user_r_data1_r_empty,
152 valid => open );
153 s_data1_ul2ffout_enable <= not s_data1_ul2ffout_full;
154  
155 -- generate;
156  
157 ------------------------------------------------------
158  
159 --data2_gen : if( C_USES_DATA2_INTERFACE = '1' ) generate
160 -- FIFO_IN instantiation:
161 data2_fifo_in_inst : fifo_32x512
162 port map (
163 clk => i_clk, srst => i_rst,
164 din => user_w_data2_w_data, wr_en => user_w_data2_w_wren, full => user_w_data2_w_full,
165 dout => s_data2_ffin2fte_data, rd_en => s_data2_ffin2fte_rden, empty => s_data2_ffin2fte_empty,
166 valid => open );
167  
168 -- FIFO_to_enable instantiation:
169 data2_fifo_to_enable_inst : entity fifo_related.fifo_to_enable
170 port map (
171 clk => i_clk, reset => i_rst,
172 din => s_data2_ffin2fte_data, rden => s_data2_ffin2fte_rden, empty => s_data2_ffin2fte_empty,
173 data => s_data2_fte2ul_data, valid => s_data2_fte2ul_valid, enable => s_data2_fte2ul_enable );
174  
175 -- FIFO_OUT instantiation:
176 data2_fifo_out_inst : fifo_32x512
177 port map (
178 clk => i_clk, srst => i_rst,
179 din => s_data2_ul2ffout_data, wr_en => s_data2_ul2ffout_valid, full => s_data2_ul2ffout_full,
180 dout => user_r_data2_r_data, rd_en => user_r_data2_r_rden, empty => user_r_data2_r_empty,
181 valid => open );
182 s_data2_ul2ffout_enable <= not s_data2_ul2ffout_full;
183  
184 --end generate;
185  
186 ----------------------------------------------------------
187  
188 --control_gen : if( C_USES_CONTROL_INTERFACE = '1' ) generate
189 -- FIFO_IN instantiation:
190 control_fifo_in_inst : fifo_32x512
191 port map (
192 clk => i_clk, srst => i_rst,
193 din => user_w_control_w_data, wr_en => user_w_control_w_wren, full => user_w_control_w_full,
194 dout => s_control_ffin2fte_data, rd_en => s_control_ffin2fte_rden, empty => s_control_ffin2fte_empty,
195 valid => open );
196  
197 -- FIFO_to_enable instantiation:
198 control_fifo_to_enable_inst : entity fifo_related.fifo_to_enable
199 port map (
200 clk => i_clk, reset => i_rst,
201 din => s_control_ffin2fte_data, rden => s_control_ffin2fte_rden, empty => s_control_ffin2fte_empty,
202 data => s_control_fte2ul_data, valid => s_control_fte2ul_valid, enable => s_control_fte2ul_enable );
203  
204 -- FIFO_OUT instantiation:
205 control_fifo_out_inst : fifo_32x512
206 port map (
207 clk => i_clk, srst => i_rst,
208 din => s_control_ul2ffout_data, wr_en => s_control_ul2ffout_valid, full => s_control_ul2ffout_full,
209 dout => user_r_control_r_data, rd_en => user_r_control_r_rden, empty => user_r_control_r_empty,
210 valid => open );
211 s_control_ul2ffout_enable <= not s_control_ul2ffout_full;
212  
213 --end generate;
214  
215 --------------------------------------------------------------
216  
217 -- user logic:
218 user_logic_cmp_inst : user_logic_cmp
219 port map (
220 i_clk => i_clk,
221 i_rst => i_rst,
222  
223 -- data1 interface:
224 i_data1in_data => s_data1_fte2ul_data,
225 i_data1in_valid => s_data1_fte2ul_valid,
226 o_data1in_enable => s_data1_fte2ul_enable,
227 o_data1out_data => s_data1_ul2ffout_data,
228 o_data1out_valid => s_data1_ul2ffout_valid,
229 i_data1out_enable => s_data1_ul2ffout_enable,
230  
231 -- data2 interface:
232 i_data2in_data => s_data2_fte2ul_data,
233 i_data2in_valid => s_data2_fte2ul_valid,
234 o_data2in_enable => s_data2_fte2ul_enable,
235 o_data2out_data => s_data2_ul2ffout_data,
236 o_data2out_valid => s_data2_ul2ffout_valid,
237 i_data2out_enable => s_data2_ul2ffout_enable,
238  
239 -- control interface:
240 i_controlin_data => s_control_fte2ul_data,
241 i_controlin_valid => s_control_fte2ul_valid,
242 o_controlin_enable => s_control_fte2ul_enable,
243 o_controlout_data => s_control_ul2ffout_data,
244 o_controlout_valid => s_control_ul2ffout_valid,
245 i_controlout_enable => s_control_ul2ffout_enable
246 );
247  
248 end architecture;