Rev Author Line No. Line
4918 kaklik 1 ---------------------------------------------
2 -- glue incoming data (from MSB position)
3 --
4 -- in: D1, D2, D3, D4...
5 -- out: D1D2, D3D4...
6 --
7 --
8 -- NOTE: hardwired for 8 + 8, beware if changing dimensions. swap_endianness only works on 8-bits
9  
10 library ieee;
11 use ieee.std_logic_1164.all;
12  
13 library utilities;
14  
15 entity glue_data is
16 port (
17  
18 i_clk : in std_logic;
19 i_reset_n : in std_logic;
20  
21 i_data : in std_logic_vector( 7 downto 0 );
22 i_valid : in std_logic;
23 o_enable : out std_logic;
24  
25 o_data : out std_logic_vector( 15 downto 0 );
26 o_valid : out std_logic;
27 i_enable : in std_logic
28  
29 );
30  
31 end glue_data;
32  
33 architecture behavioral of glue_data is
34  
35 component swap_endianness
36 port (
37 i_data : in std_logic_vector;
38 o_data : out std_logic_vector
39 );
40 end component;
41  
42 signal s_rst_n : std_logic;
43 signal s_packed_data : std_logic_vector( 15 downto 0 );
44  
45 begin
46  
47 -- pack data:
48 pack_data_inst : entity utilities.pack_data
49 generic map ( G_OUTPUT_WIDTH => 16 )
50 port map (
51 i_clk => i_clk, i_reset_n => i_reset_n,
52 i_data => i_data, i_valid => i_valid, o_enable => o_enable,
53 o_data => s_packed_data, o_valid => o_valid, i_enable => i_enable );
54  
55 -- and swap the bytes to have the first to come on MSB:
56 swap_endianness_inst : swap_endianness
57 port map( i_data => s_packed_data, o_data => o_data );
58  
59 end architecture;
60