Rev Author Line No. Line
4918 kaklik 1 --------------------------------------------
2 -- wrapper for the local oscillator division logic
3 --
4 library ieee;
5 use ieee.std_logic_1164.all;
6  
7 library UNISIM;
8 use UNISIM.vcomponents.all;
9  
10 library sychro1;
11  
12 entity lo_divider_wrapper is
13 generic (
14 G_DIVISOR : integer
15 );
16 port (
17  
18 -- input clock:
19 IN_CLK_LO_N : IN std_logic;
20 IN_CLK_LO_P : IN std_logic;
21  
22 in_clk_enable : in std_logic;
23  
24 -- divided clock
25 OUT_CLK_LO_DIVIDED_N : OUT std_logic;
26 OUT_CLK_LO_DIVIDED_P : OUT std_logic
27  
28 );
29  
30 end lo_divider_wrapper;
31  
32 architecture behavioral of lo_divider_wrapper is
33  
34 -- clock signals for in->divide->out clock:
35 signal s_in_clk_lo : std_logic;
36 signal s_in_clk_lo_bufred : std_logic;
37 signal s_divided_lo : std_logic;
38 attribute clock_signal : string;
39 attribute clock_signal of s_divided_lo : signal is "yes";
40  
41 begin
42  
43 IBUFGDS_inst : IBUFGDS
44 generic map (
45 DIFF_TERM => TRUE
46 --IBUF_LOW_PWR => TRUE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
47 )
48 port map (
49 O => s_in_clk_lo, -- Clock buffer output
50 I => IN_CLK_LO_P, -- Diff_p clock buffer input (connect directly to top-level port)
51 IB => IN_CLK_LO_N -- Diff_n clock buffer input (connect directly to top-level port)
52 );
53  
54 -- TEST2: misto counteru pouziju deleni v BUFR
55 BUFR_inst : BUFR
56 generic map (
57 BUFR_DIVIDE => "BYPASS", -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
58 SIM_DEVICE => "VIRTEX6") -- Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6"
59 port map (
60 O => s_in_clk_lo_bufred, -- Clock buffer output
61 CE => in_clk_enable, -- Clock enable input
62 CLR => '0', -- Clock buffer reset input
63 I => s_in_clk_lo -- Clock buffer input
64 );
65  
66 -- TEST3: opravil jsem clock_divider, zkusim ho sem dat zpatky
67 -- -> BUFR -> BYPASS
68 -- zpatky clock_divider
69  
70 -- TEMP1: vyhozeni counteru
71 divider_inst : entity sychro1.clock_divider
72 generic map( G_DIVISOR => G_DIVISOR )
73 port map( i_clk => s_in_clk_lo_bufred, i_rst => '0', o_clk => s_divided_lo );
74 --s_divided_lo <= s_in_clk_lo_bufred;
75  
76 OBUFDS_inst : OBUFDS
77 generic map (
78 IOSTANDARD => "DEFAULT" )
79 port map (
80 O => OUT_CLK_LO_DIVIDED_P, -- Diff_p output (connect directly to top-level port)
81 OB => OUT_CLK_LO_DIVIDED_N, -- Diff_n output (connect directly to top-level port)
82 I => s_divided_lo -- Buffer input
83 );
84  
85 end architecture;
86