Rev Author Line No. Line
4918 kaklik 1 -- file: selectio_iserdes_8bit_ddr_diffin.vhd
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47 ------------------------------------------------------------------------------
48 -- User entered comments
49 ------------------------------------------------------------------------------
50 -- None
51 ------------------------------------------------------------------------------
52 --
53 -- EDIT: the clocking logic has been moved outside
54  
55  
56 library ieee;
57 use ieee.std_logic_1164.all;
58 use ieee.std_logic_unsigned.all;
59 use ieee.std_logic_arith.all;
60 use ieee.std_logic_misc.all;
61 use ieee.numeric_std.all;
62  
63 library unisim;
64 use unisim.vcomponents.all;
65  
66 entity myserdes_ddr is
67 generic
68 (-- width of the data for the system
69 sys_w : integer := 1;
70 -- width of the data for the device
71 dev_w : integer := 8);
72 port
73 (
74 -- From the system into the device
75 DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0);
76 DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0);
77 DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0);
78  
79 BITSLIP : in std_logic; -- Bitslip module is enabled in NETWORKING mode
80 -- User should tie it to '0' if not needed
81  
82 -- Clock and reset signals
83 CLK_IN : in std_logic; -- Fast clock from IOB, after IBUFGDS and BUFIO
84 CLK_DIV_IN : in std_logic; -- Divided fast clock from IBUFGDS and BUFR
85  
86 IO_RESET : in std_logic); -- Reset signal for IO circuit
87 end myserdes_ddr;
88  
89 architecture xilinx of myserdes_ddr is
90 attribute CORE_GENERATION_INFO : string;
91 attribute CORE_GENERATION_INFO of xilinx : architecture is "selectio_iserdes_8bit_ddr_diffin,selectio_wiz_v4_1,{component_name=selectio_iserdes_8bit_ddr_diffin,bus_dir=INPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=true,use_phase_detector=false,serialization_factor=8,enable_bitslip=false,enable_train=false,system_data_width=1,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=DIFF,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,v6_bus_in_delay=NONE,v6_bus_out_delay=NONE,v6_clk_buf=BUFIO,v6_active_edge=DDR,v6_ddr_alignment=SAME_EDGE_PIPELINED,v6_oddr_alignment=SAME_EDGE,ddr_alignment=C0,v6_interface_type=NETWORKING,interface_type=NETWORKING,v6_bus_in_tap=0,v6_bus_out_tap=0,v6_clk_io_std=LVDS_25,v6_clk_sig_type=DIFF}";
92 constant clock_enable : std_logic := '1';
93 signal unused : std_logic;
94  
95  
96 -- After the buffer
97 signal data_in_from_pins_int : std_logic_vector(sys_w-1 downto 0);
98 -- Between the delay and serdes
99 signal data_in_from_pins_delay : std_logic_vector(sys_w-1 downto 0);
100 constant num_serial_bits : integer := dev_w/sys_w;
101 type serdarr is array (0 to 9) of std_logic_vector(sys_w-1 downto 0);
102 -- Array to use intermediately from the serdes to the internal
103 -- devices. bus "0" is the leftmost bus
104 -- * fills in starting with 0
105 signal iserdes_q : serdarr := (( others => (others => '0')));
106 signal serdesstrobe : std_logic;
107 signal icascade1 : std_logic_vector(sys_w-1 downto 0);
108 signal icascade2 : std_logic_vector(sys_w-1 downto 0);
109 signal clk_in_inv : std_logic;
110  
111  
112  
113 begin
114  
115 -- We have multiple bits- step over every bit, instantiating the required elements
116 pins: for pin_count in 0 to sys_w-1 generate
117 begin
118 -- Instantiate the buffers
119 ----------------------------------
120 -- Instantiate a buffer for every bit of the data bus
121 ibufds_inst : IBUFDS
122 generic map (
123 DIFF_TERM => TRUE, -- Differential termination
124 IOSTANDARD => "LVDS_25")
125 port map (
126 I => DATA_IN_FROM_PINS_P (pin_count),
127 IB => DATA_IN_FROM_PINS_N (pin_count),
128 O => data_in_from_pins_int(pin_count));
129  
130  
131 -- Pass through the delay
132 -----------------------------------
133 data_in_from_pins_delay(pin_count) <= data_in_from_pins_int(pin_count);
134  
135 -- Instantiate the serdes primitive
136 ----------------------------------
137  
138 clk_in_inv <= not (CLK_IN);
139  
140 -- declare the iserdes
141 iserdese1_master : ISERDESE1
142 generic map (
143 DATA_RATE => "DDR",
144 DATA_WIDTH => 8,
145 INTERFACE_TYPE => "NETWORKING",
146 DYN_CLKDIV_INV_EN => FALSE,
147 DYN_CLK_INV_EN => FALSE,
148 NUM_CE => 2,
149  
150 OFB_USED => FALSE,
151 IOBDELAY => "NONE", -- Use input at D to output the data on Q1-Q6
152 SERDES_MODE => "MASTER")
153 port map (
154 Q1 => iserdes_q(0)(pin_count),
155 Q2 => iserdes_q(1)(pin_count),
156 Q3 => iserdes_q(2)(pin_count),
157 Q4 => iserdes_q(3)(pin_count),
158 Q5 => iserdes_q(4)(pin_count),
159 Q6 => iserdes_q(5)(pin_count),
160 SHIFTOUT1 => icascade1(pin_count), -- Cascade connection to Slave ISERDES
161 SHIFTOUT2 => icascade2(pin_count), -- Cascade connection to Slave ISERDES
162 BITSLIP => BITSLIP, -- 1-bit Invoke Bitslip. This can be used with any
163 -- DATA_WIDTH, cascaded or not.
164 CE1 => clock_enable, -- 1-bit Clock enable input
165 CE2 => clock_enable, -- 1-bit Clock enable input
166 CLK => CLK_IN, -- Fast Source Synchronous SERDES clock from BUFIO
167 CLKB => clk_in_inv, -- Locally inverted clock
168 CLKDIV => CLK_DIV_IN, -- Slow clock driven by BUFR
169 D => data_in_from_pins_delay(pin_count), -- 1-bit Input signal from IOB.
170 DDLY => '0',
171 RST => IO_RESET, -- 1-bit Asynchronous reset only.
172 SHIFTIN1 => '0',
173 SHIFTIN2 => '0',
174 -- unused connections
175 DYNCLKDIVSEL => '0',
176 DYNCLKSEL => '0',
177 OFB => '0',
178 OCLK => '0',
179 O => open); -- unregistered output of ISERDESE1
180  
181 iserdese1_slave : ISERDESE1
182 generic map (
183 DATA_RATE => "DDR",
184 DATA_WIDTH => 8,
185 INTERFACE_TYPE => "NETWORKING",
186 DYN_CLKDIV_INV_EN => FALSE,
187 DYN_CLK_INV_EN => FALSE,
188 NUM_CE => 2,
189  
190 OFB_USED => FALSE,
191 IOBDELAY => "NONE", -- Use input at D to output the data on Q1-Q6
192 SERDES_MODE => "SLAVE")
193 port map (
194 Q1 => open,
195 Q2 => open,
196 Q3 => iserdes_q(6)(pin_count),
197 Q4 => iserdes_q(7)(pin_count),
198 Q5 => iserdes_q(8)(pin_count),
199 Q6 => iserdes_q(9)(pin_count),
200 SHIFTOUT1 => open,
201 SHIFTOUT2 => open,
202 SHIFTIN1 => icascade1(pin_count), -- Cascade connections from Master ISERDES
203 SHIFTIN2 => icascade2(pin_count), -- Cascade connections from Master ISERDES
204 BITSLIP => BITSLIP, -- 1-bit Invoke Bitslip. This can be used with any
205 -- DATA_WIDTH, cascaded or not.
206 CE1 => clock_enable, -- 1-bit Clock enable input
207 CE2 => clock_enable, -- 1-bit Clock enable input
208 CLK => CLK_IN, -- Fast source synchronous serdes clock
209 CLKB => clk_in_inv, -- locally inverted clock
210 CLKDIV => CLK_DIV_IN, -- Slow clock sriven by BUFR.
211 D => '0', -- Slave ISERDES module. No need to connect D, DDLY
212 DDLY => '0',
213 RST => IO_RESET, -- 1-bit Asynchronous reset only.
214 -- unused connections
215 DYNCLKDIVSEL => '0',
216 DYNCLKSEL => '0',
217 OFB => '0',
218 OCLK => '0',
219 O => open); -- unregistered output of ISERDESE1
220  
221 -- Concatenate the serdes outputs together. Keep the timesliced
222 -- bits together, and placing the earliest bits on the right
223 -- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
224 -- the output will be 3210, 7654, ...
225 -------------------------------------------------------------
226  
227 in_slices: for slice_count in 0 to num_serial_bits-1 generate begin
228 -- This places the first data in time on the right
229 -- DATA_IN_TO_DEVICE(slice_count) <=
230 -- iserdes_q(num_serial_bits-slice_count-1)(0);
231 -- To place the first data in time on the left, use the
232 -- following code, instead
233 DATA_IN_TO_DEVICE(slice_count) <=
234 iserdes_q(slice_count)(0);
235 end generate in_slices;
236  
237  
238 end generate pins;
239  
240  
241  
242  
243  
244 end xilinx;
245  
246  
247