Rev Author Line No. Line
4918 kaklik 1 library ieee;
2 use ieee.std_logic_1164.all;
3  
4 library UNISIM;
5 use UNISIM.vcomponents.all;
6  
7 library utilities;
8  
9 entity processing_block is
10 port (
11  
12 -- clock:
13 clk_iserdes_in : in std_logic;
14 clk_iserdes_in_div : in std_logic;
15 clk_global : in std_logic;
16  
17 -- reset:
18 rst : in std_logic;
19  
20 -- bitslip:
21 bitslip : in std_logic;
22 bitslip_done : in std_logic; -- todo: use this
23 bitslip_drop_byte : in std_logic;
24  
25 -- input signal:
26 in_data_p : in std_logic;
27 in_data_n : in std_logic;
28 in_data_swap_pn : in std_logic;
29  
30 -- input switch for counter output:
31 in_output_counting : in std_logic;
32  
33 -- output after iserdes and pack16 for bitslip:
34 o_iserdes_output : out std_logic_vector( 15 downto 0 );
35 o_iserdes_output_valid : out std_logic;
36  
37 -- output fwft FIFO:
38 o_data : out std_logic_vector( 31 downto 0 );
39 o_valid : out std_logic;
40 i_rden : in std_logic
41 );
42  
43 end processing_block;
44  
45 architecture behavioral of processing_block is
46  
47 component swap_endianness
48 port (
49 i_data : in std_logic_vector;
50 o_data : out std_logic_vector
51 );
52 end component;
53  
54 component fifo_32x512_dualclk_fwft
55 port (
56 rst : in std_logic;
57 wr_clk : in std_logic;
58 rd_clk : in std_logic;
59 din : in std_logic_vector(31 downto 0);
60 wr_en : in std_logic;
61 rd_en : in std_logic;
62 dout : out std_logic_vector(31 downto 0);
63 full : out std_logic;
64 empty : out std_logic;
65 valid : out std_logic
66 );
67 end component;
68  
69 component myserdes_ddr_wrapper
70 generic
71 ( sys_w : integer := 1;
72 dev_w : integer := 8);
73 port (
74 -- CLOCK:
75 clk_in : in std_logic;
76 clk_in_div : in std_logic;
77 -- PADS IN:
78 data_in_from_pins_p : in std_logic;
79 data_in_from_pins_n : in std_logic;
80 -- DATA OUT:
81 data_in_to_device : out std_logic_vector( dev_w - 1 downto 0 );
82  
83 bitslip : in std_logic;
84 rst_in : in std_logic );
85 end component;
86  
87 component saw_generator_wrapper
88 generic (
89 G_INCREASE_EVERY_NTH : positive := 4
90 );
91 port (
92  
93 i_clk : in std_logic;
94 i_rst : in std_logic;
95  
96 o_valid : out std_logic;
97 o_data : out std_logic_vector
98  
99 );
100 end component;
101  
102 -- Frame signal
103 signal s_in_frame_for_data : std_logic_vector( 7 downto 0 );
104 signal s_in_frame_for_data_precorrect : std_logic_vector( 7 downto 0 );
105  
106 signal s_in_frame_for_data_packed16 : std_logic_vector( 15 downto 0 );
107 signal s_in_frame_for_data_packed16_le : std_logic_vector( 15 downto 0 );
108 signal s_in_frame_for_data_packed16_swapped : std_logic_vector( 15 downto 0 );
109 signal s_in_frame_for_data_packed16_valid : std_logic;
110 signal s_in_frame_for_data_packed16_valid_wbitslip_done : std_logic;
111 signal s_in_frame_for_data_packed32 : std_logic_vector( 31 downto 0 );
112 signal s_in_frame_for_data_packed32_valid : std_logic;
113  
114 signal s_rst_n : std_logic;
115  
116 -- counter:
117 signal s_counter_valid : std_logic;
118 signal s_counter_data : std_logic_vector( 31 downto 0 );
119  
120 -- selection signals for the final FIFO:
121 signal s_selected_source_valid : std_logic;
122 signal s_selected_source_data : std_logic_vector( 31 downto 0 );
123  
124 -- byte drop request
125 signal s_bitslip_drop_byte_n : std_logic;
126  
127 begin
128  
129 s_rst_n <= not rst;
130 s_bitslip_drop_byte_n <= not bitslip_drop_byte;
131  
132 -- iserdes wrapper:
133 myserdes_ddr_wrapper_inst : myserdes_ddr_wrapper
134 port map (
135 clk_in => clk_iserdes_in, clk_in_div => clk_iserdes_in_div,
136 data_in_from_pins_p => in_data_p, data_in_from_pins_n => in_data_n, data_in_to_device => s_in_frame_for_data_precorrect,
137 bitslip => bitslip, rst_in => rst );
138  
139 -- correct hardware swapping of P&N wires:
140 s_in_frame_for_data <= s_in_frame_for_data_precorrect when in_data_swap_pn = '0' else
141 not s_in_frame_for_data_precorrect;
142  
143 -- glue two parts to 16-bit full data:
144 glue_data_inst : entity work.glue_data
145 port map (
146 i_clk => clk_iserdes_in_div, i_reset_n => s_rst_n,
147 i_data => s_in_frame_for_data, i_valid => s_bitslip_drop_byte_n, o_enable => open,
148 o_data => s_in_frame_for_data_packed16, o_valid => s_in_frame_for_data_packed16_valid, i_enable => '1' );
149  
150 -- output the 16-bit to manage bitslip:
151 o_iserdes_output <= s_in_frame_for_data_packed16;
152 o_iserdes_output_valid <= s_in_frame_for_data_packed16_valid;
153  
154 -- these data go further after bitslip has been set:
155 s_in_frame_for_data_packed16_le <= s_in_frame_for_data_packed16;
156 s_in_frame_for_data_packed16_valid_wbitslip_done <= bitslip_done and s_in_frame_for_data_packed16_valid;
157  
158 -- insert the pack block to 32 bits:
159 pack_data32_inst : entity utilities.pack_data
160 generic map (
161 G_OUTPUT_WIDTH => 32 )
162 port map (
163 i_clk => clk_iserdes_in_div, i_reset_n => s_rst_n,
164 i_data => s_in_frame_for_data_packed16_le, i_valid => s_in_frame_for_data_packed16_valid_wbitslip_done, o_enable => open,
165 o_data => s_in_frame_for_data_packed32, o_valid => s_in_frame_for_data_packed32_valid, i_enable => '1' );
166  
167 -- counter:
168 counter_inst : saw_generator_wrapper
169 generic map( G_INCREASE_EVERY_NTH => 4 )
170 port map(
171 i_clk => clk_iserdes_in_div, i_rst => rst, o_valid => s_counter_valid, o_data => s_counter_data );
172  
173 -- output either the grabbed data or the counter, based on request:
174 s_selected_source_valid <= s_counter_valid when in_output_counting = '1' else s_in_frame_for_data_packed32_valid;
175 s_selected_source_data <= s_counter_data when in_output_counting = '1' else s_in_frame_for_data_packed32;
176  
177 -- insert the cross-domain FIFO:
178 cross_domain_fifo_inst : fifo_32x512_dualclk_fwft
179 port map (
180 rst => rst, wr_clk => clk_iserdes_in_div, rd_clk => clk_global,
181 din => s_selected_source_data, wr_en => s_selected_source_valid, full => open,
182 dout => o_data, valid => o_valid, rd_en => i_rden, empty => open );
183  
184 end architecture;
185