Rev Author Line No. Line
3641 kaklik 1 ---------------------------------------------
2 -- increase output every fourth clock cycle
3 --
4  
5 library ieee;
6 use ieee.std_logic_1164.all;
7 use ieee.numeric_std.all;
8  
9 library sychro1;
10  
11 entity saw_generator_wrapper is
12 generic (
13 G_INCREASE_EVERY_NTH : positive := 4
14 );
15 port (
16  
17 i_clk : in std_logic;
18 i_rst : in std_logic;
19  
20 o_valid : out std_logic;
21 o_data : out std_logic_vector
22  
23 );
24 end saw_generator_wrapper;
25  
26 architecture behavioral of saw_generator_wrapper is
27  
28 signal s_modulo_counter_carry : std_logic;
29  
30 begin
31  
32 -- first counter that counts modulo G_INCREASE_EVERY_NTH to generate a valid signal for the second counter
33 -- and the output:
34 modulo_up_counter : entity sychro1.up_counter
35 generic map ( G_MIN_NUMBER => 0, G_MAX_NUMBER => G_INCREASE_EVERY_NTH - 1 )
36 port map ( i_clk => i_clk, i_rst => i_rst, i_valid => '1', o_data => open, o_carry => s_modulo_counter_carry );
37  
38 -- the second counter:
39 main_up_counter : entity sychro1.up_counter_stdlv
40 generic map ( G_BITS => o_data'length, G_MIN_NUMBER => ( o_data'range => '0' ), G_MAX_NUMBER => ( o_data'range => '1' ) )
41 port map( i_clk => i_clk, i_rst => i_rst, i_valid => s_modulo_counter_carry, o_data => o_data, o_carry => open );
42  
43 -- signal connection:
44 o_valid <= s_modulo_counter_carry;
45  
46 end architecture;
47