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kakl |
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# Board: www.mlab.cz S3AN01A |
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# Device: XC3S50AN-4C |
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# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes |
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# Main Clock (Embedded 100MHz board oscillator) |
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NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33; |
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#NET "CLK100MHz" LOC = P125 | IOSTANDARD = LVCMOS33; |
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NET "CLK100MHz" TNM_NET = CLK100MHz; |
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TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%; |
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NET "LO_CLOCK" TNM_NET = LO_CLOCK; |
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kakl |
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TIMESPEC TS_LO_CLOCK = PERIOD "LO_CLOCK" 5.2 ns HIGH 50%; |
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kakl |
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# For DCM connection across the whole chip |
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NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE; |
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NET "PS2_CLK2" CLOCK_DEDICATED_ROUTE = FALSE; |
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# Mode signals |
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NET "M[0]" LOC = P38 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "M[1]" LOC = P37 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M1 and M2 for boot from external SPI Flash Memory |
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NET "M[2]" LOC = P39 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Use jumper on M2 for boot from internal Flash memory |
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# SPI Flash Vendor Mode Select (for external SPI boot Flash) |
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NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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# DIP Switches (positive signals with pull-down) |
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NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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# Push Buttons (positive signals with pull-down) |
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NET "PB[0]" LOC = P121 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "PB[1]" LOC = P120 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "PB[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "PB[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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# LED String (positive output signals) |
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NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33; |
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NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33; |
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NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33; |
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NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33; |
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NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33; |
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NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33; |
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NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33; |
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NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33; |
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# LED Display Output Signals (negative, multiplexed) |
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NET "LD_A_n" LOC = P15 |IOSTANDARD = LVCMOS33; |
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NET "LD_B_n" LOC = P30 |IOSTANDARD = LVCMOS33; |
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NET "LD_C_n" LOC = P21 |IOSTANDARD = LVCMOS33; |
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NET "LD_D_n" LOC = P19 |IOSTANDARD = LVCMOS33; |
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NET "LD_E_n" LOC = P18 |IOSTANDARD = LVCMOS33; |
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NET "LD_F_n" LOC = P16 |IOSTANDARD = LVCMOS33; |
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NET "LD_G_n" LOC = P24 |IOSTANDARD = LVCMOS33; |
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NET "LD_DP_n" LOC = P20 |IOSTANDARD = LVCMOS33; |
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NET "LD_0_n" LOC = P25 |IOSTANDARD = LVCMOS33; |
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NET "LD_1_n" LOC = P31 |IOSTANDARD = LVCMOS33; |
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NET "LD_2_n" LOC = P32 |IOSTANDARD = LVCMOS33; |
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NET "LD_3_n" LOC = P13 |IOSTANDARD = LVCMOS33; # !!! Connect U1.13 with U1.33 |
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NET "LD_4_n" LOC = P27 |IOSTANDARD = LVCMOS33; |
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NET "LD_5_n" LOC = P29 |IOSTANDARD = LVCMOS33; |
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NET "LD_6_n" LOC = P28 |IOSTANDARD = LVCMOS33; |
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NET "LD_7_n" LOC = P12 |IOSTANDARD = LVCMOS33; # !!! Connect U1.12 with U1.35 |
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# VGA Analog Display Connection (outputs) |
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NET "VGA_R[0]" LOC = P3 |IOSTANDARD = LVCMOS33; |
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NET "VGA_R[1]" LOC = P4 |IOSTANDARD = LVCMOS33; |
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NET "VGA_G[0]" LOC = P5 |IOSTANDARD = LVCMOS33; |
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NET "VGA_G[1]" LOC = P6 |IOSTANDARD = LVCMOS33; |
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NET "VGA_B[0]" LOC = P7 |IOSTANDARD = LVCMOS33; |
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NET "VGA_B[1]" LOC = P8 |IOSTANDARD = LVCMOS33; |
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NET "VGA_VS" LOC = P10 |IOSTANDARD = LVCMOS33; |
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NET "VGA_HS" LOC = P11 |IOSTANDARD = LVCMOS33; |
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# Bank 1 Port (input for tests, pull-up) |
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NET "B[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "B[24]" LOC = P97 |IOSTANDARD = LVCMOS33 |PULLUP = YES; # Connected with B[23] on PCB |
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# PS/2 Bidirectional Port (open collector, J31 and J32) |
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#NET "PS2_CLK1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # S3AN01A PCB Design has bug so these pins |
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#NET "PS2_DATA1" LOC = P | IOSTANDARD = LVCMOS33 | PULLUP = YES; # will be assinged after PCB redesign |
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NET "PS2_CLK2" LOC = P42 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "PS2_DATA2" LOC = P58 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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# Diferencial Signals on 4 pin header (J7) |
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NET "DIF1P" LOC = P110 |IOSTANDARD = LVCMOS33 ; |
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NET "DIF1N" LOC = P111 |IOSTANDARD = LVCMOS33 ; |
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NET "DIF2P" LOC = P112 |IOSTANDARD = LVCMOS33 ; |
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NET "DIF2N" LOC = P113 |IOSTANDARD = LVCMOS33 ; |
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# I2C Signals (on connector J30) |
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NET "I2C_SCL" LOC = P115 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "I2C_SDA" LOC = P114 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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# Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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NET "SD1AP" LOC = P54 |IOSTANDARD = LVPECL_33; |
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NET "SD1AN" LOC = P55 |IOSTANDARD = LVPECL_33; |
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NET "SD1BP" LOC = P59 |IOSTANDARD = LVCMOS33 ; |
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NET "SD1BN" LOC = P57 |IOSTANDARD = LVCMOS33 ; |
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NET "SD2AP" LOC = P124 |IOSTANDARD = LVDS_33 ; |
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NET "SD2AN" LOC = P126 |IOSTANDARD = LVDS_33 ; |
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NET "SD2BP" LOC = P131 |IOSTANDARD = LVCMOS33 ; |
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NET "SD2BN" LOC = P129 |IOSTANDARD = LVCMOS33 ; |
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# SPI Memory Interface |
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NET "SPI_CS_n" LOC = P41 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "SPI_DO" LOC = P71 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "SPI_DI" LOC = P62 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "SPI_CLK" LOC = P72 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "SPI_WP_n" LOC = P70 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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# Analog In Out |
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NET "ANA_OUTD" LOC = P67 |IOSTANDARD = LVCMOS33; |
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NET "ANA_REFD" LOC = P68 |IOSTANDARD = LVCMOS33; |
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NET "ANA_IND" LOC = P69 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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/* |
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# Used Signals (test points) |
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NET "TPS1" LOC = P53 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
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NET "TPS2" LOC = P125 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
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NET "TPS3" LOC = P127 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
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NET "TPS4" LOC = P130 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
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NET "TPS5" LOC = P141 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
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NET "TPS6" LOC = P123 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; |
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NET "XXX1" LOC = P33 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only |
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NET "XXX2" LOC = P35 | IOSTANDARD = LVCMOS33 | PULLDOWN = YES; # input only |
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*/ |