Rev Author Line No. Line
2971 jichapav 1 /*
2 ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
3 2011,2012 Giovanni Di Sirio.
4  
5 This file is part of ChibiOS/RT.
6  
7 ChibiOS/RT is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11  
12 ChibiOS/RT is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16  
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>.
19  
20 ---
21  
22 A special exception to the GPL can be applied should you wish to distribute
23 a combined work that includes ChibiOS/RT, without being obliged to provide
24 the source code for any proprietary components. See the file exception.txt
25 for full details of how and when the exception can be applied.
26 */
27  
28 /*
29 * STM32F1xx drivers configuration.
30 * The following settings override the default settings present in
31 * the various device driver implementation headers.
32 * Note that the settings for each driver only have effect if the whole
33 * driver is enabled in halconf.h.
34 *
35 * IRQ priorities:
36 * 15...0 Lowest...Highest.
37 *
38 * DMA priorities:
39 * 0...3 Lowest...Highest.
40 */
41  
42 #define STM32F103_MCUCONF
43  
44 /*
45 * HAL driver system settings.
46 */
47 #define STM32_NO_INIT FALSE
48 #define STM32_HSI_ENABLED TRUE
49 #define STM32_LSI_ENABLED FALSE
50 #define STM32_HSE_ENABLED TRUE
51 #define STM32_LSE_ENABLED FALSE
52 #define STM32_SW STM32_SW_PLL
53 #define STM32_PLLSRC STM32_PLLSRC_HSE
54 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
55 #define STM32_PLLMUL_VALUE 9
56 #define STM32_HPRE STM32_HPRE_DIV1
57 #define STM32_PPRE1 STM32_PPRE1_DIV2
58 #define STM32_PPRE2 STM32_PPRE2_DIV2
59 #define STM32_ADCPRE STM32_ADCPRE_DIV4
60 #define STM32_USB_CLOCK_REQUIRED TRUE
61 #define STM32_USBPRE STM32_USBPRE_DIV1P5
62 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
63 #define STM32_RTCSEL STM32_RTCSEL_HSEDIV
64 #define STM32_PVD_ENABLE FALSE
65 #define STM32_PLS STM32_PLS_LEV0
66  
67 /*
68 * ADC driver system settings.
69 */
70 #define STM32_ADC_USE_ADC1 TRUE
71 #define STM32_ADC_ADC1_DMA_PRIORITY 2
72 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
73  
74 /*
75 * CAN driver system settings.
76 */
77 #define STM32_CAN_USE_CAN1 TRUE
78 #define STM32_CAN_CAN1_IRQ_PRIORITY 11
79  
80 /*
81 * EXT driver system settings.
82 */
83 #define STM32_EXT_EXTI0_IRQ_PRIORITY 6
84 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6
85 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6
86 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6
87 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6
88 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
89 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
90 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6
91 #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
92 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
93 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
94  
95 /*
96 * GPT driver system settings.
97 */
98 #define STM32_GPT_USE_TIM1 FALSE
99 #define STM32_GPT_USE_TIM2 TRUE
100 #define STM32_GPT_USE_TIM3 FALSE
101 #define STM32_GPT_USE_TIM4 FALSE
102 #define STM32_GPT_USE_TIM5 FALSE
103 #define STM32_GPT_USE_TIM8 FALSE
104 #define STM32_GPT_TIM1_IRQ_PRIORITY 7
105 #define STM32_GPT_TIM2_IRQ_PRIORITY 7
106 #define STM32_GPT_TIM3_IRQ_PRIORITY 7
107 #define STM32_GPT_TIM4_IRQ_PRIORITY 7
108 #define STM32_GPT_TIM5_IRQ_PRIORITY 7
109 #define STM32_GPT_TIM8_IRQ_PRIORITY 7
110  
111 /*
112 * I2C driver system settings.
113 */
114 #define STM32_I2C_USE_I2C1 FALSE
115 #define STM32_I2C_USE_I2C2 FALSE
116 #define STM32_I2C_USE_I2C3 FALSE
117 #define STM32_I2C_I2C1_IRQ_PRIORITY 10
118 #define STM32_I2C_I2C2_IRQ_PRIORITY 10
119 #define STM32_I2C_I2C3_IRQ_PRIORITY 10
120 #define STM32_I2C_I2C1_DMA_PRIORITY 1
121 #define STM32_I2C_I2C2_DMA_PRIORITY 1
122 #define STM32_I2C_I2C3_DMA_PRIORITY 1
123 #define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
124 #define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
125 #define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
126  
127 /*
128 * ICU driver system settings.
129 */
130 #define STM32_ICU_USE_TIM1 FALSE
131 #define STM32_ICU_USE_TIM2 FALSE
132 #define STM32_ICU_USE_TIM3 FALSE
133 #define STM32_ICU_USE_TIM4 FALSE
134 #define STM32_ICU_USE_TIM5 FALSE
135 #define STM32_ICU_USE_TIM8 FALSE
136 #define STM32_ICU_TIM1_IRQ_PRIORITY 7
137 #define STM32_ICU_TIM2_IRQ_PRIORITY 7
138 #define STM32_ICU_TIM3_IRQ_PRIORITY 7
139 #define STM32_ICU_TIM4_IRQ_PRIORITY 7
140 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
141 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
142  
143 /*
144 * PWM driver system settings.
145 */
146 #define STM32_PWM_USE_ADVANCED FALSE
147 #define STM32_PWM_USE_TIM1 FALSE
148 #define STM32_PWM_USE_TIM2 FALSE
149 #define STM32_PWM_USE_TIM3 TRUE
150 #define STM32_PWM_USE_TIM4 TRUE
151 #define STM32_PWM_USE_TIM5 FALSE
152 #define STM32_PWM_USE_TIM8 FALSE
153 #define STM32_PWM_TIM1_IRQ_PRIORITY 7
154 #define STM32_PWM_TIM2_IRQ_PRIORITY 7
155 #define STM32_PWM_TIM3_IRQ_PRIORITY 7
156 #define STM32_PWM_TIM4_IRQ_PRIORITY 7
157 #define STM32_PWM_TIM5_IRQ_PRIORITY 7
158 #define STM32_PWM_TIM8_IRQ_PRIORITY 7
159  
160 /*
161 * RTC driver system settings.
162 */
163 #define STM32_RTC_IRQ_PRIORITY 15
164  
165 /*
166 * SERIAL driver system settings.
167 */
168 #define STM32_SERIAL_USE_USART1 TRUE
169 #define STM32_SERIAL_USE_USART2 TRUE
170 #define STM32_SERIAL_USE_USART3 FALSE
171 #define STM32_SERIAL_USE_UART4 FALSE
172 #define STM32_SERIAL_USE_UART5 FALSE
173 #define STM32_SERIAL_USE_USART6 FALSE
174 #define STM32_SERIAL_USART1_PRIORITY 12
175 #define STM32_SERIAL_USART2_PRIORITY 12
176 #define STM32_SERIAL_USART3_PRIORITY 12
177 #define STM32_SERIAL_UART4_PRIORITY 12
178 #define STM32_SERIAL_UART5_PRIORITY 12
179 #define STM32_SERIAL_USART6_PRIORITY 12
180  
181 /*
182 * SPI driver system settings.
183 */
184 #define STM32_SPI_USE_SPI1 FALSE
185 #define STM32_SPI_USE_SPI2 FALSE
186 #define STM32_SPI_USE_SPI3 FALSE
187 #define STM32_SPI_SPI1_DMA_PRIORITY 1
188 #define STM32_SPI_SPI2_DMA_PRIORITY 1
189 #define STM32_SPI_SPI3_DMA_PRIORITY 1
190 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
191 #define STM32_SPI_SPI2_IRQ_PRIORITY 10
192 #define STM32_SPI_SPI3_IRQ_PRIORITY 10
193 #define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
194  
195 /*
196 * UART driver system settings.
197 */
198 #define STM32_UART_USE_USART1 FALSE
199 #define STM32_UART_USE_USART2 FALSE
200 #define STM32_UART_USE_USART3 FALSE
201 #define STM32_UART_USART1_IRQ_PRIORITY 12
202 #define STM32_UART_USART2_IRQ_PRIORITY 12
203 #define STM32_UART_USART3_IRQ_PRIORITY 12
204 #define STM32_UART_USART1_DMA_PRIORITY 0
205 #define STM32_UART_USART2_DMA_PRIORITY 0
206 #define STM32_UART_USART3_DMA_PRIORITY 0
207 #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
208  
209 /*
210 * USB driver system settings.
211 */
212 #define STM32_USB_USE_USB1 TRUE
213 #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
214 #define STM32_USB_USB1_HP_IRQ_PRIORITY 6
215 #define STM32_USB_USB1_LP_IRQ_PRIORITY 14