Rev Author Line No. Line
3201 kakl 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO.
4 --
5 -- HW Design Name: S3AN01A
6 -- Project Name: Atomic Counter
7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3
3205 kakl 9 -- Description: Counter up to 640 MHz synchonised by GPS.
10 -- Output frequency is displayed on the 7seg. LED display.
11 -- You can choice half or full frequency by DIPSW7.
3201 kakl 12 --
13 -- Dependencies: TTLPECL01A, GPS01A
14 --
15 -- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $
16 --
17 ----------------------------------------------------------------------------------
18  
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.numeric_std.ALL;
22  
23 library UNISIM;
24 use UNISIM.vcomponents.all;
25  
26 entity AtomicCounter is
27 generic (
28 -- Top Value for 100MHz Clock Counter
29 MAXCOUNT: integer := 10_000; -- Maximum for the first counter
30 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
31 );
32 port (
33 -- Clock on PCB
34 CLK100MHz: in std_logic;
35  
36 -- Mode Signals (usualy not used)
37 M: in std_logic_vector(2 downto 0);
38 VS: in std_logic_vector(2 downto 0);
39  
40 -- Dipswitch Inputs
41 DIPSW: in std_logic_vector(7 downto 0);
42  
43 -- Push Buttons
44 PB: in std_logic_vector(3 downto 0);
45  
46 -- LED Bar Outputs
47 LED: out std_logic_vector(7 downto 0);
48  
49 -- LED Display (8 digit with 7 segments and ddecimal point)
50 LD_A_n: out std_logic;
51 LD_B_n: out std_logic;
52 LD_C_n: out std_logic;
53 LD_D_n: out std_logic;
54 LD_E_n: out std_logic;
55 LD_F_n: out std_logic;
56 LD_G_n: out std_logic;
57 LD_DP_n: out std_logic;
58 LD_0_n: out std_logic;
59 LD_1_n: out std_logic;
60 LD_2_n: out std_logic;
61 LD_3_n: out std_logic;
62 LD_4_n: out std_logic;
63 LD_5_n: out std_logic;
64 LD_6_n: out std_logic;
65 LD_7_n: out std_logic;
66  
67 -- VGA Video Out Port
68 VGA_R: out std_logic_vector(1 downto 0);
69 VGA_G: out std_logic_vector(1 downto 0);
70 VGA_B: out std_logic_vector(1 downto 0);
71 VGA_VS: out std_logic;
72 VGA_HS: out std_logic;
73  
74 -- Bank 1 Pins - Inputs for this Test
75 B: inout std_logic_vector(24 downto 0);
76  
77 -- PS/2 Bidirectional Port (open collector, J31 and J32)
78 PS2_CLK1: inout std_logic;
79 PS2_DATA1: inout std_logic;
80 PS2_CLK2: inout std_logic;
81 PS2_DATA2: inout std_logic;
82  
83 -- Diferencial Signals on 4 pin header (J7)
84 DIF1P: inout std_logic;
85 DIF1N: inout std_logic;
86 DIF2P: inout std_logic;
87 DIF2N: inout std_logic;
88  
89  
90 -- I2C Signals (on connector J30)
91 I2C_SCL: inout std_logic;
92 I2C_SDA: inout std_logic;
93  
94 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
95 SD1AP: inout std_logic;
96 SD1AN: inout std_logic;
97 SD1BP: inout std_logic;
98 SD1BN: inout std_logic;
99 SD2AP: inout std_logic;
100 SD2AN: inout std_logic;
101 SD2BP: inout std_logic;
102 SD2BN: inout std_logic;
103  
104 -- Analog In Out
105 ANA_OUTD: out std_logic;
106 ANA_REFD: out std_logic;
107 ANA_IND: in std_logic;
108  
109 -- SPI Memory Interface
110 SPI_CS_n: inout std_logic;
111 SPI_DO: inout std_logic;
112 SPI_DI: inout std_logic;
113 SPI_CLK: inout std_logic;
114 SPI_WP_n: inout std_logic
115 );
116 end entity AtomicCounter;
117  
118  
119 architecture AtomicCounter_a of AtomicCounter is
120  
3208 kakl 121 function to_bcd ( bin : std_logic_vector(31 downto 0) ) return std_logic_vector is
3201 kakl 122 variable i : integer:=0;
3208 kakl 123 variable mybcd : std_logic_vector(35 downto 0) := (others => '0');
124 variable bint : std_logic_vector(31 downto 0) := bin;
3201 kakl 125 begin
3208 kakl 126 for i in 0 to 31 loop -- repeating 16 times.
127 mybcd(35 downto 1) := mybcd(34 downto 0); --shifting the bits.
128 mybcd(0) := bint(31);
129 bint(31 downto 1) := bint(30 downto 0);
3201 kakl 130 bint(0) :='0';
131  
132  
3208 kakl 133 if(i < 31 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
3201 kakl 134 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
135 end if;
136  
3208 kakl 137 if(i < 31 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
3201 kakl 138 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
139 end if;
140  
3208 kakl 141 if(i < 31 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
3201 kakl 142 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
143 end if;
144  
3208 kakl 145 if(i < 31 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
3201 kakl 146 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
147 end if;
148  
3208 kakl 149 if(i < 31 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
3201 kakl 150 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
151 end if;
152  
3208 kakl 153 if(i < 31 and mybcd(23 downto 20) > "0100") then --add 3 if BCD digit is greater than 4.
154 mybcd(23 downto 20) := std_logic_vector(unsigned(mybcd(23 downto 20)) + 3);
155 end if;
156  
157 if(i < 31 and mybcd(27 downto 24) > "0100") then --add 3 if BCD digit is greater than 4.
158 mybcd(27 downto 24) := std_logic_vector(unsigned(mybcd(27 downto 24)) + 3);
159 end if;
160  
161 if(i < 31 and mybcd(31 downto 28) > "0100") then --add 3 if BCD digit is greater than 4.
162 mybcd(31 downto 28) := std_logic_vector(unsigned(mybcd(31 downto 28)) + 3);
163 end if;
164  
165 if(i < 31 and mybcd(35 downto 32) > "0100") then --add 3 if BCD digit is greater than 4.
166 mybcd(35 downto 32) := std_logic_vector(unsigned(mybcd(35 downto 32)) + 3);
167 end if;
168  
3201 kakl 169 end loop;
170  
171 return mybcd;
172 end to_bcd;
173  
174  
175 -- Counters
176 -- ----------------
177  
3208 kakl 178 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
3201 kakl 179  
180  
181 -- LED Display
182 -- -----------
183  
184 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
185 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
186 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
187 signal Enable: std_logic;
188 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
189 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
190 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
191  
192  
193 signal LO_CLOCK: std_logic; -- Frequency divided by 2
194 signal EXT_CLOCK: std_logic; -- Input Frequency
195  
196 signal Decko: std_logic; -- D flip-flop
197 signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata
198  
199 begin
200  
201 -- Input divider by 2
202 process (EXT_CLOCK)
203 begin
204 if rising_edge(EXT_CLOCK) then
205 LO_CLOCK <= not LO_CLOCK;
206 end if;
207 end process;
208  
209  
210 -- Counter
211 process (LO_CLOCK)
212 begin
213  
214 if rising_edge(LO_CLOCK) then
215  
216 if (State = 3) or (State = 0) then
3208 kakl 217 if DIPSW(7) = '0' then -- Half/Full frequency
3201 kakl 218 Counter <= Counter + 1;
219 else
3208 kakl 220 Counter <= Counter + 2;
3201 kakl 221 end if;
222 end if;
223 if (State = 1) then
3208 kakl 224 Freq(31 downto 0) <= std_logic_vector(Counter);
3201 kakl 225 end if;
226 if (State = 2) then
227 Counter <= (others => '0');
228 end if;
229 end if;
230  
231 end process;
232  
233  
234 -- Sampling 1PPS signal
235 process (LO_CLOCK)
236 begin
237 if rising_edge(LO_CLOCK) then
238 Decko <= B(22);
239 end if;
240 end process;
241  
242 -- Automata for controlling the Counter
243 process (LO_CLOCK)
244 begin
245 if rising_edge(LO_CLOCK) then
246 if (Decko = '1') then
247 if (State < 3) then
248 State <= State + 1;
249 end if;
250 else
251 State <= (others => '0');
252 end if;
253 end if;
254 end process;
255  
256 -- Coding to BCD for LED Display
257  
258 process (Decko)
259 begin
260 if falling_edge(Decko) then
3208 kakl 261 Number(35 downto 0) <= to_bcd(Freq(31 downto 0));
3201 kakl 262 end if;
263 end process;
264  
3208 kakl 265 -- Number(35 downto 0) <= NumberPom(35 downto 0);
3201 kakl 266  
267 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
268 LED(6 downto 4) <= (others => '0');
269 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
270  
271 -- LED Display (multiplexed)
272 -- =========================
273  
274 -- Connect LED Display Output Ports (negative outputs)
275 LD_A_n <= not (Segments(0) and Enable);
276 LD_B_n <= not (Segments(1) and Enable);
277 LD_C_n <= not (Segments(2) and Enable);
278 LD_D_n <= not (Segments(3) and Enable);
279 LD_E_n <= not (Segments(4) and Enable);
280 LD_F_n <= not (Segments(5) and Enable);
281 LD_G_n <= not (Segments(6) and Enable);
282 LD_DP_n <= not (Segments(7) and Enable);
283  
284 LD_0_n <= not Digits(0);
285 LD_1_n <= not Digits(1);
286 LD_2_n <= not Digits(2);
287 LD_3_n <= not Digits(3);
288 LD_4_n <= not Digits(4);
289 LD_5_n <= not Digits(5);
290 LD_6_n <= not Digits(6);
291 LD_7_n <= not Digits(7);
292  
293 -- Time Multiplex
294 process (CLK100MHz)
295 begin
296 if rising_edge(CLK100MHz) then
297 if MuxCounter < MUXCOUNT-1 then
298 MuxCounter <= MuxCounter + 1;
299 else
300 MuxCounter <= (others => '0');
301 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
302 Enable <= '0';
303 end if;
304 if MuxCounter > (MUXCOUNT-4) then
305 Enable <= '1';
306 end if;
307 end if;
308 end process;
309  
310 -- HEX to 7 Segmet Decoder
311 -- -- A
312 -- | | F B
313 -- -- G
314 -- | | E C
315 -- -- D H
316 -- ABCDEFGH
317 Segments <= "11111100" when Code="0000" else -- Digit 0
318 "01100000" when Code="0001" else -- Digit 1
319 "11011010" when Code="0010" else -- Digit 2
320 "11110010" when Code="0011" else -- Digit 3
321 "01100110" when Code="0100" else -- Digit 4
322 "10110110" when Code="0101" else -- Digit 5
323 "10111110" when Code="0110" else -- Digit 6
324 "11100000" when Code="0111" else -- Digit 7
325 "11111110" when Code="1000" else -- Digit 8
326 "11110110" when Code="1001" else -- Digit 9
327 "11101110" when Code="1010" else -- Digit A
328 "00111110" when Code="1011" else -- Digit b
329 "10011100" when Code="1100" else -- Digit C
330 "01111010" when Code="1101" else -- Digit d
331 "10011110" when Code="1110" else -- Digit E
332 "10001110" when Code="1111" else -- Digit F
333 "00000000";
334  
335 Code <= Number( 3 downto 0) when Digits="00000001" else
336 Number( 7 downto 4) when Digits="00000010" else
337 Number(11 downto 8) when Digits="00000100" else
338 Number(15 downto 12) when Digits="00001000" else
339 Number(19 downto 16) when Digits="00010000" else
340 Number(23 downto 20) when Digits="00100000" else
341 Number(27 downto 24) when Digits="01000000" else
342 Number(31 downto 28) when Digits="10000000" else
343 "0000";
344  
345  
346  
347 -- Diferencial In/Outs
348 -- ========================
349 DIFbuffer1 : IBUFGDS
350 generic map (
351 DIFF_TERM => FALSE, -- Differential Termination
352 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
353 -- "0"-"16"
354 IOSTANDARD => "LVPECL_33")
355 port map (
356 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
357 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
358 O => EXT_CLOCK -- Buffer output - Counter INPUT
359 );
360  
361 OBUFDS_inst : OBUFDS
362 generic map (
363 IOSTANDARD => "LVDS_33")
364 port map (
365 O => SD2AP, -- Diff_p output (connect directly to top-level port)
366 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
367 I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS
368 );
369  
370 -- Output Signal on SATA Connector
371 -- SD1AP <= 'Z'; -- Counter INPUT
372 -- SD1AN <= 'Z';
373 SD1BP <= 'Z';
374 SD1BN <= 'Z';
375  
376 -- Input Here via SATA Cable
377 -- SD2AP <= 'Z'; -- Counter OUTPUT
378 -- SD2AN <= 'Z';
379 SD2BP <= 'Z';
380 SD2BN <= 'Z';
381  
382  
383 -- Unused Signals
384 -- ==============
385  
386 -- Differential inputs onn header
387 DIF1N <= 'Z';
388 DIF1P <= 'Z';
389 DIF2N <= 'Z';
390 DIF2P <= 'Z';
391  
392 -- I2C Signals (on connector J30)
393 I2C_SCL <= 'Z';
394 I2C_SDA <= 'Z';
395  
396 -- SPI Memory Interface
397 SPI_CS_n <= 'Z';
398 SPI_DO <= 'Z';
399 SPI_DI <= 'Z';
400 SPI_CLK <= 'Z';
401 SPI_WP_n <= 'Z';
402  
403 -- A/D
404 ANA_OUTD <= 'Z';
405 ANA_REFD <= 'Z';
406  
407 -- VGA
408 VGA_R <= "ZZ";
409 VGA_G <= "ZZ";
410 VGA_B <= "ZZ";
411 VGA_VS <= 'Z';
412 VGA_HS <= 'Z';
413  
414 -- PS2
415 PS2_DATA2 <= 'Z';
416 PS2_CLK2 <='Z';
417  
418 end architecture AtomicCounter_a;