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kakl |
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-- Company: www.mlab.cz |
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-- Based on code written by MIHO. |
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-- |
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-- HW Design Name: S3AN01A |
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-- Project Name: Atomic Counter |
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-- Target Devices: XC3S50AN-4 |
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-- Tool versions: ISE 13.3 |
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kakl |
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-- Description: Counter up to 640 MHz synchonised by GPS. |
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-- Output frequency is displayed on the 7seg. LED display. |
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-- You can choice half or full frequency by DIPSW7. |
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kakl |
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-- |
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-- Dependencies: TTLPECL01A, GPS01A |
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-- |
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-- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $ |
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-- |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.numeric_std.ALL; |
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library UNISIM; |
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use UNISIM.vcomponents.all; |
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entity AtomicCounter is |
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generic ( |
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-- Top Value for 100MHz Clock Counter |
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MAXCOUNT: integer := 10_000; -- Maximum for the first counter |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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); |
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port ( |
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-- Clock on PCB |
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CLK100MHz: in std_logic; |
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-- Mode Signals (usualy not used) |
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M: in std_logic_vector(2 downto 0); |
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VS: in std_logic_vector(2 downto 0); |
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-- Dipswitch Inputs |
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DIPSW: in std_logic_vector(7 downto 0); |
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-- Push Buttons |
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PB: in std_logic_vector(3 downto 0); |
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-- LED Bar Outputs |
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LED: out std_logic_vector(7 downto 0); |
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-- LED Display (8 digit with 7 segments and ddecimal point) |
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LD_A_n: out std_logic; |
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LD_B_n: out std_logic; |
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LD_C_n: out std_logic; |
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LD_D_n: out std_logic; |
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LD_E_n: out std_logic; |
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LD_F_n: out std_logic; |
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LD_G_n: out std_logic; |
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LD_DP_n: out std_logic; |
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LD_0_n: out std_logic; |
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LD_1_n: out std_logic; |
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LD_2_n: out std_logic; |
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LD_3_n: out std_logic; |
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LD_4_n: out std_logic; |
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LD_5_n: out std_logic; |
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LD_6_n: out std_logic; |
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LD_7_n: out std_logic; |
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-- VGA Video Out Port |
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VGA_R: out std_logic_vector(1 downto 0); |
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VGA_G: out std_logic_vector(1 downto 0); |
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VGA_B: out std_logic_vector(1 downto 0); |
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VGA_VS: out std_logic; |
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VGA_HS: out std_logic; |
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-- Bank 1 Pins - Inputs for this Test |
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B: inout std_logic_vector(24 downto 0); |
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-- PS/2 Bidirectional Port (open collector, J31 and J32) |
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PS2_CLK1: inout std_logic; |
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PS2_DATA1: inout std_logic; |
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PS2_CLK2: inout std_logic; |
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PS2_DATA2: inout std_logic; |
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-- Diferencial Signals on 4 pin header (J7) |
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DIF1P: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2N: inout std_logic; |
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-- I2C Signals (on connector J30) |
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I2C_SCL: inout std_logic; |
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I2C_SDA: inout std_logic; |
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-- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29) |
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SD1AP: inout std_logic; |
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SD1AN: inout std_logic; |
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SD1BP: inout std_logic; |
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SD1BN: inout std_logic; |
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SD2AP: inout std_logic; |
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SD2AN: inout std_logic; |
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SD2BP: inout std_logic; |
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SD2BN: inout std_logic; |
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-- Analog In Out |
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ANA_OUTD: out std_logic; |
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ANA_REFD: out std_logic; |
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ANA_IND: in std_logic; |
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-- SPI Memory Interface |
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SPI_CS_n: inout std_logic; |
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SPI_DO: inout std_logic; |
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SPI_DI: inout std_logic; |
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SPI_CLK: inout std_logic; |
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SPI_WP_n: inout std_logic |
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); |
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end entity AtomicCounter; |
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architecture AtomicCounter_a of AtomicCounter is |
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kakl |
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function to_bcd ( bin : std_logic_vector(31 downto 0) ) return std_logic_vector is |
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kakl |
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variable i : integer:=0; |
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kakl |
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variable mybcd : std_logic_vector(35 downto 0) := (others => '0'); |
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variable bint : std_logic_vector(31 downto 0) := bin; |
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kakl |
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begin |
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for i in 0 to 31 loop -- repeating 16 times. |
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mybcd(35 downto 1) := mybcd(34 downto 0); --shifting the bits. |
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mybcd(0) := bint(31); |
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bint(31 downto 1) := bint(30 downto 0); |
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kakl |
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bint(0) :='0'; |
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kakl |
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if(i < 31 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4. |
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kakl |
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mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3); |
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end if; |
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kakl |
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if(i < 31 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4. |
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kakl |
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mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3); |
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end if; |
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if(i < 31 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4. |
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kakl |
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mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3); |
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end if; |
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if(i < 31 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4. |
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kakl |
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mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3); |
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end if; |
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kakl |
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if(i < 31 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4. |
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kakl |
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mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3); |
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end if; |
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if(i < 31 and mybcd(23 downto 20) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(23 downto 20) := std_logic_vector(unsigned(mybcd(23 downto 20)) + 3); |
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end if; |
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if(i < 31 and mybcd(27 downto 24) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(27 downto 24) := std_logic_vector(unsigned(mybcd(27 downto 24)) + 3); |
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end if; |
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if(i < 31 and mybcd(31 downto 28) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(31 downto 28) := std_logic_vector(unsigned(mybcd(31 downto 28)) + 3); |
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end if; |
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if(i < 31 and mybcd(35 downto 32) > "0100") then --add 3 if BCD digit is greater than 4. |
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mybcd(35 downto 32) := std_logic_vector(unsigned(mybcd(35 downto 32)) + 3); |
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end if; |
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kakl |
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end loop; |
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return mybcd; |
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end to_bcd; |
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-- Counters |
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-- ---------------- |
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signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary) |
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-- LED Display |
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-- ----------- |
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signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input |
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signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal Enable: std_logic; |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output |
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signal LO_CLOCK: std_logic; -- Frequency divided by 2 |
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signal EXT_CLOCK: std_logic; -- Input Frequency |
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signal Decko: std_logic; -- D flip-flop |
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signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata |
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begin |
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-- Input divider by 2 |
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process (EXT_CLOCK) |
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begin |
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if rising_edge(EXT_CLOCK) then |
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LO_CLOCK <= not LO_CLOCK; |
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end if; |
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end process; |
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-- Counter |
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process (LO_CLOCK) |
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begin |
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if rising_edge(LO_CLOCK) then |
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if (State = 3) or (State = 0) then |
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if DIPSW(7) = '0' then -- Half/Full frequency |
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Counter <= Counter + 1; |
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else |
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Counter <= Counter + 2; |
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kakl |
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end if; |
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end if; |
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if (State = 1) then |
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kakl |
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Freq(31 downto 0) <= std_logic_vector(Counter); |
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end if; |
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if (State = 2) then |
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Counter <= (others => '0'); |
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end if; |
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end if; |
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end process; |
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-- Sampling 1PPS signal |
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process (LO_CLOCK) |
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begin |
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if rising_edge(LO_CLOCK) then |
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Decko <= B(22); |
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end if; |
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end process; |
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-- Automata for controlling the Counter |
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process (LO_CLOCK) |
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begin |
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if rising_edge(LO_CLOCK) then |
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if (Decko = '1') then |
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if (State < 3) then |
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State <= State + 1; |
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end if; |
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else |
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State <= (others => '0'); |
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end if; |
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end if; |
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end process; |
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-- Coding to BCD for LED Display |
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process (Decko) |
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begin |
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if falling_edge(Decko) then |
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Number(35 downto 0) <= to_bcd(Freq(31 downto 0)); |
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end if; |
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end process; |
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kakl |
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-- Number(35 downto 0) <= NumberPom(35 downto 0); |
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kakl |
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LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar |
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LED(6 downto 4) <= (others => '0'); |
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LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar |
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-- LED Display (multiplexed) |
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-- ========================= |
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-- Connect LED Display Output Ports (negative outputs) |
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LD_A_n <= not (Segments(0) and Enable); |
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LD_B_n <= not (Segments(1) and Enable); |
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LD_C_n <= not (Segments(2) and Enable); |
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LD_D_n <= not (Segments(3) and Enable); |
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LD_E_n <= not (Segments(4) and Enable); |
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LD_F_n <= not (Segments(5) and Enable); |
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LD_G_n <= not (Segments(6) and Enable); |
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LD_DP_n <= not (Segments(7) and Enable); |
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LD_0_n <= not Digits(0); |
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LD_1_n <= not Digits(1); |
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LD_2_n <= not Digits(2); |
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LD_3_n <= not Digits(3); |
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LD_4_n <= not Digits(4); |
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LD_5_n <= not Digits(5); |
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LD_6_n <= not Digits(6); |
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LD_7_n <= not Digits(7); |
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-- Time Multiplex |
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process (CLK100MHz) |
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begin |
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if rising_edge(CLK100MHz) then |
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if MuxCounter < MUXCOUNT-1 then |
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MuxCounter <= MuxCounter + 1; |
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else |
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MuxCounter <= (others => '0'); |
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Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left |
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Enable <= '0'; |
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end if; |
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if MuxCounter > (MUXCOUNT-4) then |
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Enable <= '1'; |
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end if; |
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end if; |
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end process; |
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-- HEX to 7 Segmet Decoder |
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-- -- A |
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-- | | F B |
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-- -- G |
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-- | | E C |
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-- -- D H |
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-- ABCDEFGH |
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Segments <= "11111100" when Code="0000" else -- Digit 0 |
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"01100000" when Code="0001" else -- Digit 1 |
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"11011010" when Code="0010" else -- Digit 2 |
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"11110010" when Code="0011" else -- Digit 3 |
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"01100110" when Code="0100" else -- Digit 4 |
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"10110110" when Code="0101" else -- Digit 5 |
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"10111110" when Code="0110" else -- Digit 6 |
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"11100000" when Code="0111" else -- Digit 7 |
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"11111110" when Code="1000" else -- Digit 8 |
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"11110110" when Code="1001" else -- Digit 9 |
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"11101110" when Code="1010" else -- Digit A |
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"00111110" when Code="1011" else -- Digit b |
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"10011100" when Code="1100" else -- Digit C |
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"01111010" when Code="1101" else -- Digit d |
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"10011110" when Code="1110" else -- Digit E |
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"10001110" when Code="1111" else -- Digit F |
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"00000000"; |
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Code <= Number( 3 downto 0) when Digits="00000001" else |
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Number( 7 downto 4) when Digits="00000010" else |
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Number(11 downto 8) when Digits="00000100" else |
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Number(15 downto 12) when Digits="00001000" else |
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Number(19 downto 16) when Digits="00010000" else |
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Number(23 downto 20) when Digits="00100000" else |
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Number(27 downto 24) when Digits="01000000" else |
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Number(31 downto 28) when Digits="10000000" else |
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"0000"; |
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-- Diferencial In/Outs |
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-- ======================== |
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DIFbuffer1 : IBUFGDS |
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generic map ( |
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DIFF_TERM => FALSE, -- Differential Termination |
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IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, |
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-- "0"-"16" |
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IOSTANDARD => "LVPECL_33") |
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port map ( |
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I => SD1AP, -- Diff_p buffer input (connect directly to top-level port) |
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IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port) |
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O => EXT_CLOCK -- Buffer output - Counter INPUT |
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); |
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OBUFDS_inst : OBUFDS |
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|
362 |
generic map ( |
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|
363 |
IOSTANDARD => "LVDS_33") |
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|
364 |
port map ( |
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|
365 |
O => SD2AP, -- Diff_p output (connect directly to top-level port) |
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366 |
OB => SD2AN, -- Diff_n output (connect directly to top-level port) |
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|
367 |
I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS |
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|
368 |
); |
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|
369 |
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370 |
-- Output Signal on SATA Connector |
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371 |
-- SD1AP <= 'Z'; -- Counter INPUT |
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|
372 |
-- SD1AN <= 'Z'; |
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373 |
SD1BP <= 'Z'; |
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374 |
SD1BN <= 'Z'; |
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|
375 |
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376 |
-- Input Here via SATA Cable |
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|
377 |
-- SD2AP <= 'Z'; -- Counter OUTPUT |
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|
378 |
-- SD2AN <= 'Z'; |
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|
379 |
SD2BP <= 'Z'; |
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|
380 |
SD2BN <= 'Z'; |
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|
381 |
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|
382 |
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|
|
383 |
-- Unused Signals |
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|
384 |
-- ============== |
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|
385 |
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|
386 |
-- Differential inputs onn header |
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|
387 |
DIF1N <= 'Z'; |
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|
388 |
DIF1P <= 'Z'; |
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|
389 |
DIF2N <= 'Z'; |
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|
390 |
DIF2P <= 'Z'; |
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|
391 |
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|
392 |
-- I2C Signals (on connector J30) |
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|
393 |
I2C_SCL <= 'Z'; |
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|
394 |
I2C_SDA <= 'Z'; |
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|
395 |
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|
396 |
-- SPI Memory Interface |
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|
397 |
SPI_CS_n <= 'Z'; |
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|
398 |
SPI_DO <= 'Z'; |
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|
399 |
SPI_DI <= 'Z'; |
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|
400 |
SPI_CLK <= 'Z'; |
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|
401 |
SPI_WP_n <= 'Z'; |
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|
402 |
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|
403 |
-- A/D |
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|
404 |
ANA_OUTD <= 'Z'; |
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|
405 |
ANA_REFD <= 'Z'; |
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|
406 |
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|
407 |
-- VGA |
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|
408 |
VGA_R <= "ZZ"; |
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|
409 |
VGA_G <= "ZZ"; |
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|
410 |
VGA_B <= "ZZ"; |
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|
411 |
VGA_VS <= 'Z'; |
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|
412 |
VGA_HS <= 'Z'; |
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|
413 |
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|
|
414 |
-- PS2 |
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|
415 |
PS2_DATA2 <= 'Z'; |
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|
416 |
PS2_CLK2 <='Z'; |
|
|
417 |
|
|
|
418 |
end architecture AtomicCounter_a; |