Rev Author Line No. Line
3201 kakl 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO.
4 --
5 -- HW Design Name: S3AN01A
6 -- Project Name: Atomic Counter
7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3
9 -- Description: Counter synchonised by GPS.
10 --
11 -- Dependencies: TTLPECL01A, GPS01A
12 --
13 -- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $
14 --
15 ----------------------------------------------------------------------------------
16  
17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL;
19 use IEEE.numeric_std.ALL;
20  
21 library UNISIM;
22 use UNISIM.vcomponents.all;
23  
24 entity AtomicCounter is
25 generic (
26 -- Top Value for 100MHz Clock Counter
27 MAXCOUNT: integer := 10_000; -- Maximum for the first counter
28 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
29 );
30 port (
31 -- Clock on PCB
32 CLK100MHz: in std_logic;
33  
34 -- Mode Signals (usualy not used)
35 M: in std_logic_vector(2 downto 0);
36 VS: in std_logic_vector(2 downto 0);
37  
38 -- Dipswitch Inputs
39 DIPSW: in std_logic_vector(7 downto 0);
40  
41 -- Push Buttons
42 PB: in std_logic_vector(3 downto 0);
43  
44 -- LED Bar Outputs
45 LED: out std_logic_vector(7 downto 0);
46  
47 -- LED Display (8 digit with 7 segments and ddecimal point)
48 LD_A_n: out std_logic;
49 LD_B_n: out std_logic;
50 LD_C_n: out std_logic;
51 LD_D_n: out std_logic;
52 LD_E_n: out std_logic;
53 LD_F_n: out std_logic;
54 LD_G_n: out std_logic;
55 LD_DP_n: out std_logic;
56 LD_0_n: out std_logic;
57 LD_1_n: out std_logic;
58 LD_2_n: out std_logic;
59 LD_3_n: out std_logic;
60 LD_4_n: out std_logic;
61 LD_5_n: out std_logic;
62 LD_6_n: out std_logic;
63 LD_7_n: out std_logic;
64  
65 -- VGA Video Out Port
66 VGA_R: out std_logic_vector(1 downto 0);
67 VGA_G: out std_logic_vector(1 downto 0);
68 VGA_B: out std_logic_vector(1 downto 0);
69 VGA_VS: out std_logic;
70 VGA_HS: out std_logic;
71  
72 -- Bank 1 Pins - Inputs for this Test
73 B: inout std_logic_vector(24 downto 0);
74  
75 -- PS/2 Bidirectional Port (open collector, J31 and J32)
76 PS2_CLK1: inout std_logic;
77 PS2_DATA1: inout std_logic;
78 PS2_CLK2: inout std_logic;
79 PS2_DATA2: inout std_logic;
80  
81 -- Diferencial Signals on 4 pin header (J7)
82 DIF1P: inout std_logic;
83 DIF1N: inout std_logic;
84 DIF2P: inout std_logic;
85 DIF2N: inout std_logic;
86  
87  
88 -- I2C Signals (on connector J30)
89 I2C_SCL: inout std_logic;
90 I2C_SDA: inout std_logic;
91  
92 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
93 SD1AP: inout std_logic;
94 SD1AN: inout std_logic;
95 SD1BP: inout std_logic;
96 SD1BN: inout std_logic;
97 SD2AP: inout std_logic;
98 SD2AN: inout std_logic;
99 SD2BP: inout std_logic;
100 SD2BN: inout std_logic;
101  
102 -- Analog In Out
103 ANA_OUTD: out std_logic;
104 ANA_REFD: out std_logic;
105 ANA_IND: in std_logic;
106  
107 -- SPI Memory Interface
108 SPI_CS_n: inout std_logic;
109 SPI_DO: inout std_logic;
110 SPI_DI: inout std_logic;
111 SPI_CLK: inout std_logic;
112 SPI_WP_n: inout std_logic
113 );
114 end entity AtomicCounter;
115  
116  
117 architecture AtomicCounter_a of AtomicCounter is
118  
119 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
120 variable i : integer:=0;
121 variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
122 variable bint : std_logic_vector(15 downto 0) := bin;
123 begin
124 for i in 0 to 15 loop -- repeating 16 times.
125 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits.
126 mybcd(0) := bint(15);
127 bint(15 downto 1) := bint(14 downto 0);
128 bint(0) :='0';
129  
130  
131 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
132 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
133 end if;
134  
135 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
136 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
137 end if;
138  
139 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
140 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
141 end if;
142  
143 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
144 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
145 end if;
146  
147 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
148 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
149 end if;
150  
151 end loop;
152  
153 return mybcd;
154 end to_bcd;
155  
156  
157 -- Counters
158 -- ----------------
159  
160 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
161 signal CounterMaxcount: unsigned(15 downto 0) := "0000000000000000"; -- Main Counter 10 kHz, max. 655.35 MHz (binary)
162  
163  
164 -- LED Display
165 -- -----------
166  
167 signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- Variable for bin/BCD conversion
168 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
169 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
170 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
171 signal Enable: std_logic;
172 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
173 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
174 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
175  
176  
177 signal LO_CLOCK: std_logic; -- Frequency divided by 2
178 signal EXT_CLOCK: std_logic; -- Input Frequency
179  
180 signal Decko: std_logic; -- D flip-flop
181 signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata
182  
183 begin
184  
185 -- Input divider by 2
186 process (EXT_CLOCK)
187 begin
188 if rising_edge(EXT_CLOCK) then
189 LO_CLOCK <= not LO_CLOCK;
190 end if;
191 end process;
192  
193  
194 -- Counter
195 process (LO_CLOCK)
196 begin
197  
198 if rising_edge(LO_CLOCK) then
199  
200 if (State = 3) or (State = 0) then
201 if Counter < MAXCOUNT-1 then
202 Counter <= Counter + 1;
203 else
204 Counter <= (others => '0');
205 CounterMaxcount <= CounterMaxcount + 1;
206 end if;
207 end if;
208 if (State = 1) then
209 Freq(15 downto 0) <= std_logic_vector("00"&Counter);
210 Freq(31 downto 16) <= std_logic_vector(CounterMaxcount);
211 end if;
212 if (State = 2) then
213 CounterMaxcount <= (others => '0');
214 Counter <= (others => '0');
215 end if;
216 end if;
217  
218 end process;
219  
220  
221 -- Sampling 1PPS signal
222 process (LO_CLOCK)
223 begin
224 if rising_edge(LO_CLOCK) then
225 Decko <= B(22);
226 end if;
227 end process;
228  
229 -- Automata for controlling the Counter
230 process (LO_CLOCK)
231 begin
232 if rising_edge(LO_CLOCK) then
233 if (Decko = '1') then
234 if (State < 3) then
235 State <= State + 1;
236 end if;
237 else
238 State <= (others => '0');
239 end if;
240 end if;
241 end process;
242  
243 -- Coding to BCD for LED Display
244  
245 process (Decko)
246 begin
247 if falling_edge(Decko) then
248 if DIPSW(7) = '0' then
249 NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0); -- Half frequency
250 NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0);
251 else
252 NumberPom(15 downto 0) <= to_bcd(Freq(14 downto 1)&"0")(15 downto 0); -- Full frequency
253 NumberPom(35 downto 16) <= to_bcd(Freq(30 downto 15))(19 downto 0);
254 end if;
255 end if;
256 end process;
257  
258 Number(35 downto 0) <= NumberPom(35 downto 0);
259  
260 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
261 LED(6 downto 4) <= (others => '0');
262 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
263  
264 -- LED Display (multiplexed)
265 -- =========================
266  
267 -- Connect LED Display Output Ports (negative outputs)
268 LD_A_n <= not (Segments(0) and Enable);
269 LD_B_n <= not (Segments(1) and Enable);
270 LD_C_n <= not (Segments(2) and Enable);
271 LD_D_n <= not (Segments(3) and Enable);
272 LD_E_n <= not (Segments(4) and Enable);
273 LD_F_n <= not (Segments(5) and Enable);
274 LD_G_n <= not (Segments(6) and Enable);
275 LD_DP_n <= not (Segments(7) and Enable);
276  
277 LD_0_n <= not Digits(0);
278 LD_1_n <= not Digits(1);
279 LD_2_n <= not Digits(2);
280 LD_3_n <= not Digits(3);
281 LD_4_n <= not Digits(4);
282 LD_5_n <= not Digits(5);
283 LD_6_n <= not Digits(6);
284 LD_7_n <= not Digits(7);
285  
286 -- Time Multiplex
287 process (CLK100MHz)
288 begin
289 if rising_edge(CLK100MHz) then
290 if MuxCounter < MUXCOUNT-1 then
291 MuxCounter <= MuxCounter + 1;
292 else
293 MuxCounter <= (others => '0');
294 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
295 Enable <= '0';
296 end if;
297 if MuxCounter > (MUXCOUNT-4) then
298 Enable <= '1';
299 end if;
300 end if;
301 end process;
302  
303 -- HEX to 7 Segmet Decoder
304 -- -- A
305 -- | | F B
306 -- -- G
307 -- | | E C
308 -- -- D H
309 -- ABCDEFGH
310 Segments <= "11111100" when Code="0000" else -- Digit 0
311 "01100000" when Code="0001" else -- Digit 1
312 "11011010" when Code="0010" else -- Digit 2
313 "11110010" when Code="0011" else -- Digit 3
314 "01100110" when Code="0100" else -- Digit 4
315 "10110110" when Code="0101" else -- Digit 5
316 "10111110" when Code="0110" else -- Digit 6
317 "11100000" when Code="0111" else -- Digit 7
318 "11111110" when Code="1000" else -- Digit 8
319 "11110110" when Code="1001" else -- Digit 9
320 "11101110" when Code="1010" else -- Digit A
321 "00111110" when Code="1011" else -- Digit b
322 "10011100" when Code="1100" else -- Digit C
323 "01111010" when Code="1101" else -- Digit d
324 "10011110" when Code="1110" else -- Digit E
325 "10001110" when Code="1111" else -- Digit F
326 "00000000";
327  
328 Code <= Number( 3 downto 0) when Digits="00000001" else
329 Number( 7 downto 4) when Digits="00000010" else
330 Number(11 downto 8) when Digits="00000100" else
331 Number(15 downto 12) when Digits="00001000" else
332 Number(19 downto 16) when Digits="00010000" else
333 Number(23 downto 20) when Digits="00100000" else
334 Number(27 downto 24) when Digits="01000000" else
335 Number(31 downto 28) when Digits="10000000" else
336 "0000";
337  
338  
339  
340 -- Diferencial In/Outs
341 -- ========================
342 DIFbuffer1 : IBUFGDS
343 generic map (
344 DIFF_TERM => FALSE, -- Differential Termination
345 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
346 -- "0"-"16"
347 IOSTANDARD => "LVPECL_33")
348 port map (
349 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
350 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
351 O => EXT_CLOCK -- Buffer output - Counter INPUT
352 );
353  
354 OBUFDS_inst : OBUFDS
355 generic map (
356 IOSTANDARD => "LVDS_33")
357 port map (
358 O => SD2AP, -- Diff_p output (connect directly to top-level port)
359 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
360 I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS
361 );
362  
363 -- Output Signal on SATA Connector
364 -- SD1AP <= 'Z'; -- Counter INPUT
365 -- SD1AN <= 'Z';
366 SD1BP <= 'Z';
367 SD1BN <= 'Z';
368  
369 -- Input Here via SATA Cable
370 -- SD2AP <= 'Z'; -- Counter OUTPUT
371 -- SD2AN <= 'Z';
372 SD2BP <= 'Z';
373 SD2BN <= 'Z';
374  
375  
376 -- Unused Signals
377 -- ==============
378  
379 -- Differential inputs onn header
380 DIF1N <= 'Z';
381 DIF1P <= 'Z';
382 DIF2N <= 'Z';
383 DIF2P <= 'Z';
384  
385 -- I2C Signals (on connector J30)
386 I2C_SCL <= 'Z';
387 I2C_SDA <= 'Z';
388  
389 -- SPI Memory Interface
390 SPI_CS_n <= 'Z';
391 SPI_DO <= 'Z';
392 SPI_DI <= 'Z';
393 SPI_CLK <= 'Z';
394 SPI_WP_n <= 'Z';
395  
396 -- A/D
397 ANA_OUTD <= 'Z';
398 ANA_REFD <= 'Z';
399  
400 -- VGA
401 VGA_R <= "ZZ";
402 VGA_G <= "ZZ";
403 VGA_B <= "ZZ";
404 VGA_VS <= 'Z';
405 VGA_HS <= 'Z';
406  
407 -- PS2
408 PS2_DATA2 <= 'Z';
409 PS2_CLK2 <='Z';
410  
411 end architecture AtomicCounter_a;