Rev Author Line No. Line
3165 kakl 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO.
4 --
5 -- HW Design Name: S3AN01A
6 -- Project Name: gtime
7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A.
10 --
11 -- Dependencies: CLKGEN01B, GPS01A
12 --
13 -- Version: $Id: PulseGen.vhd 2534 2012-09-02 13:40:37Z kakl $
14 --
15 ----------------------------------------------------------------------------------
16  
17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL;
19 use IEEE.numeric_std.ALL;
20 use WORK.PS2_pkg.ALL;
21  
22 library UNISIM;
23 use UNISIM.vcomponents.all;
24  
25 entity gtime is
26 generic (
27 -- Top Value for 100MHz Clock Counter
28 --!!!KAKL MAXCOUNT: integer := 30_000_000;
29 MAXCOUNT: integer := 3_000_000;
30 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
31 );
32 port (
33 -- Main Clock
34 CLK100MHz: in std_logic;
35  
36 -- Mode Signals (usualy not used)
37 M: in std_logic_vector(2 downto 0);
38 VS: in std_logic_vector(2 downto 0);
39  
40 -- Dipswitch Inputs
41 DIPSW: in std_logic_vector(7 downto 0);
42  
43 -- Push Buttons
44 PB: in std_logic_vector(3 downto 0);
45  
46 -- LED Bar Outputs
47 LED: out std_logic_vector(7 downto 0);
48  
49 -- LED Display (8 digit with 7 segments and ddecimal point)
50 LD_A_n: out std_logic;
51 LD_B_n: out std_logic;
52 LD_C_n: out std_logic;
53 LD_D_n: out std_logic;
54 LD_E_n: out std_logic;
55 LD_F_n: out std_logic;
56 LD_G_n: out std_logic;
57 LD_DP_n: out std_logic;
58 LD_0_n: out std_logic;
59 LD_1_n: out std_logic;
60 LD_2_n: out std_logic;
61 LD_3_n: out std_logic;
62 LD_4_n: out std_logic;
63 LD_5_n: out std_logic;
64 LD_6_n: out std_logic;
65 LD_7_n: out std_logic;
66  
67 -- VGA Video Out Port
68 VGA_R: out std_logic_vector(1 downto 0);
69 VGA_G: out std_logic_vector(1 downto 0);
70 VGA_B: out std_logic_vector(1 downto 0);
71 VGA_VS: out std_logic;
72 VGA_HS: out std_logic;
73  
74 -- Bank 1 Pins - Inputs for this Test
75 B: inout std_logic_vector(24 downto 0);
76  
77 -- PS/2 Bidirectional Port (open collector, J31 and J32)
78 -- PS2_CLK1: inout std_logic;
79 -- PS2_DATA1: inout std_logic;
80 PS2_CLK2: inout std_logic;
81 PS2_DATA2: inout std_logic;
82  
83 -- Diferencial Signals on 4 pin header (J7)
84 DIF1P: inout std_logic;
85 DIF1N: inout std_logic;
86 DIF2P: inout std_logic;
87 DIF2N: inout std_logic;
88  
89  
90 -- I2C Signals (on connector J30)
91 I2C_SCL: inout std_logic;
92 I2C_SDA: inout std_logic;
93  
94 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
95 SD1AP: inout std_logic;
96 SD1AN: inout std_logic;
97 SD1BP: inout std_logic;
98 SD1BN: inout std_logic;
99 SD2AP: inout std_logic;
100 SD2AN: inout std_logic;
101 SD2BP: inout std_logic;
102 SD2BN: inout std_logic;
103  
104 -- Analog In Out
105 ANA_OUTD: out std_logic;
106 ANA_REFD: out std_logic;
107 ANA_IND: in std_logic;
108  
109 -- SPI Memory Interface
110 SPI_CS_n: inout std_logic;
111 SPI_DO: inout std_logic;
112 SPI_DI: inout std_logic;
113 SPI_CLK: inout std_logic;
114 SPI_WP_n: inout std_logic
115 );
116 end entity gtime;
117  
118  
119 architecture gtime_a of gtime is
120  
121 function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
122 variable i : integer:=0;
123 variable mybcd : std_logic_vector(11 downto 0) := (others => '0');
124 variable bint : std_logic_vector(7 downto 0) := bin;
125 begin
126 for i in 0 to 7 loop -- repeating 8 times.
127 mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits.
128 mybcd(0) := bint(7);
129 bint(7 downto 1) := bint(6 downto 0);
130 bint(0) :='0';
131  
132  
133 if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
134 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
135 end if;
136  
137 if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
138 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
139 end if;
140  
141 if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
142 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
143 end if;
144 end loop;
145  
146 return mybcd;
147 end to_bcd;
148  
149  
150 -- O1: ____|^^^^^^^|______
151 -- O2: _________|^^|______
152 -- t1 t2
153 -- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz
154  
155 signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2
156 signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2
157 signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer
158 signal O1: std_logic := '0'; -- Output 1
159 signal O2: std_logic := '0'; -- Output 2
160 signal CTburst: unsigned(15 downto 0) := X"0000"; -- Pulse counter
161  
162 -- LED Demo Signals
163 -- ----------------
164  
165 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary)
166 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
167  
168 signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz)
169  
170 -- LED Display
171 -- -----------
172  
173 signal Number: std_logic_vector(32 downto 0); -- LED Display Input
174 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
175 signal Enable: std_logic;
176 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
177 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
178 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
179  
180 -- PS/2 Port
181 -- ---------
182  
183 -- Interface Signals
184 signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code
185 signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
186 signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock)
187 signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code
188  
189 -- Result
190 signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory)
191  
192 -- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese
193  
194 -- VGA Demo Signals
195 -- ----------------
196  
197 signal CLK: std_logic; -- Main Clock - global distribution network
198 signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG
199 signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network
200 signal VGA_Blank: boolean; -- Blank
201 signal VGA_Hsync: boolean; -- Horisontal Synchronisation
202 signal VGA_Vsync: boolean; -- Vertical Synchronisation
203  
204 signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter
205 signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter
206  
207 signal PinState: std_logic; -- For IB1 Port Test
208 signal Red: std_logic_vector(1 downto 0);
209 signal Green: std_logic_vector(1 downto 0);
210 signal Blue: std_logic_vector(1 downto 0);
211  
212 -- ADDA
213 signal ADDA_DataIn: std_logic_vector(7 downto 0);
214  
215  
216 signal LO_CLOCK: std_logic;
217  
218 begin
219  
220 -- Basic LED Blinking Test
221 -- =======================
222  
223 -- LED Bar Counter
224 --!!!KAKL process (CLK100MHz)
225 process (LO_CLOCK)
226 begin
227 -- if rising_edge(CLK100MHz) then
228 if DIPSW(0)='1' then
229 if rising_edge(LO_CLOCK) then
230 if Counter < MAXCOUNT-1 then
231 Counter <= Counter + 1;
232 else
233 Counter <= (others => '0');
234 Bar <= Bar + 1;
235 end if;
236 end if;
237 end if;
238 end process;
239  
240 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
241  
242 FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
243  
244 -- LED Display (multiplexed)
245 -- =========================
246  
247 -- Connect LED Display Output Ports (negative outputs)
248 LD_A_n <= not (Segments(0) and Enable);
249 LD_B_n <= not (Segments(1) and Enable);
250 LD_C_n <= not (Segments(2) and Enable);
251 LD_D_n <= not (Segments(3) and Enable);
252 LD_E_n <= not (Segments(4) and Enable);
253 LD_F_n <= not (Segments(5) and Enable);
254 LD_G_n <= not (Segments(6) and Enable);
255 LD_DP_n <= not (Segments(7) and Enable);
256  
257 LD_0_n <= not Digits(0);
258 LD_1_n <= not Digits(1);
259 LD_2_n <= not Digits(2);
260 LD_3_n <= not Digits(3);
261 LD_4_n <= not Digits(4);
262 LD_5_n <= not Digits(5);
263 LD_6_n <= not Digits(6);
264 LD_7_n <= not Digits(7);
265  
266 -- Time Multiplex
267 process (CLK100MHz)
268 begin
269 if rising_edge(CLK100MHz) then
270 if MuxCounter < MUXCOUNT-1 then
271 MuxCounter <= MuxCounter + 1;
272 else
273 MuxCounter <= (others => '0');
274 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
275 Enable <= '0';
276 end if;
277 if MuxCounter > (MUXCOUNT-4) then
278 Enable <= '1';
279 end if;
280 end if;
281 end process;
282  
283 -- BCD to 7 Segmet Decoder
284 -- -- A
285 -- | | F B
286 -- -- G
287 -- | | E C
288 -- -- D H
289 -- ABCDEFGH
290 Segments <= "11111100" when Code="0000" else -- Digit 0
291 "01100000" when Code="0001" else -- Digit 1
292 "11011010" when Code="0010" else -- Digit 2
293 "11110010" when Code="0011" else -- Digit 3
294 "01100110" when Code="0100" else -- Digit 4
295 "10110110" when Code="0101" else -- Digit 5
296 "10111110" when Code="0110" else -- Digit 6
297 "11100000" when Code="0111" else -- Digit 7
298 "11111110" when Code="1000" else -- Digit 8
299 "11110110" when Code="1001" else -- Digit 9
300 "11101110" when Code="1010" else -- Digit A
301 "00111110" when Code="1011" else -- Digit b
302 "10011100" when Code="1100" else -- Digit C
303 "01111010" when Code="1101" else -- Digit d
304 "10011110" when Code="1110" else -- Digit E
305 "10001110" when Code="1111" else -- Digit F
306 "00000000";
307  
308 Code <= Number( 3 downto 0) when Digits="00000001" else
309 Number( 7 downto 4) when Digits="00000010" else
310 Number(11 downto 8) when Digits="00000100" else
311 Number(15 downto 12) when Digits="00001000" else
312 Number(19 downto 16) when Digits="00010000" else
313 Number(23 downto 20) when Digits="00100000" else
314 Number(27 downto 24) when Digits="01000000" else
315 Number(31 downto 28) when Digits="10000000" else
316 "0000";
317  
318 -- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0
319 -- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1
320 -- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2
321 -- "11111111";
322  
323 -- Number(31 downto 28) <= Key(3 downto 0);
324  
325 -- Number( 7 downto 0) <= std_logic_vector(BAR);
326 -- Number(31 downto 24) <= DIPSW;
327  
328 -- PS/2 Port
329 -- =========
330  
331 -- Instantiate PS/2 Keyboard Interface Handler
332 PS2_Keyboard: PS2 generic map(
333 CLKFREQ => 100_000_000
334 )
335 port map(
336 -- Main Clock
337 Clk => CLK100MHz,
338  
339 -- PS/2 Port
340 PS2_Clk => PS2_CLK2,
341 PS2_Data => PS2_DATA2,
342  
343 -- Result - valid when PS2_Valid
344 PS2_Code => PS2_Code,
345 PS2_Attribs => PS2_Attribs,
346 PS2_Valid => PS2_Valid,
347  
348 -- Immediate State of Shifts
349 PS2_Shifts => PS2_Shifts
350 ); -- PS2
351  
352 process (CLK100MHz)
353 begin
354 if rising_edge(CLK100MHz) then
355 if PS2_Valid and PS2_Attribs(7)='0' then
356 -- Valid Scan Code with no Break Attribute
357 PS2_Result( 7 downto 0) <= PS2_Code;
358 PS2_Result(15 downto 8) <= PS2_Attribs;
359 end if;
360  
361 if PS2_Valid and PS2_Attribs(7)='0' then
362 if PS2_Code = X"74" and T1<2000 then T1<=T1+1; end if;
363 if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if;
364 if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if;
365 if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if;
366 CT0<=X"0000";
367 O1<='0';
368 O2<='0';
369 CTburst<=X"0000";
370 end if;
371  
372 if PB(0)='1' then
373 T1<=X"0000";
374 T2<=X"0000";
375 end if;
376  
377 if DIPSW(0)='1' then
378 if CT0>X"F000" then
379 CT0<=X"0000";
380 else
381 CT0<=CT0+1;
382 end if;
383 else
384 if CT0>X"0200" then
385 CT0<=X"0000";
386 else
387 CT0<=CT0+1;
388 end if;
389 end if;
390  
391 if CTburst>2000 then
392 CTburst<=X"0000";
393 end if;
394  
395 if (CTburst<1000) or (DIPSW(1)='0') then
396 if CT0=X"0000" then
397 O1<='1';
398 end if;
399  
400 if CT0=T1+X"0000" then
401 O2<='1';
402 end if;
403 end if;
404  
405 if CT0=T2+T1+X"0000" then
406 O1<='0';
407 O2<='0';
408 CTburst<=CTburst+1;
409 end if;
410  
411 end if;
412  
413 end process;
414  
415 -- Display Result on LED
416 Number(3 downto 0) <= (others=>'0');
417 Number(15 downto 4) <= to_bcd(std_logic_vector(T2));
418 Number(19 downto 16) <= (others=>'0');
419 Number(31 downto 20) <= to_bcd(std_logic_vector(T1));
420  
421  
422 -- Test Diferencial In/Outs
423 -- ========================
424 DIFbuffer1 : IBUFGDS
425 generic map (
426 DIFF_TERM => TRUE, -- Differential Termination
427 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
428 -- "0"-"16"
429 IOSTANDARD => "DEFAULT")
430 port map (
431 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
432 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
433 O => LO_CLOCK -- Buffer output
434 );
435  
436  
437 -- Output Signal on SATA Connector
438 -- SD1AP <= Bar(0);
439 -- SD1AN <= Bar(1);
440 SD1BP <= 'Z';
441 SD1BN <= 'Z';
442  
443 -- Input Here via SATA Cable
444 SD2AP <= 'Z';
445 SD2AN <= 'Z';
446 SD2BP <= 'Z';
447 SD2BN <= 'Z';
448  
449 -- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them
450 -- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!!
451 DIF1P <= O1;
452 B(0) <= O1;
453 DIF1N <= not O1;
454 B(1) <= not O1;
455 DIF2P <= O2;
456 B(2) <= O2;
457 DIF2N <= not O2;
458 B(3) <= not O2;
459  
460 VGA_R(0) <= O1;
461 VGA_R(1) <= O2;
462  
463 -- Unused Signals
464 -- ==============
465  
466 -- I2C Signals (on connector J30)
467 I2C_SCL <= 'Z';
468 I2C_SDA <= 'Z';
469  
470 -- SPI Memory Interface
471 SPI_CS_n <= 'Z';
472 SPI_DO <= 'Z';
473 SPI_DI <= 'Z';
474 SPI_CLK <= 'Z';
475 SPI_WP_n <= 'Z';
476  
477 ANA_OUTD <= 'Z';
478 ANA_REFD <= 'Z';
479  
480 VGA_R <= "ZZ";
481 VGA_G <= "ZZ";
482 VGA_B <= "ZZ";
483 VGA_VS <= 'Z';
484 VGA_HS <= 'Z';
485  
486 end architecture gtime_a;