Rev Author Line No. Line
3165 kakl 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO.
4 --
5 -- HW Design Name: S3AN01A
6 -- Project Name: gtime
7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A.
10 --
11 -- Dependencies: CLKGEN01B, GPS01A
12 --
3172 kakl 13 -- Version: $Id: gtime.vhd 3177 2013-07-17 23:48:47Z kakl $
3165 kakl 14 --
15 ----------------------------------------------------------------------------------
16  
17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL;
19 use IEEE.numeric_std.ALL;
20  
21 library UNISIM;
22 use UNISIM.vcomponents.all;
23  
24 entity gtime is
25 generic (
26 -- Top Value for 100MHz Clock Counter
27 --!!!KAKL MAXCOUNT: integer := 30_000_000;
3173 kakl 28 MAXCOUNT: integer := 10_000;
3165 kakl 29 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
30 );
31 port (
32 -- Main Clock
33 CLK100MHz: in std_logic;
34  
35 -- Mode Signals (usualy not used)
36 M: in std_logic_vector(2 downto 0);
37 VS: in std_logic_vector(2 downto 0);
38  
39 -- Dipswitch Inputs
40 DIPSW: in std_logic_vector(7 downto 0);
41  
42 -- Push Buttons
43 PB: in std_logic_vector(3 downto 0);
44  
45 -- LED Bar Outputs
46 LED: out std_logic_vector(7 downto 0);
47  
48 -- LED Display (8 digit with 7 segments and ddecimal point)
49 LD_A_n: out std_logic;
50 LD_B_n: out std_logic;
51 LD_C_n: out std_logic;
52 LD_D_n: out std_logic;
53 LD_E_n: out std_logic;
54 LD_F_n: out std_logic;
55 LD_G_n: out std_logic;
56 LD_DP_n: out std_logic;
57 LD_0_n: out std_logic;
58 LD_1_n: out std_logic;
59 LD_2_n: out std_logic;
60 LD_3_n: out std_logic;
61 LD_4_n: out std_logic;
62 LD_5_n: out std_logic;
63 LD_6_n: out std_logic;
64 LD_7_n: out std_logic;
65  
66 -- VGA Video Out Port
67 VGA_R: out std_logic_vector(1 downto 0);
68 VGA_G: out std_logic_vector(1 downto 0);
69 VGA_B: out std_logic_vector(1 downto 0);
70 VGA_VS: out std_logic;
71 VGA_HS: out std_logic;
72  
73 -- Bank 1 Pins - Inputs for this Test
74 B: inout std_logic_vector(24 downto 0);
75  
76 -- PS/2 Bidirectional Port (open collector, J31 and J32)
77 -- PS2_CLK1: inout std_logic;
78 -- PS2_DATA1: inout std_logic;
79 PS2_CLK2: inout std_logic;
80 PS2_DATA2: inout std_logic;
81  
82 -- Diferencial Signals on 4 pin header (J7)
83 DIF1P: inout std_logic;
84 DIF1N: inout std_logic;
85 DIF2P: inout std_logic;
86 DIF2N: inout std_logic;
87  
88  
89 -- I2C Signals (on connector J30)
90 I2C_SCL: inout std_logic;
91 I2C_SDA: inout std_logic;
92  
93 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
94 SD1AP: inout std_logic;
95 SD1AN: inout std_logic;
96 SD1BP: inout std_logic;
97 SD1BN: inout std_logic;
98 SD2AP: inout std_logic;
99 SD2AN: inout std_logic;
100 SD2BP: inout std_logic;
101 SD2BN: inout std_logic;
102  
103 -- Analog In Out
104 ANA_OUTD: out std_logic;
105 ANA_REFD: out std_logic;
106 ANA_IND: in std_logic;
107  
108 -- SPI Memory Interface
109 SPI_CS_n: inout std_logic;
110 SPI_DO: inout std_logic;
111 SPI_DI: inout std_logic;
112 SPI_CLK: inout std_logic;
113 SPI_WP_n: inout std_logic
114 );
115 end entity gtime;
116  
117  
118 architecture gtime_a of gtime is
119  
3176 kakl 120 function to_bcd ( bin : std_logic_vector(15 downto 0) ) return std_logic_vector is
3165 kakl 121 variable i : integer:=0;
3176 kakl 122 variable mybcd : std_logic_vector(19 downto 0) := (others => '0');
123 variable bint : std_logic_vector(15 downto 0) := bin;
3165 kakl 124 begin
3176 kakl 125 for i in 0 to 15 loop -- repeating 16 times.
126 mybcd(19 downto 1) := mybcd(18 downto 0); --shifting the bits.
127 mybcd(0) := bint(15);
128 bint(15 downto 1) := bint(14 downto 0);
3165 kakl 129 bint(0) :='0';
130  
131  
3176 kakl 132 if(i < 15 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
3165 kakl 133 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
134 end if;
135  
3176 kakl 136 if(i < 15 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
3165 kakl 137 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
138 end if;
139  
3176 kakl 140 if(i < 15 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
3165 kakl 141 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
142 end if;
3176 kakl 143  
144 if(i < 15 and mybcd(15 downto 12) > "0100") then --add 3 if BCD digit is greater than 4.
145 mybcd(15 downto 12) := std_logic_vector(unsigned(mybcd(15 downto 12)) + 3);
146 end if;
147  
148 if(i < 15 and mybcd(19 downto 16) > "0100") then --add 3 if BCD digit is greater than 4.
149 mybcd(19 downto 16) := std_logic_vector(unsigned(mybcd(19 downto 16)) + 3);
150 end if;
151  
3165 kakl 152 end loop;
153  
154 return mybcd;
155 end to_bcd;
156  
157  
158 -- LED Demo Signals
159 -- ----------------
160  
3176 kakl 161 signal Counter: unsigned(13 downto 0) := "00000000000000"; -- Main Counter 1 Hz, max. 9.999 kHz (binary)
162 signal CounterMaxcount: unsigned(14 downto 0) := "000000000000000"; -- Main Counter 10 kHz, max. 327.67 MHz (binary)
163 signal Bar: unsigned(7 downto 0) := X"00"; -- Register for Bar output (binary)
3165 kakl 164  
165  
166 -- LED Display
167 -- -----------
168  
3177 kakl 169 signal NumberPom: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
3176 kakl 170 signal Number: std_logic_vector(35 downto 0) := X"000000000"; -- LED Display Input
171 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
172 signal HalfFreq: std_logic_vector(31 downto 0);
3165 kakl 173 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
174 signal Enable: std_logic;
175 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
176 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
177 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
178  
179  
3166 kakl 180 signal LO_CLOCK: std_logic;
3177 kakl 181 signal EXT_CLOCK: std_logic;
3165 kakl 182  
3166 kakl 183 signal Decko: std_logic;
3173 kakl 184 signal State: unsigned(2 downto 0) := (others => '0');
185  
3165 kakl 186 begin
187  
3177 kakl 188 process (EXT_CLOCK)
189 begin
190  
191 if rising_edge(EXT_CLOCK) then
192 LO_CLOCK <= not LO_CLOCK;
193 end if;
194 end process;
195  
196  
3176 kakl 197 -- Counter
3165 kakl 198 process (LO_CLOCK)
199 begin
3173 kakl 200  
201 if rising_edge(LO_CLOCK) then
202  
203 if (State = 3) or (State = 0) then
3172 kakl 204 if Counter < MAXCOUNT-1 then
205 Counter <= Counter + 1;
206 else
207 Counter <= (others => '0');
3173 kakl 208 CounterMaxcount <= CounterMaxcount + 1;
3172 kakl 209 end if;
3165 kakl 210 end if;
3173 kakl 211 if (State = 1) then
3176 kakl 212 Freq(15 downto 0) <= std_logic_vector("00"&Counter);
213 Freq(31 downto 16) <= std_logic_vector("0"&CounterMaxcount);
3173 kakl 214 end if;
215 if (State = 2) then
216 CounterMaxcount <= (others => '0');
217 Counter <= (others => '0');
218 end if;
219 end if;
3165 kakl 220  
3172 kakl 221 end process;
3166 kakl 222  
3173 kakl 223  
3176 kakl 224 -- Sampling 1PPS signal
3166 kakl 225 process (LO_CLOCK)
226 begin
227 if rising_edge(LO_CLOCK) then
3176 kakl 228 Decko <= B(22);
3173 kakl 229 end if;
230 end process;
231  
3176 kakl 232 -- Automata for controling the Counter
3173 kakl 233 process (LO_CLOCK)
234 begin
235 if rising_edge(LO_CLOCK) then
236 if (Decko = '1') then
237 if (State < 3) then
238 State <= State + 1;
3166 kakl 239 end if;
240 else
3173 kakl 241 State <= (others => '0');
3166 kakl 242 end if;
243 end if;
244 end process;
3173 kakl 245  
3176 kakl 246 -- Coding to BCD for LED Display
3165 kakl 247  
3177 kakl 248 process (Decko)
249 begin
250 if falling_edge(Decko) then
251 NumberPom(15 downto 0) <= to_bcd(Freq(15 downto 0))(15 downto 0);
252 NumberPom(35 downto 16) <= to_bcd(Freq(31 downto 16))(19 downto 0);
253 end if;
254 end process;
3165 kakl 255  
3177 kakl 256 Number(35 downto 0) <= NumberPom(35 downto 0);
257  
3176 kakl 258 LED(7) <= Decko; -- Disply 1PPS pulse on LEDbar
259 LED(6 downto 4) <= (others => '0');
260 LED(3 downto 0) <= Number(35 downto 32); -- Disply 100-th of MHz on LEDbar
261  
3165 kakl 262 -- LED Display (multiplexed)
263 -- =========================
264  
265 -- Connect LED Display Output Ports (negative outputs)
266 LD_A_n <= not (Segments(0) and Enable);
267 LD_B_n <= not (Segments(1) and Enable);
268 LD_C_n <= not (Segments(2) and Enable);
269 LD_D_n <= not (Segments(3) and Enable);
270 LD_E_n <= not (Segments(4) and Enable);
271 LD_F_n <= not (Segments(5) and Enable);
272 LD_G_n <= not (Segments(6) and Enable);
273 LD_DP_n <= not (Segments(7) and Enable);
274  
275 LD_0_n <= not Digits(0);
276 LD_1_n <= not Digits(1);
277 LD_2_n <= not Digits(2);
278 LD_3_n <= not Digits(3);
279 LD_4_n <= not Digits(4);
280 LD_5_n <= not Digits(5);
281 LD_6_n <= not Digits(6);
282 LD_7_n <= not Digits(7);
283  
284 -- Time Multiplex
285 process (CLK100MHz)
286 begin
287 if rising_edge(CLK100MHz) then
288 if MuxCounter < MUXCOUNT-1 then
289 MuxCounter <= MuxCounter + 1;
290 else
291 MuxCounter <= (others => '0');
292 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
293 Enable <= '0';
294 end if;
295 if MuxCounter > (MUXCOUNT-4) then
296 Enable <= '1';
297 end if;
298 end if;
299 end process;
300  
3166 kakl 301 -- HEX to 7 Segmet Decoder
3165 kakl 302 -- -- A
303 -- | | F B
304 -- -- G
305 -- | | E C
306 -- -- D H
307 -- ABCDEFGH
308 Segments <= "11111100" when Code="0000" else -- Digit 0
309 "01100000" when Code="0001" else -- Digit 1
310 "11011010" when Code="0010" else -- Digit 2
311 "11110010" when Code="0011" else -- Digit 3
312 "01100110" when Code="0100" else -- Digit 4
313 "10110110" when Code="0101" else -- Digit 5
314 "10111110" when Code="0110" else -- Digit 6
315 "11100000" when Code="0111" else -- Digit 7
316 "11111110" when Code="1000" else -- Digit 8
317 "11110110" when Code="1001" else -- Digit 9
318 "11101110" when Code="1010" else -- Digit A
319 "00111110" when Code="1011" else -- Digit b
320 "10011100" when Code="1100" else -- Digit C
321 "01111010" when Code="1101" else -- Digit d
322 "10011110" when Code="1110" else -- Digit E
323 "10001110" when Code="1111" else -- Digit F
324 "00000000";
325  
326 Code <= Number( 3 downto 0) when Digits="00000001" else
327 Number( 7 downto 4) when Digits="00000010" else
328 Number(11 downto 8) when Digits="00000100" else
329 Number(15 downto 12) when Digits="00001000" else
330 Number(19 downto 16) when Digits="00010000" else
331 Number(23 downto 20) when Digits="00100000" else
332 Number(27 downto 24) when Digits="01000000" else
333 Number(31 downto 28) when Digits="10000000" else
334 "0000";
335  
336  
337  
3166 kakl 338 -- Diferencial In/Outs
3165 kakl 339 -- ========================
340 DIFbuffer1 : IBUFGDS
341 generic map (
3173 kakl 342 DIFF_TERM => FALSE, -- Differential Termination
3176 kakl 343 IBUF_DELAY_VALUE => "16", -- Specify the amount of added input delay for buffer,
3165 kakl 344 -- "0"-"16"
345 IOSTANDARD => "DEFAULT")
346 port map (
347 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
348 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
3177 kakl 349 O => EXT_CLOCK -- Buffer output
3165 kakl 350 );
351  
3176 kakl 352 OBUFDS_inst : OBUFDS
353 generic map (
354 IOSTANDARD => "DEFAULT")
355 port map (
356 O => SD2AP, -- Diff_p output (connect directly to top-level port)
357 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
3177 kakl 358 I => EXT_CLOCK -- Buffer input
3176 kakl 359 );
3165 kakl 360  
361 -- Output Signal on SATA Connector
3166 kakl 362 -- SD1AP <= 'Z';
363 -- SD1AN <= 'Z';
3165 kakl 364 SD1BP <= 'Z';
365 SD1BN <= 'Z';
366  
367 -- Input Here via SATA Cable
3176 kakl 368 -- SD2AP <= 'Z';
369 -- SD2AN <= 'Z';
3165 kakl 370 SD2BP <= 'Z';
371 SD2BN <= 'Z';
372  
373  
374 -- Unused Signals
375 -- ==============
376  
377 -- I2C Signals (on connector J30)
378 I2C_SCL <= 'Z';
379 I2C_SDA <= 'Z';
380  
381 -- SPI Memory Interface
382 SPI_CS_n <= 'Z';
383 SPI_DO <= 'Z';
384 SPI_DI <= 'Z';
385 SPI_CLK <= 'Z';
386 SPI_WP_n <= 'Z';
387  
388 ANA_OUTD <= 'Z';
389 ANA_REFD <= 'Z';
390  
391 VGA_R <= "ZZ";
392 VGA_G <= "ZZ";
393 VGA_B <= "ZZ";
394 VGA_VS <= 'Z';
395 VGA_HS <= 'Z';
396  
397 end architecture gtime_a;