Rev Author Line No. Line
3165 kakl 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz
3 -- Based on code written by MIHO.
4 --
5 -- HW Design Name: S3AN01A
6 -- Project Name: gtime
7 -- Target Devices: XC3S50AN-4
8 -- Tool versions: ISE 13.3
9 -- Description: Time and frequency synchronisation for RDMS01A.
10 --
3223 kakl 11 -- Dependencies: CLKGEN01B, GPS01A, STM32F10xRxT01A
3165 kakl 12 --
3172 kakl 13 -- Version: $Id: gtime.vhd 3223 2013-07-25 22:41:43Z kakl $
3165 kakl 14 --
15 ----------------------------------------------------------------------------------
16  
17 library IEEE;
18 use IEEE.STD_LOGIC_1164.ALL;
19 use IEEE.numeric_std.ALL;
20  
21 library UNISIM;
22 use UNISIM.vcomponents.all;
23  
24 entity gtime is
25 generic (
26 -- Top Value for 100MHz Clock Counter
3219 kakl 27 MAXCOUNT: integer := 10_000; -- Maximum for the first counter
3165 kakl 28 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
29 );
30 port (
3219 kakl 31 -- Clock on PCB
3165 kakl 32 CLK100MHz: in std_logic;
3219 kakl 33  
3165 kakl 34 -- Mode Signals (usualy not used)
35 M: in std_logic_vector(2 downto 0);
36 VS: in std_logic_vector(2 downto 0);
37  
38 -- Dipswitch Inputs
39 DIPSW: in std_logic_vector(7 downto 0);
40  
41 -- Push Buttons
42 PB: in std_logic_vector(3 downto 0);
43  
44 -- LED Bar Outputs
45 LED: out std_logic_vector(7 downto 0);
46  
47 -- LED Display (8 digit with 7 segments and ddecimal point)
48 LD_A_n: out std_logic;
49 LD_B_n: out std_logic;
50 LD_C_n: out std_logic;
51 LD_D_n: out std_logic;
52 LD_E_n: out std_logic;
53 LD_F_n: out std_logic;
54 LD_G_n: out std_logic;
55 LD_DP_n: out std_logic;
56 LD_0_n: out std_logic;
57 LD_1_n: out std_logic;
58 LD_2_n: out std_logic;
59 LD_3_n: out std_logic;
60 LD_4_n: out std_logic;
61 LD_5_n: out std_logic;
62 LD_6_n: out std_logic;
63 LD_7_n: out std_logic;
64  
65 -- VGA Video Out Port
66 VGA_R: out std_logic_vector(1 downto 0);
67 VGA_G: out std_logic_vector(1 downto 0);
68 VGA_B: out std_logic_vector(1 downto 0);
69 VGA_VS: out std_logic;
70 VGA_HS: out std_logic;
71  
72 -- Bank 1 Pins - Inputs for this Test
73 B: inout std_logic_vector(24 downto 0);
74  
75 -- PS/2 Bidirectional Port (open collector, J31 and J32)
3219 kakl 76 PS2_CLK1: inout std_logic;
77 PS2_DATA1: inout std_logic;
3165 kakl 78 PS2_CLK2: inout std_logic;
79 PS2_DATA2: inout std_logic;
80  
81 -- Diferencial Signals on 4 pin header (J7)
82 DIF1P: inout std_logic;
83 DIF1N: inout std_logic;
84 DIF2P: inout std_logic;
85 DIF2N: inout std_logic;
86  
87  
88 -- I2C Signals (on connector J30)
89 I2C_SCL: inout std_logic;
90 I2C_SDA: inout std_logic;
91  
92 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
93 SD1AP: inout std_logic;
94 SD1AN: inout std_logic;
95 SD1BP: inout std_logic;
96 SD1BN: inout std_logic;
97 SD2AP: inout std_logic;
98 SD2AN: inout std_logic;
99 SD2BP: inout std_logic;
100 SD2BN: inout std_logic;
101  
102 -- Analog In Out
103 ANA_OUTD: out std_logic;
104 ANA_REFD: out std_logic;
105 ANA_IND: in std_logic;
106  
107 -- SPI Memory Interface
108 SPI_CS_n: inout std_logic;
109 SPI_DO: inout std_logic;
110 SPI_DI: inout std_logic;
111 SPI_CLK: inout std_logic;
112 SPI_WP_n: inout std_logic
113 );
114 end entity gtime;
115  
116  
117 architecture gtime_a of gtime is
118  
3176 kakl 119  
3219 kakl 120 -- Counter
3165 kakl 121 -- ----------------
122  
3219 kakl 123 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter 2 Hz (binary)
3165 kakl 124  
125  
126 -- LED Display
127 -- -----------
128  
3219 kakl 129 signal Number: std_logic_vector(31 downto 0) := X"00000000"; -- LED Display Input
3176 kakl 130 signal Freq: std_logic_vector(31 downto 0) := X"00000000"; -- Measured Frequency
3165 kakl 131 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
132 signal Enable: std_logic;
133 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
134 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
135 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
136  
137  
3219 kakl 138 -- signal LO_CLOCK: std_logic; -- Frequency divided by 2
139 signal EXT_CLOCK: std_logic; -- Input Frequency
3165 kakl 140  
3219 kakl 141 signal Decko: std_logic; -- D flip-flop
142 signal State: unsigned(2 downto 0) := (others => '0'); -- Inner states of automata
3173 kakl 143  
3219 kakl 144 signal SCLK: std_logic;
145 signal SCLK2: std_logic;
146  
147  
3165 kakl 148 begin
149  
3219 kakl 150 -- Counter
3177 kakl 151 process (EXT_CLOCK)
152 begin
153  
154 if rising_edge(EXT_CLOCK) then
3173 kakl 155  
3219 kakl 156 if (State = 2) or (State = 0) then
157 Counter <= Counter + 1;
3165 kakl 158 end if;
3173 kakl 159 if (State = 1) then
3219 kakl 160 Freq(31 downto 0) <= std_logic_vector(Counter);
3173 kakl 161 Counter <= (others => '0');
162 end if;
163 end if;
3165 kakl 164  
3172 kakl 165 end process;
3166 kakl 166  
3173 kakl 167  
3176 kakl 168 -- Sampling 1PPS signal
3219 kakl 169 process (EXT_CLOCK)
3166 kakl 170 begin
3219 kakl 171 if rising_edge(EXT_CLOCK) then
3176 kakl 172 Decko <= B(22);
3173 kakl 173 end if;
174 end process;
175  
3219 kakl 176 -- Automata for controlling the Counter
177 process (EXT_CLOCK)
3173 kakl 178 begin
3219 kakl 179 if rising_edge(EXT_CLOCK) then
3173 kakl 180 if (Decko = '1') then
3219 kakl 181 if (State < 2) then
3173 kakl 182 State <= State + 1;
3166 kakl 183 end if;
184 else
3173 kakl 185 State <= (others => '0');
3166 kakl 186 end if;
187 end if;
188 end process;
3173 kakl 189  
3177 kakl 190 process (Decko)
191 begin
3219 kakl 192 if Decko = '0' then
193 LED(6) <= '1';
194 else
195 LED(6) <= '0';
3177 kakl 196 end if;
197 end process;
198  
3219 kakl 199 SCLK <= B(0);
200  
3223 kakl 201 -- Output Shift Register
3219 kakl 202 process (Decko,SCLK)
203 begin
204 if (Decko = '0') then
205 Number(31 downto 0) <= Freq(31 downto 0);
206 else
207 if rising_edge(SCLK) then
208 Number(30 downto 0) <= Number(31 downto 1);
209 end if;
210 end if;
211 end process;
3176 kakl 212  
3219 kakl 213 B(1) <= Number(0);
214 B(2) <= Decko;
215  
216 LED(7) <= Decko; -- Display 1PPS pulse on LEDbar
217 LED(5 downto 0) <= (others => '0');
218  
3165 kakl 219 -- LED Display (multiplexed)
220 -- =========================
221  
222 -- Connect LED Display Output Ports (negative outputs)
223 LD_A_n <= not (Segments(0) and Enable);
224 LD_B_n <= not (Segments(1) and Enable);
225 LD_C_n <= not (Segments(2) and Enable);
226 LD_D_n <= not (Segments(3) and Enable);
227 LD_E_n <= not (Segments(4) and Enable);
228 LD_F_n <= not (Segments(5) and Enable);
229 LD_G_n <= not (Segments(6) and Enable);
230 LD_DP_n <= not (Segments(7) and Enable);
231  
232 LD_0_n <= not Digits(0);
233 LD_1_n <= not Digits(1);
234 LD_2_n <= not Digits(2);
235 LD_3_n <= not Digits(3);
236 LD_4_n <= not Digits(4);
237 LD_5_n <= not Digits(5);
238 LD_6_n <= not Digits(6);
239 LD_7_n <= not Digits(7);
240  
241 -- Time Multiplex
242 process (CLK100MHz)
243 begin
244 if rising_edge(CLK100MHz) then
245 if MuxCounter < MUXCOUNT-1 then
246 MuxCounter <= MuxCounter + 1;
247 else
248 MuxCounter <= (others => '0');
249 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
250 Enable <= '0';
251 end if;
252 if MuxCounter > (MUXCOUNT-4) then
253 Enable <= '1';
254 end if;
255 end if;
256 end process;
257  
3166 kakl 258 -- HEX to 7 Segmet Decoder
3165 kakl 259 -- -- A
260 -- | | F B
261 -- -- G
262 -- | | E C
263 -- -- D H
264 -- ABCDEFGH
265 Segments <= "11111100" when Code="0000" else -- Digit 0
266 "01100000" when Code="0001" else -- Digit 1
267 "11011010" when Code="0010" else -- Digit 2
268 "11110010" when Code="0011" else -- Digit 3
269 "01100110" when Code="0100" else -- Digit 4
270 "10110110" when Code="0101" else -- Digit 5
271 "10111110" when Code="0110" else -- Digit 6
272 "11100000" when Code="0111" else -- Digit 7
273 "11111110" when Code="1000" else -- Digit 8
274 "11110110" when Code="1001" else -- Digit 9
275 "11101110" when Code="1010" else -- Digit A
276 "00111110" when Code="1011" else -- Digit b
277 "10011100" when Code="1100" else -- Digit C
278 "01111010" when Code="1101" else -- Digit d
279 "10011110" when Code="1110" else -- Digit E
280 "10001110" when Code="1111" else -- Digit F
281 "00000000";
282  
283 Code <= Number( 3 downto 0) when Digits="00000001" else
284 Number( 7 downto 4) when Digits="00000010" else
285 Number(11 downto 8) when Digits="00000100" else
286 Number(15 downto 12) when Digits="00001000" else
287 Number(19 downto 16) when Digits="00010000" else
288 Number(23 downto 20) when Digits="00100000" else
289 Number(27 downto 24) when Digits="01000000" else
290 Number(31 downto 28) when Digits="10000000" else
291 "0000";
292  
293  
3166 kakl 294 -- Diferencial In/Outs
3165 kakl 295 -- ========================
296 DIFbuffer1 : IBUFGDS
297 generic map (
3173 kakl 298 DIFF_TERM => FALSE, -- Differential Termination
3219 kakl 299 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
3165 kakl 300 -- "0"-"16"
3219 kakl 301 IOSTANDARD => "LVPECL_33")
3165 kakl 302 port map (
303 I => SD1AP, -- Diff_p buffer input (connect directly to top-level port)
304 IB => SD1AN, -- Diff_n buffer input (connect directly to top-level port)
3219 kakl 305 O => EXT_CLOCK -- Buffer output - Counter INPUT
3165 kakl 306 );
307  
3176 kakl 308 OBUFDS_inst : OBUFDS
309 generic map (
3219 kakl 310 IOSTANDARD => "LVDS_33")
3176 kakl 311 port map (
312 O => SD2AP, -- Diff_p output (connect directly to top-level port)
313 OB => SD2AN, -- Diff_n output (connect directly to top-level port)
3219 kakl 314 I => EXT_CLOCK -- Buffer input are connected directly to IBUFGDS
3176 kakl 315 );
3165 kakl 316  
317 -- Output Signal on SATA Connector
3219 kakl 318 -- SD1AP <= 'Z'; -- Counter INPUT
3166 kakl 319 -- SD1AN <= 'Z';
3165 kakl 320 SD1BP <= 'Z';
321 SD1BN <= 'Z';
322  
323 -- Input Here via SATA Cable
3219 kakl 324 -- SD2AP <= 'Z'; -- Counter OUTPUT
3176 kakl 325 -- SD2AN <= 'Z';
3165 kakl 326 SD2BP <= 'Z';
327 SD2BN <= 'Z';
328  
329  
330 -- Unused Signals
331 -- ==============
332  
3219 kakl 333 -- Differential inputs onn header
334 DIF1N <= 'Z';
335 DIF1P <= 'Z';
336 DIF2N <= 'Z';
337 DIF2P <= 'Z';
338  
3165 kakl 339 -- I2C Signals (on connector J30)
340 I2C_SCL <= 'Z';
341 I2C_SDA <= 'Z';
342  
343 -- SPI Memory Interface
344 SPI_CS_n <= 'Z';
345 SPI_DO <= 'Z';
346 SPI_DI <= 'Z';
347 SPI_CLK <= 'Z';
348 SPI_WP_n <= 'Z';
349  
3219 kakl 350 -- A/D
3165 kakl 351 ANA_OUTD <= 'Z';
352 ANA_REFD <= 'Z';
353  
3219 kakl 354 -- VGA
3165 kakl 355 VGA_R <= "ZZ";
356 VGA_G <= "ZZ";
357 VGA_B <= "ZZ";
358 VGA_VS <= 'Z';
359 VGA_HS <= 'Z';
360  
3219 kakl 361 -- PS2
362 PS2_DATA2 <= 'Z';
363 PS2_CLK2 <='Z';
364  
3165 kakl 365 end architecture gtime_a;