Rev Author Line No. Line
3047 miho 1 // ------------------------------------------------------------------
2 //
3 // TRAIN01A and TRAN02A MLAB Module Hardware Definition
4 //
5 // (c) miho WWW.MLAB.CZ/PermaLink/TRAIN
6 //
7 // ------------------------------------------------------------------
8  
9  
10 // Timer
11 #define F_CPU 8000000UL // Internal RC Oscillator 8MHz
12  
13  
14 // Input bits port definitions
15 #define SW_PORT_0 C // Port PC5
16 #define SW_DATA_0 5
17  
18 #define SW_PORT_1 C // Port PC4
19 #define SW_DATA_1 4
20  
21 #define SW_PORT_2 C // Port PC3
22 #define SW_DATA_2 3
23  
24 #define SW_PORT_3 C // Port PC2
25 #define SW_DATA_3 2
26  
27 #define SW_PORT_4 C // Port PC1
28 #define SW_DATA_4 1
29  
30 #define SW_PORT_5 C // Port PC0
31 #define SW_DATA_5 0
32  
33 #define SW_PORT_6 B // Port PB5
34 #define SW_DATA_6 5
35  
36 #define SW_PORT_7 B // Port PB2
37 #define SW_DATA_7 2
38  
39  
40 // Output bits port definitions
41 #define RE_PORT_0 B // Port PB1
42 #define RE_DATA_0 1
43  
44 #define RE_PORT_1 B // Port PB0
45 #define RE_DATA_1 0
46  
47 #define RE_PORT_2 D // Port PD7
48 #define RE_DATA_2 7
49  
50 #define RE_PORT_3 D // Port PD6
51 #define RE_DATA_3 6
52  
53 #define RE_PORT_4 D // Port PD5
54 #define RE_DATA_4 5
55  
56 #define RE_PORT_5 D // Port PD4
57 #define RE_DATA_5 4
58  
59 #define RE_PORT_6 D // Port PD3
60 #define RE_DATA_6 3
61  
62 #define RE_PORT_7 D // Port PD2
63 #define RE_DATA_7 2
64  
65  
66 //--------------------------------------------------------
67  
68  
69 // Macros
70 #define GLUE(a,b) a##b
71 #define PORT(a) GLUE(PORT,a)
72 #define PIN(a) GLUE(PIN,a)
73 #define DDR(a) GLUE(DDR,a)
74  
75  
76 // Output port tables - DDR
77 volatile uint8_t * RE_DDR_Table[8] =
78 {
79 &DDR(RE_PORT_0),
80 &DDR(RE_PORT_1),
81 &DDR(RE_PORT_2),
82 &DDR(RE_PORT_3),
83 &DDR(RE_PORT_4),
84 &DDR(RE_PORT_5),
85 &DDR(RE_PORT_6),
86 &DDR(RE_PORT_7)
87 };
88  
89 // Output port tables - PORT
90 volatile uint8_t * RE_PORT_Table[8] =
91 {
92 &PORT(RE_PORT_0),
93 &PORT(RE_PORT_1),
94 &PORT(RE_PORT_2),
95 &PORT(RE_PORT_3),
96 &PORT(RE_PORT_4),
97 &PORT(RE_PORT_5),
98 &PORT(RE_PORT_6),
99 &PORT(RE_PORT_7)
100 };
101  
102 // Output port tables - MASK
103 unsigned char RE_BIT_MASK[8] =
104 {
105 1<<RE_DATA_0,
106 1<<RE_DATA_1,
107 1<<RE_DATA_2,
108 1<<RE_DATA_3,
109 1<<RE_DATA_4,
110 1<<RE_DATA_5,
111 1<<RE_DATA_6,
112 1<<RE_DATA_7
113 };
114  
115  
116 // Input port tables - PORT
117 volatile uint8_t * SW_PORT_Table[8] =
118 {
119 &PORT(SW_PORT_0),
120 &PORT(SW_PORT_1),
121 &PORT(SW_PORT_2),
122 &PORT(SW_PORT_3),
123 &PORT(SW_PORT_4),
124 &PORT(SW_PORT_5),
125 &PORT(SW_PORT_6),
126 &PORT(SW_PORT_7)
127 };
128  
129 // Input port tables - PIN
130 volatile uint8_t * SW_PIN_Table[8] =
131 {
132 &PIN(SW_PORT_0),
133 &PIN(SW_PORT_1),
134 &PIN(SW_PORT_2),
135 &PIN(SW_PORT_3),
136 &PIN(SW_PORT_4),
137 &PIN(SW_PORT_5),
138 &PIN(SW_PORT_6),
139 &PIN(SW_PORT_7)
140 };
141  
142 // Input port tables - MASK
143 unsigned char SW_BIT_MASK[8] =
144 {
145 1<<SW_DATA_0,
146 1<<SW_DATA_1,
147 1<<SW_DATA_2,
148 1<<SW_DATA_3,
149 1<<SW_DATA_4,
150 1<<SW_DATA_5,
151 1<<SW_DATA_6,
152 1<<SW_DATA_7
153 };