Rev Author Line No. Line
2067 kakl 1 /**
2 ******************************************************************************
3 * @file stm32f10x_rcc.h
4 * @author MCD Application Team
5 * @version V3.4.0
6 * @date 10/15/2010
7 * @brief This file contains all the functions prototypes for the RCC firmware
8 * library.
9 ******************************************************************************
10 * @copy
11 *
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 *
19 * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
20 */
21  
22 /* Define to prevent recursive inclusion -------------------------------------*/
23 #ifndef __STM32F10x_RCC_H
24 #define __STM32F10x_RCC_H
25  
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29  
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32f10x.h"
32  
33 /** @addtogroup STM32F10x_StdPeriph_Driver
34 * @{
35 */
36  
37 /** @addtogroup RCC
38 * @{
39 */
40  
41 /** @defgroup RCC_Exported_Types
42 * @{
43 */
44  
45 typedef struct
46 {
47 uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
48 uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
49 uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
50 uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
51 uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
52 }RCC_ClocksTypeDef;
53  
54 /**
55 * @}
56 */
57  
58 /** @defgroup RCC_Exported_Constants
59 * @{
60 */
61  
62 /** @defgroup HSE_configuration
63 * @{
64 */
65  
66 #define RCC_HSE_OFF ((uint32_t)0x00000000)
67 #define RCC_HSE_ON ((uint32_t)0x00010000)
68 #define RCC_HSE_Bypass ((uint32_t)0x00040000)
69 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
70 ((HSE) == RCC_HSE_Bypass))
71  
72 /**
73 * @}
74 */
75  
76 /** @defgroup PLL_entry_clock_source
77 * @{
78 */
79  
80 #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
81  
82 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
83 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
84 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
85 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
86 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
87 ((SOURCE) == RCC_PLLSource_HSE_Div2))
88 #else
89 #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
90 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
91 ((SOURCE) == RCC_PLLSource_PREDIV1))
92 #endif /* STM32F10X_CL */
93  
94 /**
95 * @}
96 */
97  
98 /** @defgroup PLL_multiplication_factor
99 * @{
100 */
101 #ifndef STM32F10X_CL
102 #define RCC_PLLMul_2 ((uint32_t)0x00000000)
103 #define RCC_PLLMul_3 ((uint32_t)0x00040000)
104 #define RCC_PLLMul_4 ((uint32_t)0x00080000)
105 #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
106 #define RCC_PLLMul_6 ((uint32_t)0x00100000)
107 #define RCC_PLLMul_7 ((uint32_t)0x00140000)
108 #define RCC_PLLMul_8 ((uint32_t)0x00180000)
109 #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
110 #define RCC_PLLMul_10 ((uint32_t)0x00200000)
111 #define RCC_PLLMul_11 ((uint32_t)0x00240000)
112 #define RCC_PLLMul_12 ((uint32_t)0x00280000)
113 #define RCC_PLLMul_13 ((uint32_t)0x002C0000)
114 #define RCC_PLLMul_14 ((uint32_t)0x00300000)
115 #define RCC_PLLMul_15 ((uint32_t)0x00340000)
116 #define RCC_PLLMul_16 ((uint32_t)0x00380000)
117 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
118 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
119 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
120 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
121 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
122 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
123 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
124 ((MUL) == RCC_PLLMul_16))
125  
126 #else
127 #define RCC_PLLMul_4 ((uint32_t)0x00080000)
128 #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
129 #define RCC_PLLMul_6 ((uint32_t)0x00100000)
130 #define RCC_PLLMul_7 ((uint32_t)0x00140000)
131 #define RCC_PLLMul_8 ((uint32_t)0x00180000)
132 #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
133 #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
134  
135 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
136 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
137 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
138 ((MUL) == RCC_PLLMul_6_5))
139 #endif /* STM32F10X_CL */
140 /**
141 * @}
142 */
143  
144 /** @defgroup PREDIV1_division_factor
145 * @{
146 */
147 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
148 #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
149 #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
150 #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
151 #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
152 #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
153 #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
154 #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
155 #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
156 #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
157 #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
158 #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
159 #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
160 #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
161 #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
162 #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
163 #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
164  
165 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
166 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
167 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
168 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
169 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
170 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
171 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
172 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
173 #endif
174 /**
175 * @}
176 */
177  
178  
179 /** @defgroup PREDIV1_clock_source
180 * @{
181 */
182 #ifdef STM32F10X_CL
183 /* PREDIV1 clock source (for STM32 connectivity line devices) */
184 #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
185 #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
186  
187 #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
188 ((SOURCE) == RCC_PREDIV1_Source_PLL2))
189 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
190 /* PREDIV1 clock source (for STM32 Value line devices) */
191 #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
192  
193 #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
194 #endif
195 /**
196 * @}
197 */
198  
199 #ifdef STM32F10X_CL
200 /** @defgroup PREDIV2_division_factor
201 * @{
202 */
203  
204 #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
205 #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
206 #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
207 #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
208 #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
209 #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
210 #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
211 #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
212 #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
213 #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
214 #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
215 #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
216 #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
217 #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
218 #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
219 #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
220  
221 #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
222 ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
223 ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
224 ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
225 ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
226 ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
227 ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
228 ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
229 /**
230 * @}
231 */
232  
233  
234 /** @defgroup PLL2_multiplication_factor
235 * @{
236 */
237  
238 #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
239 #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
240 #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
241 #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
242 #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
243 #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
244 #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
245 #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
246 #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
247  
248 #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
249 ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
250 ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
251 ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
252 ((MUL) == RCC_PLL2Mul_20))
253 /**
254 * @}
255 */
256  
257  
258 /** @defgroup PLL3_multiplication_factor
259 * @{
260 */
261  
262 #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
263 #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
264 #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
265 #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
266 #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
267 #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
268 #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
269 #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
270 #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
271  
272 #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
273 ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
274 ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
275 ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
276 ((MUL) == RCC_PLL3Mul_20))
277 /**
278 * @}
279 */
280  
281 #endif /* STM32F10X_CL */
282  
283  
284 /** @defgroup System_clock_source
285 * @{
286 */
287  
288 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
289 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
290 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
291 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
292 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
293 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
294 /**
295 * @}
296 */
297  
298 /** @defgroup AHB_clock_source
299 * @{
300 */
301  
302 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
303 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
304 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
305 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
306 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
307 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
308 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
309 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
310 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
311 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
312 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
313 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
314 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
315 ((HCLK) == RCC_SYSCLK_Div512))
316 /**
317 * @}
318 */
319  
320 /** @defgroup APB1_APB2_clock_source
321 * @{
322 */
323  
324 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
325 #define RCC_HCLK_Div2 ((uint32_t)0x00000400)
326 #define RCC_HCLK_Div4 ((uint32_t)0x00000500)
327 #define RCC_HCLK_Div8 ((uint32_t)0x00000600)
328 #define RCC_HCLK_Div16 ((uint32_t)0x00000700)
329 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
330 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
331 ((PCLK) == RCC_HCLK_Div16))
332 /**
333 * @}
334 */
335  
336 /** @defgroup RCC_Interrupt_source
337 * @{
338 */
339  
340 #define RCC_IT_LSIRDY ((uint8_t)0x01)
341 #define RCC_IT_LSERDY ((uint8_t)0x02)
342 #define RCC_IT_HSIRDY ((uint8_t)0x04)
343 #define RCC_IT_HSERDY ((uint8_t)0x08)
344 #define RCC_IT_PLLRDY ((uint8_t)0x10)
345 #define RCC_IT_CSS ((uint8_t)0x80)
346  
347 #ifndef STM32F10X_CL
348 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
349 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
350 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
351 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
352 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
353 #else
354 #define RCC_IT_PLL2RDY ((uint8_t)0x20)
355 #define RCC_IT_PLL3RDY ((uint8_t)0x40)
356 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
357 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
358 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
359 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
360 ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
361 #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
362 #endif /* STM32F10X_CL */
363  
364  
365 /**
366 * @}
367 */
368  
369 #ifndef STM32F10X_CL
370 /** @defgroup USB_Device_clock_source
371 * @{
372 */
373  
374 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
375 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
376  
377 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
378 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
379 /**
380 * @}
381 */
382 #else
383 /** @defgroup USB_OTG_FS_clock_source
384 * @{
385 */
386 #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
387 #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
388  
389 #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
390 ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
391 /**
392 * @}
393 */
394 #endif /* STM32F10X_CL */
395  
396  
397 #ifdef STM32F10X_CL
398 /** @defgroup I2S2_clock_source
399 * @{
400 */
401 #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
402 #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
403  
404 #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
405 ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
406 /**
407 * @}
408 */
409  
410 /** @defgroup I2S3_clock_source
411 * @{
412 */
413 #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
414 #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
415  
416 #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
417 ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
418 /**
419 * @}
420 */
421 #endif /* STM32F10X_CL */
422  
423  
424 /** @defgroup ADC_clock_source
425 * @{
426 */
427  
428 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
429 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
430 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
431 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
432 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
433 ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
434 /**
435 * @}
436 */
437  
438 /** @defgroup LSE_configuration
439 * @{
440 */
441  
442 #define RCC_LSE_OFF ((uint8_t)0x00)
443 #define RCC_LSE_ON ((uint8_t)0x01)
444 #define RCC_LSE_Bypass ((uint8_t)0x04)
445 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
446 ((LSE) == RCC_LSE_Bypass))
447 /**
448 * @}
449 */
450  
451 /** @defgroup RTC_clock_source
452 * @{
453 */
454  
455 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
456 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
457 #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
458 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
459 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
460 ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
461 /**
462 * @}
463 */
464  
465 /** @defgroup AHB_peripheral
466 * @{
467 */
468  
469 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
470 #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
471 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
472 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
473 #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
474  
475 #ifndef STM32F10X_CL
476 #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
477 #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
478 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
479 #else
480 #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
481 #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
482 #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
483 #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
484  
485 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
486 #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
487 #endif /* STM32F10X_CL */
488 /**
489 * @}
490 */
491  
492 /** @defgroup APB2_peripheral
493 * @{
494 */
495  
496 #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
497 #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
498 #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
499 #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
500 #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
501 #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
502 #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
503 #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
504 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
505 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
506 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
507 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
508 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
509 #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
510 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
511 #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
512 #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
513 #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
514 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
515 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
516 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
517  
518 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
519 /**
520 * @}
521 */
522  
523 /** @defgroup APB1_peripheral
524 * @{
525 */
526  
527 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
528 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
529 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
530 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
531 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
532 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
533 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
534 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
535 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
536 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
537 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
538 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
539 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
540 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
541 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
542 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
543 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
544 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
545 #define RCC_APB1Periph_USB ((uint32_t)0x00800000)
546 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
547 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
548 #define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
549 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
550 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
551 #define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
552  
553 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
554  
555 /**
556 * @}
557 */
558  
559 /** @defgroup Clock_source_to_output_on_MCO_pin
560 * @{
561 */
562  
563 #define RCC_MCO_NoClock ((uint8_t)0x00)
564 #define RCC_MCO_SYSCLK ((uint8_t)0x04)
565 #define RCC_MCO_HSI ((uint8_t)0x05)
566 #define RCC_MCO_HSE ((uint8_t)0x06)
567 #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
568  
569 #ifndef STM32F10X_CL
570 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
571 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
572 ((MCO) == RCC_MCO_PLLCLK_Div2))
573 #else
574 #define RCC_MCO_PLL2CLK ((uint8_t)0x08)
575 #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
576 #define RCC_MCO_XT1 ((uint8_t)0x0A)
577 #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
578  
579 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
580 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
581 ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
582 ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
583 ((MCO) == RCC_MCO_PLL3CLK))
584 #endif /* STM32F10X_CL */
585  
586 /**
587 * @}
588 */
589  
590 /** @defgroup RCC_Flag
591 * @{
592 */
593  
594 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
595 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
596 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
597 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
598 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
599 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
600 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
601 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
602 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
603 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
604 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
605  
606 #ifndef STM32F10X_CL
607 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
608 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
609 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
610 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
611 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
612 ((FLAG) == RCC_FLAG_LPWRRST))
613 #else
614 #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
615 #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
616 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
617 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
618 ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
619 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
620 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
621 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
622 ((FLAG) == RCC_FLAG_LPWRRST))
623 #endif /* STM32F10X_CL */
624  
625 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
626 /**
627 * @}
628 */
629  
630 /**
631 * @}
632 */
633  
634 /** @defgroup RCC_Exported_Macros
635 * @{
636 */
637  
638 /**
639 * @}
640 */
641  
642 /** @defgroup RCC_Exported_Functions
643 * @{
644 */
645  
646 void RCC_DeInit(void);
647 void RCC_HSEConfig(uint32_t RCC_HSE);
648 ErrorStatus RCC_WaitForHSEStartUp(void);
649 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
650 void RCC_HSICmd(FunctionalState NewState);
651 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
652 void RCC_PLLCmd(FunctionalState NewState);
653  
654 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
655 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
656 #endif
657  
658 #ifdef STM32F10X_CL
659 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
660 void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
661 void RCC_PLL2Cmd(FunctionalState NewState);
662 void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
663 void RCC_PLL3Cmd(FunctionalState NewState);
664 #endif /* STM32F10X_CL */
665  
666 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
667 uint8_t RCC_GetSYSCLKSource(void);
668 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
669 void RCC_PCLK1Config(uint32_t RCC_HCLK);
670 void RCC_PCLK2Config(uint32_t RCC_HCLK);
671 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
672  
673 #ifndef STM32F10X_CL
674 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
675 #else
676 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
677 #endif /* STM32F10X_CL */
678  
679 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
680  
681 #ifdef STM32F10X_CL
682 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
683 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
684 #endif /* STM32F10X_CL */
685  
686 void RCC_LSEConfig(uint8_t RCC_LSE);
687 void RCC_LSICmd(FunctionalState NewState);
688 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
689 void RCC_RTCCLKCmd(FunctionalState NewState);
690 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
691 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
692 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
693 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
694  
695 #ifdef STM32F10X_CL
696 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
697 #endif /* STM32F10X_CL */
698  
699 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
700 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
701 void RCC_BackupResetCmd(FunctionalState NewState);
702 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
703 void RCC_MCOConfig(uint8_t RCC_MCO);
704 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
705 void RCC_ClearFlag(void);
706 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
707 void RCC_ClearITPendingBit(uint8_t RCC_IT);
708  
709 #ifdef __cplusplus
710 }
711 #endif
712  
713 #endif /* __STM32F10x_RCC_H */
714 /**
715 * @}
716 */
717  
718 /**
719 * @}
720 */
721  
722 /**
723 * @}
724 */
725  
726 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/