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miho

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; ======================================================================

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; USB interrupt handler

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;

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; This is the handler for the interrupt caused by the initial rising edge

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; on the D+ USB signal. The NRZI encoding and bit stuffing are removed,

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; and the packet is saved in one of the two input buffers. In some cases,

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; a reply packet is sent right away.

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;

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; When a DATA0/DATA1 packet directly follows a SETUP or OUT packet, while

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; this interrupt handler is not yet finished, there would be no time to

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; return and take another interrupt. In that case, the second packet is

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; decoded directly in the same invocation.

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;

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; This code is *extremely* time critical. For instance, there is not a

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; single spare cycle in the receiver loop, and only two in the transmitter

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; loop. In addition, the various code paths are laid out in such a way that

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; the various USB timeouts are not violated, in particular the maximum time

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; between the reception of a packet and the reply, which is 6.5 bit times

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; for a detachable cable (TRSPIPD1), and 7.5 bit times for a captive cable

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; (TRSPIPD2). The worst-case delay here is 51 cycles, which is just below

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; the 52 cycles for a detachable cable.

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;

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; The interrupt handler must be reached within 34 cycles after D+ goes high

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; for the first time, so the interrupts should not be disabled for longer

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; than 34-4-2=28 cycles.

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;

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; The end-of-packet (EOP) is sampled in the second bit, because the USB

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; standard allows the EOP to be delayed by up to one bit. As the EOP

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; duration is two bits, this is not a problem.

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;

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; Stack usage including the return address: 11 bytes.

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;

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;

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; This is free software, licensed under the terms of the GNU General

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; Public License as published by the Free Software Foundation.

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; ======================================================================

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#include "def.h"

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; ----------------------------------------------------------------------

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; local data

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; ----------------------------------------------------------------------

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.data

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tx_ack: .byte USB_PID_ACK ; ACK packet

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tx_nak: .byte USB_PID_NAK ; NAK packet

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.lcomm token_pid, 1 ; PID of most recent token packet

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; ----------------------------------------------------------------------

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; register definitions

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; ----------------------------------------------------------------------

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// receiver:

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#define count r16

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#define usbmask r17

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#define odd r18

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#define byte r19

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#define fixup r20

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#define even r22

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// transmitter:

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#define output odd

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#define done fixup

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#define next even

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// control:

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#define pid odd

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#define addr usbmask

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#define tmp fixup

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#define nop2 rjmp .+0 // not .+2 for some strange reason

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; ----------------------------------------------------------------------

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; interrupt handler

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; ----------------------------------------------------------------------

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.text

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.global USB_INT_VECTOR

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.type USB_INT_VECTOR, @function

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; ----------------------------------------------------------------------

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; This handler must be reached no later than 34 cycles after D+ goes high

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; for the first time.

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; ----------------------------------------------------------------------

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USB_INT_VECTOR:

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; save registers

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push count

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push usbmask

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push odd

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push YH

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push YL

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in count, SREG

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push count

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; ----------------------------------------------------------------------

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; Synchronize to the pattern 10101011 on D+. This code must be reached

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; no later than 47 cycles after D+ goes high for the first time.

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; ----------------------------------------------------------------------

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sync:

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; wait until D+ == 0

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sbic USB_IN, USBTINY_DPLUS

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rjmp sync ; jump if D+ == 1

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resync:

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; sync on 0-->1 transition on D+ with a 2 cycle resolution

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sbic USB_IN, USBTINY_DPLUS

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