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/** |
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* \brief Internal defs for tpi |
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* \file tpi_defs.h |
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* \author S³awomir Fra |
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*/ |
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#ifndef __TPI_DEFS_H__ |
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#define __TPI_DEFS_H__ |
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/* TPI instructions */ |
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#define TPI_OP_SLD 0x20 |
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#define TPI_OP_SLD_INC 0x24 |
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#define TPI_OP_SST 0x60 |
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#define TPI_OP_SST_INC 0x64 |
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#define TPI_OP_SSTPR(a) (0x68 | (a)) |
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#define TPI_OP_SIN(a) (0x10 | (((a)<<1)&0x60) | ((a)&0x0F) ) |
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#define TPI_OP_SOUT(a) (0x90 | (((a)<<1)&0x60) | ((a)&0x0F) ) |
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#define TPI_OP_SLDCS(a) (0x80 | ((a)&0x0F) ) |
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#define TPI_OP_SSTCS(a) (0xC0 | ((a)&0x0F) ) |
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#define TPI_OP_SKEY 0xE0 |
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/* TPI control/status registers */ |
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#define TPIIR 0xF |
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#define TPIPCR 0x2 |
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#define TPISR 0x0 |
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// TPIPCR bits |
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#define TPIPCR_GT_2 0x04 |
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#define TPIPCR_GT_1 0x02 |
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#define TPIPCR_GT_0 0x01 |
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#define TPIPCR_GT_128b 0x00 |
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#define TPIPCR_GT_64b 0x01 |
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#define TPIPCR_GT_32b 0x02 |
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#define TPIPCR_GT_16b 0x03 |
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#define TPIPCR_GT_8b 0x04 |
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#define TPIPCR_GT_4b 0x05 |
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#define TPIPCR_GT_2b 0x06 |
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#define TPIPCR_GT_0b 0x07 |
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// TPISR bits |
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#define TPISR_NVMEN 0x02 |
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/* NVM registers */ |
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#define NVMCSR 0x32 |
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#define NVMCMD 0x33 |
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// NVMCSR bits |
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#define NVMCSR_BSY 0x80 |
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// NVMCMD values |
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#define NVMCMD_NOP 0x00 |
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#define NVMCMD_CHIP_ERASE 0x10 |
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#define NVMCMD_SECTION_ERASE 0x14 |
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#define NVMCMD_WORD_WRITE 0x1D |
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#endif /*__TPI_DEFS_H__*/ |