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<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
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<header> |
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<!-- ISE source project file created by Project Navigator. --> |
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<!-- --> |
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<!-- This file contains project source information including a list of --> |
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<!-- project source files, project and process properties. This file, --> |
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<!-- along with the project source files, is sufficient to open and --> |
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<!-- implement in ISE Project Navigator. --> |
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<!-- --> |
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<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
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</header> |
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<version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/> |
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<files> |
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<file xil_pn:name="src/PulseGen.vhd" xil_pn:type="FILE_VHDL"> |
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
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</file> |
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<file xil_pn:name="src/S3AN01B.ucf" xil_pn:type="FILE_UCF"> |
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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</file> |
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<file xil_pn:name="src/LIB/PS2.vhd" xil_pn:type="FILE_VHDL"> |
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
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</file> |
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</files> |
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<properties> |
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<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
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<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
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<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/> |
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<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
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<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
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<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/> |
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<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/> |
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<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
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<property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/> |
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<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
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<property xil_pn:name="Device" xil_pn:value="xc3s50an" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/> |
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<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
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<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
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<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/> |
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97 |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
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98 |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
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99 |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
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100 |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
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<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
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103 |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
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<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
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105 |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
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<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/> |
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107 |
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/> |
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108 |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
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109 |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
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110 |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
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111 |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
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112 |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
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113 |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
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114 |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
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115 |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/> |
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116 |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
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117 |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
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118 |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
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119 |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
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120 |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
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121 |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
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122 |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
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123 |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
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124 |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
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125 |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
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126 |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
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127 |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
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128 |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
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129 |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
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130 |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
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131 |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
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132 |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|PulseGen|PulseGen_a" xil_pn:valueState="non-default"/> |
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133 |
<property xil_pn:name="Implementation Top File" xil_pn:value="src/PulseGen.vhd" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PulseGen" xil_pn:valueState="non-default"/> |
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<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
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<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
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137 |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
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138 |
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
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<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
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140 |
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
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141 |
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
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142 |
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
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143 |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
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<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
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145 |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
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146 |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
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147 |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
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148 |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
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149 |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
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150 |
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
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151 |
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
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152 |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
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153 |
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
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154 |
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
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155 |
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
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156 |
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/> |
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157 |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
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158 |
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/> |
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159 |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
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160 |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
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161 |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
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162 |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
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163 |
<property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/> |
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164 |
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
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165 |
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/> |
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166 |
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
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167 |
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
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168 |
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
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169 |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
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170 |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
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171 |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/> |
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172 |
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
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173 |
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
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174 |
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
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175 |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
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176 |
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/> |
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177 |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
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178 |
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
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179 |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
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180 |
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/> |
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181 |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
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182 |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
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183 |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
184 |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
185 |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
186 |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
187 |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
188 |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
189 |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
190 |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
191 |
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
192 |
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
193 |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
194 |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
195 |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
196 |
<property xil_pn:name="Output File Name" xil_pn:value="PulseGen" xil_pn:valueState="default"/> |
|
|
197 |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
198 |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
|
199 |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
|
|
200 |
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/> |
|
|
201 |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
202 |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
203 |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
204 |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
|
|
205 |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
|
|
206 |
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
207 |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
|
|
208 |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
|
|
209 |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PulseGen_map.vhd" xil_pn:valueState="default"/> |
|
|
210 |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="PulseGen_timesim.vhd" xil_pn:valueState="default"/> |
|
|
211 |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PulseGen_synthesis.vhd" xil_pn:valueState="default"/> |
|
|
212 |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PulseGen_translate.vhd" xil_pn:valueState="default"/> |
|
|
213 |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
214 |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
215 |
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
|
|
216 |
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
|
217 |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
218 |
<property xil_pn:name="Project Description" xil_pn:value="Pulse Generator from 10ns to 2us." xil_pn:valueState="non-default"/> |
| 2533 |
kakl |
219 |
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/> |
| 2528 |
kakl |
220 |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
|
|
221 |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
222 |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
|
223 |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
224 |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
|
|
225 |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
226 |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
|
|
227 |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
|
|
228 |
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> |
|
|
229 |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
230 |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
|
|
231 |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
|
|
232 |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
|
|
233 |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="PulseGen" xil_pn:valueState="default"/> |
|
|
234 |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
235 |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
236 |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
237 |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
|
|
238 |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
|
|
239 |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
|
|
240 |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
|
|
241 |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
242 |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
243 |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
|
|
244 |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
245 |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
246 |
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
247 |
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
|
|
248 |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
249 |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
250 |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
251 |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
252 |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
253 |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
|
|
254 |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
|
|
255 |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
256 |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
257 |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
258 |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
259 |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
|
|
260 |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
261 |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
262 |
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
|
|
263 |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
|
|
264 |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
|
|
265 |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
|
|
266 |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
|
|
267 |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
|
|
268 |
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
269 |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
|
|
270 |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
271 |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> |
|
|
272 |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
|
|
273 |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
|
|
274 |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
|
|
275 |
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/> |
|
|
276 |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> |
|
|
277 |
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
|
|
278 |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
|
|
279 |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
|
|
280 |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
|
|
281 |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
|
|
282 |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
283 |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
|
|
284 |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
285 |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
|
|
286 |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
|
|
287 |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
288 |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
|
289 |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
290 |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
291 |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
292 |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
293 |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
294 |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
295 |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
296 |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
297 |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
298 |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
299 |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
300 |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
301 |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
302 |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
|
303 |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
304 |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
|
305 |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> |
|
|
306 |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
307 |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/13.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/> |
|
|
308 |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
|
|
309 |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/> |
|
|
310 |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
311 |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
312 |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
313 |
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
|
|
314 |
<property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
|
|
315 |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
|
|
316 |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
|
|
317 |
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
|
|
318 |
<!-- --> |
|
|
319 |
<!-- The following properties are for internal use only. These should not be modified.--> |
|
|
320 |
<!-- --> |
|
|
321 |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
322 |
<property xil_pn:name="PROP_DesignName" xil_pn:value="PulseGen" xil_pn:valueState="non-default"/> |
|
|
323 |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> |
|
|
324 |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
|
|
325 |
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
326 |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
327 |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
328 |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
329 |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
|
|
330 |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
|
|
331 |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-08-28T23:51:54" xil_pn:valueState="non-default"/> |
|
|
332 |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AAC6D7E01D414DD992A4DDE7C0B857EB" xil_pn:valueState="non-default"/> |
|
|
333 |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
|
|
334 |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
|
|
335 |
</properties> |
|
|
336 |
|
|
|
337 |
<bindings/> |
|
|
338 |
|
|
|
339 |
<libraries/> |
|
|
340 |
|
|
|
341 |
<autoManagedFiles> |
|
|
342 |
<!-- The following files are identified by `include statements in verilog --> |
|
|
343 |
<!-- source files and are automatically managed by Project Navigator. --> |
|
|
344 |
<!-- --> |
|
|
345 |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
|
|
346 |
<!-- project is analyzed based on files automatically identified as --> |
|
|
347 |
<!-- include files. --> |
|
|
348 |
</autoManagedFiles> |
|
|
349 |
|
|
|
350 |
</project> |