Rev Author Line No. Line
2528 kakl 1 ----------------------------------------------------------------------------------
2 -- Company: www.mlab.cz
3 -- Engineer: miho, kakl
4 --
5 -- Create Date: 29/08/2011
6 -- Design Name: S3AN01A Test Design
7 -- Module Name: PulseGen
8 -- Project Name: PulseGen
9 -- Target Devices: XC3S50AN-4
10 -- Tool versions: ISE 13.3
11 -- Description: Sample of Pulse Generator at S3AN01A MLAB board.
12 --
13 -- Dependencies: External PS/2 Keyboard has to be connected.
14 --
15 -- Revision: 1.00 File Created
16 --
17 ----------------------------------------------------------------------------------
18  
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.numeric_std.ALL;
22 use WORK.PS2_pkg.ALL;
23  
24 library UNISIM;
25 use UNISIM.vcomponents.all;
26  
27 entity PulseGen is
28 generic (
29 -- Top Value for 100MHz Clock Counter
30 MAXCOUNT: integer := 30_000_000;
31 MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider
32 );
33 port (
34 -- Main Clock
35 CLK100MHz: in std_logic;
36  
37 -- Mode Signals (usualy not used)
38 M: in std_logic_vector(2 downto 0);
39 VS: in std_logic_vector(2 downto 0);
40  
41 -- Dipswitch Inputs
42 DIPSW: in std_logic_vector(7 downto 0);
43  
44 -- Push Buttons
45 PB: in std_logic_vector(3 downto 0);
46  
47 -- LED Bar Outputs
48 LED: out std_logic_vector(7 downto 0);
49  
50 -- LED Display (8 digit with 7 segments and ddecimal point)
51 LD_A_n: out std_logic;
52 LD_B_n: out std_logic;
53 LD_C_n: out std_logic;
54 LD_D_n: out std_logic;
55 LD_E_n: out std_logic;
56 LD_F_n: out std_logic;
57 LD_G_n: out std_logic;
58 LD_DP_n: out std_logic;
59 LD_0_n: out std_logic;
60 LD_1_n: out std_logic;
61 LD_2_n: out std_logic;
62 LD_3_n: out std_logic;
63 LD_4_n: out std_logic;
64 LD_5_n: out std_logic;
65 LD_6_n: out std_logic;
66 LD_7_n: out std_logic;
67  
68 -- VGA Video Out Port
69 VGA_R: out std_logic_vector(1 downto 0);
70 VGA_G: out std_logic_vector(1 downto 0);
71 VGA_B: out std_logic_vector(1 downto 0);
72 VGA_VS: out std_logic;
73 VGA_HS: out std_logic;
74  
75 -- Bank 1 Pins - Inputs for this Test
76 B: inout std_logic_vector(24 downto 0);
77  
78 -- PS/2 Bidirectional Port (open collector, J31 and J32)
79 -- PS2_CLK1: inout std_logic;
80 -- PS2_DATA1: inout std_logic;
81 PS2_CLK2: inout std_logic;
82 PS2_DATA2: inout std_logic;
83  
84 -- Diferencial Signals on 4 pin header (J7)
85 DIF1P: inout std_logic;
86 DIF1N: inout std_logic;
87 DIF2P: inout std_logic;
88 DIF2N: inout std_logic;
89  
90  
91 -- I2C Signals (on connector J30)
92 I2C_SCL: inout std_logic;
93 I2C_SDA: inout std_logic;
94  
95 -- Diferencial Signals on SATA like connectors (not SATA capable, J28 and J29)
96 SD1AP: inout std_logic;
97 SD1AN: inout std_logic;
98 SD1BP: inout std_logic;
99 SD1BN: inout std_logic;
100 SD2AP: inout std_logic;
101 SD2AN: inout std_logic;
102 SD2BP: inout std_logic;
103 SD2BN: inout std_logic;
104  
105 -- Analog In Out
106 ANA_OUTD: out std_logic;
107 ANA_REFD: out std_logic;
108 ANA_IND: in std_logic;
109  
110 -- SPI Memory Interface
111 SPI_CS_n: inout std_logic;
112 SPI_DO: inout std_logic;
113 SPI_DI: inout std_logic;
114 SPI_CLK: inout std_logic;
115 SPI_WP_n: inout std_logic
116 );
117 end entity PulseGen;
118  
119  
120 architecture PulseGen_a of PulseGen is
121  
122 function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
123 variable i : integer:=0;
124 variable mybcd : std_logic_vector(11 downto 0) := (others => '0');
125 variable bint : std_logic_vector(7 downto 0) := bin;
126 begin
127 for i in 0 to 7 loop -- repeating 8 times.
128 mybcd(11 downto 1) := mybcd(10 downto 0); --shifting the bits.
129 mybcd(0) := bint(7);
130 bint(7 downto 1) := bint(6 downto 0);
131 bint(0) :='0';
132  
133  
134 if(i < 7 and mybcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
135 mybcd(3 downto 0) := std_logic_vector(unsigned(mybcd(3 downto 0)) + 3);
136 end if;
137  
138 if(i < 7 and mybcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
139 mybcd(7 downto 4) := std_logic_vector(unsigned(mybcd(7 downto 4)) + 3);
140 end if;
141  
142 if(i < 7 and mybcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
143 mybcd(11 downto 8) := std_logic_vector(unsigned(mybcd(11 downto 8)) + 3);
144 end if;
145 end loop;
146  
147 return mybcd;
148 end to_bcd;
149  
150  
151 -- O1: ____|^^^^^^^|______
152 -- O2: _________|^^|______
153 -- t1 t2
154 -- t1/t2 is from 0 to 2000 ns; repeating frequency is cca 1,6 kHz
155  
156 signal T1: unsigned(15 downto 0) := X"000a"; -- Time t1 to Impuls at O2
157 signal T2: unsigned(15 downto 0) := X"0001"; -- Duration t2 of impuls at O2
158 signal CT0: unsigned(15 downto 0) := X"0000"; -- Timer
159 signal O1: std_logic := '0'; -- Output 1
160 signal O2: std_logic := '0'; -- Output 2
161  
162 -- LED Demo Signals
163 -- ----------------
164  
165 signal Counter: unsigned(31 downto 0) := X"00000000"; -- Main Counter (binary)
166 signal Bar: unsigned(7 downto 0) := X"00"; -- Counter for Bar output (binary)
167  
168 signal FastBlink: std_logic; -- Signal mask for half intensity LED output (several kHz)
169  
170 -- LED Display
171 -- -----------
172  
173 signal Number: std_logic_vector(32 downto 0); -- LED Display Input
174 signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider
175 signal Enable: std_logic;
176 signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output
177 signal Segments: std_logic_vector(0 to 7); -- LED Segment Output
178 signal Code: std_logic_vector(3 downto 0); -- BCD to 7 Segment Decoder Output
179  
180 -- PS/2 Port
181 -- ---------
182  
183 -- Interface Signals
184 signal PS2_Code: std_logic_vector(7 downto 0); -- Key Scan Code
185 signal PS2_Attribs: std_logic_vector(7 downto 0); -- State of Shifts for Scan Code
186 signal PS2_Valid: boolean; -- Valid Data (synchronous with Main Clock)
187 signal PS2_Shifts: std_logic_vector(9 downto 0); -- Immediate (life) State of Shifts for Scan Code
188  
189 -- Result
190 signal PS2_Result: std_logic_vector(15 downto 0); -- Result (memory)
191  
192 -- signal Key: std_logic_vector(7 downto 0); -- Cislo na klavese
193  
194 -- VGA Demo Signals
195 -- ----------------
196  
197 signal CLK: std_logic; -- Main Clock - global distribution network
198 signal CLKVGAi: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - internal connection from DCM to BUFG
199 signal CLKVGA: std_logic; -- DCM Clock Out (40MHz Pixel Clock) - global distribution network
200 signal VGA_Blank: boolean; -- Blank
201 signal VGA_Hsync: boolean; -- Horisontal Synchronisation
202 signal VGA_Vsync: boolean; -- Vertical Synchronisation
203  
204 signal VCounter: unsigned(9 downto 0) := "0000000000"; -- Vertical Counter
205 signal HCounter: unsigned(10 downto 0) := "00000000000"; -- Horisontal Counter
206  
207 signal PinState: std_logic; -- For IB1 Port Test
208 signal Red: std_logic_vector(1 downto 0);
209 signal Green: std_logic_vector(1 downto 0);
210 signal Blue: std_logic_vector(1 downto 0);
211  
212 -- ADDA
213 signal ADDA_DataIn: std_logic_vector(7 downto 0);
214  
215 begin
216  
217 -- Basic LED Blinking Test
218 -- =======================
219  
220 -- LED Bar Counter
221 process (CLK100MHz)
222 begin
223 if rising_edge(CLK100MHz) then
224 if Counter < MAXCOUNT-1 then
225 Counter <= Counter + 1;
226 else
227 Counter <= (others => '0');
228 Bar <= Bar + 1;
229 end if;
230 end if;
231 end process;
232  
233 LED <= std_logic_vector(Bar); -- LED Bar Connected to Counter
234  
235 FastBlink <= Counter(13) and Counter(14) and Counter(15) and Counter(16); -- 1/16 intensity
236  
237 -- LED Display (multiplexed)
238 -- =========================
239  
240 -- Connect LED Display Output Ports (negative outputs)
241 LD_A_n <= not (Segments(0) and Enable);
242 LD_B_n <= not (Segments(1) and Enable);
243 LD_C_n <= not (Segments(2) and Enable);
244 LD_D_n <= not (Segments(3) and Enable);
245 LD_E_n <= not (Segments(4) and Enable);
246 LD_F_n <= not (Segments(5) and Enable);
247 LD_G_n <= not (Segments(6) and Enable);
248 LD_DP_n <= not (Segments(7) and Enable);
249  
250 LD_0_n <= not Digits(0);
251 LD_1_n <= not Digits(1);
252 LD_2_n <= not Digits(2);
253 LD_3_n <= not Digits(3);
254 LD_4_n <= not Digits(4);
255 LD_5_n <= not Digits(5);
256 LD_6_n <= not Digits(6);
257 LD_7_n <= not Digits(7);
258  
259 -- Time Multiplex
260 process (CLK100MHz)
261 begin
262 if rising_edge(CLK100MHz) then
263 if MuxCounter < MUXCOUNT-1 then
264 MuxCounter <= MuxCounter + 1;
265 else
266 MuxCounter <= (others => '0');
267 Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left
268 Enable <= '0';
269 end if;
270 if MuxCounter > (MUXCOUNT-4) then
271 Enable <= '1';
272 end if;
273 end if;
274 end process;
275  
276 -- BCD to 7 Segmet Decoder
277 -- -- A
278 -- | | F B
279 -- -- G
280 -- | | E C
281 -- -- D H
282 -- ABCDEFGH
283 Segments <= "11111100" when Code="0000" else -- Digit 0
284 "01100000" when Code="0001" else -- Digit 1
285 "11011010" when Code="0010" else -- Digit 2
286 "11110010" when Code="0011" else -- Digit 3
287 "01100110" when Code="0100" else -- Digit 4
288 "10110110" when Code="0101" else -- Digit 5
289 "10111110" when Code="0110" else -- Digit 6
290 "11100000" when Code="0111" else -- Digit 7
291 "11111110" when Code="1000" else -- Digit 8
292 "11110110" when Code="1001" else -- Digit 9
293 "11101110" when Code="1010" else -- Digit A
294 "00111110" when Code="1011" else -- Digit b
295 "10011100" when Code="1100" else -- Digit C
296 "01111010" when Code="1101" else -- Digit d
297 "10011110" when Code="1110" else -- Digit E
298 "10001110" when Code="1111" else -- Digit F
299 "00000000";
300  
301 Code <= Number( 3 downto 0) when Digits="00000001" else
302 Number( 7 downto 4) when Digits="00000010" else
303 Number(11 downto 8) when Digits="00000100" else
304 Number(15 downto 12) when Digits="00001000" else
305 Number(19 downto 16) when Digits="00010000" else
306 Number(23 downto 20) when Digits="00100000" else
307 Number(27 downto 24) when Digits="01000000" else
308 Number(31 downto 28) when Digits="10000000" else
309 "0000";
310  
311 -- Key <= "00000000" when PS2_Result(7 downto 0)=X"70" else -- Digit 0
312 -- "00000001" when PS2_Result(7 downto 0)=X"69" else -- Digit 1
313 -- "00000010" when PS2_Result(7 downto 0)=X"72" else -- Digit 2
314 -- "11111111";
315  
316 -- Number(31 downto 28) <= Key(3 downto 0);
317  
318 -- Number( 7 downto 0) <= std_logic_vector(BAR);
319 -- Number(31 downto 24) <= DIPSW;
320  
321 -- PS/2 Port
322 -- =========
323  
324 -- Instantiate PS/2 Keyboard Interface Handler
325 PS2_Keyboard: PS2 generic map(
326 CLKFREQ => 100_000_000
327 )
328 port map(
329 -- Main Clock
330 Clk => CLK100MHz,
331  
332 -- PS/2 Port
333 PS2_Clk => PS2_CLK2,
334 PS2_Data => PS2_DATA2,
335  
336 -- Result - valid when PS2_Valid
337 PS2_Code => PS2_Code,
338 PS2_Attribs => PS2_Attribs,
339 PS2_Valid => PS2_Valid,
340  
341 -- Immediate State of Shifts
342 PS2_Shifts => PS2_Shifts
343 ); -- PS2
344  
345 process (CLK100MHz)
346 begin
347 if rising_edge(CLK100MHz) then
348 if PS2_Valid and PS2_Attribs(7)='0' then
349 -- Valid Scan Code with no Break Attribute
350 PS2_Result( 7 downto 0) <= PS2_Code;
351 PS2_Result(15 downto 8) <= PS2_Attribs;
352 end if;
353  
354 if PS2_Valid and PS2_Attribs(7)='0' then
355 if PS2_Code = X"74" and T1<200 then T1<=T1+1; end if;
356 if PS2_Code = X"6b" and T1>0 then T1<=T1-1; end if;
357 if PS2_Code = X"75" and T2<200 then T2<=T2+1; end if;
358 if PS2_Code = X"72" and T2>0 then T2<=T2-1; end if;
359 CT0<=X"0000";
360 O1<='0';
361 O2<='0';
362 end if;
363  
364 if CT0=X"F000" then
365 CT0<=X"0000";
366 else
367 CT0<=CT0+1;
368 end if;
369  
370 if CT0=X"0000" then
371 O1<='1';
372 end if;
373  
374 if CT0=T1 then
375 O2<='1';
376 end if;
377  
378 if CT0=(T2+T1) then
379 O1<='0';
380 O2<='0';
381 end if;
382  
383 end if;
384  
385 end process;
386  
387 -- Display Result on LED
388 Number(3 downto 0) <= (others=>'0');
389 Number(15 downto 4) <= to_bcd(std_logic_vector(T2));
390 Number(19 downto 16) <= (others=>'0');
391 Number(31 downto 20) <= to_bcd(std_logic_vector(T1));
392  
393  
394 -- Test Diferencial In/Outs
395 -- ========================
396  
397 -- Output Signal on SATA Connector
398 SD1AP <= Bar(0);
399 SD1AN <= Bar(1);
400 SD1BP <= Bar(2);
401 SD1BN <= Bar(3);
402  
403 -- Input Here via SATA Cable
404 SD2AP <= 'Z';
405 SD2AN <= 'Z';
406 SD2BP <= 'Z';
407 SD2BN <= 'Z';
408  
409 -- Copy SATA Connector Input to 4 pin header (J7) - Connect these signals to B port input to visualize them
410 -- !!!!!!!!!!!! Pulse Generator Outputs !!!!!!!!!!!!!!!!!!!!!
411 DIF1P <= O1;
412 B(0) <= O1;
413 DIF1N <= not O1;
414 B(1) <= not O1;
415 DIF2P <= O2;
416 B(2) <= O2;
417 DIF2N <= not O2;
418 B(3) <= not O2;
419  
420 -- Unused Signals
421 -- ==============
422  
423 -- I2C Signals (on connector J30)
424 I2C_SCL <= 'Z';
425 I2C_SDA <= 'Z';
426  
427 -- SPI Memory Interface
428 SPI_CS_n <= 'Z';
429 SPI_DO <= 'Z';
430 SPI_DI <= 'Z';
431 SPI_CLK <= 'Z';
432 SPI_WP_n <= 'Z';
433  
434 ANA_OUTD <= 'Z';
435 ANA_REFD <= 'Z';
436  
437 VGA_R <= "ZZ";
438 VGA_G <= "ZZ";
439 VGA_B <= "ZZ";
440 VGA_VS <= 'Z';
441 VGA_HS <= 'Z';
442  
443 end architecture PulseGen_a;