Rev Author Line No. Line
3091 miho 1 ##############################################################
2 #
3 # Xilinx Core Generator version 14.5
4 # Date: Thu Jun 20 13:35:12 2013
5 #
6 ##############################################################
7 #
8 # This file contains the customisation parameters for a
9 # Xilinx CORE Generator IP GUI. It is strongly recommended
10 # that you do not manually alter this file as it may cause
11 # unexpected and unsupported behavior.
12 #
13 ##############################################################
14 #
15 # Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
16 #
17 ##############################################################
18 #
19 # BEGIN Project Options
20 SET addpads = false
21 SET asysymbol = true
22 SET busformat = BusFormatAngleBracketNotRipped
23 SET createndf = false
24 SET designentry = VHDL
25 SET device = xc3s50an
26 SET devicefamily = spartan3a
27 SET flowvendor = Other
28 SET formalverification = false
29 SET foundationsym = false
30 SET implementationfiletype = Ngc
31 SET package = tqg144
32 SET removerpms = false
33 SET simulationfiles = Behavioral
34 SET speedgrade = -4
35 SET verilogsim = false
36 SET vhdlsim = true
37 # END Project Options
38 # BEGIN Select
39 SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
40 # END Select
41 # BEGIN Parameters
42 CSET check_bramcount=false
43 CSET component_name=ChipScope_ILA_9_2048
44 CSET constraint_type=external
45 CSET counter_width_1=4
46 CSET counter_width_10=Disabled
47 CSET counter_width_11=Disabled
48 CSET counter_width_12=Disabled
49 CSET counter_width_13=Disabled
50 CSET counter_width_14=Disabled
51 CSET counter_width_15=Disabled
52 CSET counter_width_16=Disabled
53 CSET counter_width_2=Disabled
54 CSET counter_width_3=Disabled
55 CSET counter_width_4=Disabled
56 CSET counter_width_5=Disabled
57 CSET counter_width_6=Disabled
58 CSET counter_width_7=Disabled
59 CSET counter_width_8=Disabled
60 CSET counter_width_9=Disabled
61 CSET data_port_width=9
62 CSET data_same_as_trigger=false
63 CSET disable_save_keep=false
64 CSET enable_storage_qualification=true
65 CSET enable_trigger_output_port=true
66 CSET example_design=false
67 CSET exclude_from_data_storage_1=true
68 CSET exclude_from_data_storage_10=true
69 CSET exclude_from_data_storage_11=true
70 CSET exclude_from_data_storage_12=true
71 CSET exclude_from_data_storage_13=true
72 CSET exclude_from_data_storage_14=true
73 CSET exclude_from_data_storage_15=true
74 CSET exclude_from_data_storage_16=true
75 CSET exclude_from_data_storage_2=true
76 CSET exclude_from_data_storage_3=true
77 CSET exclude_from_data_storage_4=true
78 CSET exclude_from_data_storage_5=true
79 CSET exclude_from_data_storage_6=true
80 CSET exclude_from_data_storage_7=true
81 CSET exclude_from_data_storage_8=true
82 CSET exclude_from_data_storage_9=true
83 CSET match_type_1=basic_with_edges
84 CSET match_type_10=basic_with_edges
85 CSET match_type_11=basic_with_edges
86 CSET match_type_12=basic_with_edges
87 CSET match_type_13=basic_with_edges
88 CSET match_type_14=basic_with_edges
89 CSET match_type_15=basic_with_edges
90 CSET match_type_16=basic_with_edges
91 CSET match_type_2=basic_with_edges
92 CSET match_type_3=basic_with_edges
93 CSET match_type_4=basic_with_edges
94 CSET match_type_5=basic_with_edges
95 CSET match_type_6=basic_with_edges
96 CSET match_type_7=basic_with_edges
97 CSET match_type_8=basic_with_edges
98 CSET match_type_9=basic_with_edges
99 CSET match_units_1=3
100 CSET match_units_10=1
101 CSET match_units_11=1
102 CSET match_units_12=1
103 CSET match_units_13=1
104 CSET match_units_14=1
105 CSET match_units_15=1
106 CSET match_units_16=1
107 CSET match_units_2=1
108 CSET match_units_3=1
109 CSET match_units_4=1
110 CSET match_units_5=1
111 CSET match_units_6=1
112 CSET match_units_7=1
113 CSET match_units_8=1
114 CSET match_units_9=1
115 CSET max_sequence_levels=16
116 CSET number_of_trigger_ports=1
117 CSET sample_data_depth=2048
118 CSET sample_on=Rising
119 CSET trigger_port_width_1=24
120 CSET trigger_port_width_10=8
121 CSET trigger_port_width_11=8
122 CSET trigger_port_width_12=8
123 CSET trigger_port_width_13=8
124 CSET trigger_port_width_14=8
125 CSET trigger_port_width_15=8
126 CSET trigger_port_width_16=8
127 CSET trigger_port_width_2=8
128 CSET trigger_port_width_3=8
129 CSET trigger_port_width_4=8
130 CSET trigger_port_width_5=8
131 CSET trigger_port_width_6=8
132 CSET trigger_port_width_7=8
133 CSET trigger_port_width_8=8
134 CSET trigger_port_width_9=8
135 CSET use_rpms=true
136 # END Parameters
137 # BEGIN Extra information
138 MISC pkg_timestamp=2013-03-26T22:44:34Z
139 # END Extra information
140 GENERATE
141 # CRC: 100acb04