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# |
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# Xilinx Core Generator version 14.5 |
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# Date: Thu Jun 20 12:56:15 2013 |
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# |
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############################################################## |
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# |
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# This file contains the customisation parameters for a |
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# Xilinx CORE Generator IP GUI. It is strongly recommended |
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# that you do not manually alter this file as it may cause |
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# unexpected and unsupported behavior. |
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# |
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############################################################## |
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# |
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# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a |
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# |
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############################################################## |
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# |
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# BEGIN Project Options |
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SET addpads = false |
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SET asysymbol = true |
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SET busformat = BusFormatAngleBracketNotRipped |
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SET createndf = false |
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SET designentry = VHDL |
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SET device = xc3s50an |
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SET devicefamily = spartan3a |
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SET flowvendor = Other |
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SET formalverification = false |
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SET foundationsym = false |
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SET implementationfiletype = Ngc |
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SET package = tqg144 |
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SET removerpms = false |
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SET simulationfiles = Behavioral |
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SET speedgrade = -4 |
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SET verilogsim = false |
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SET vhdlsim = true |
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# END Project Options |
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# BEGIN Select |
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SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a |
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# END Select |
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# BEGIN Parameters |
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CSET asynchronous_input_port_width=8 |
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CSET asynchronous_output_port_width=8 |
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CSET component_name=ChipScope_VIO_FreqSel |
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CSET constraint_type=external |
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CSET enable_asynchronous_input_port=false |
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CSET enable_asynchronous_output_port=false |
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CSET enable_synchronous_input_port=true |
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CSET enable_synchronous_output_port=true |
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CSET example_design=false |
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CSET invert_clock_input=false |
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CSET synchronous_input_port_width=8 |
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CSET synchronous_output_port_width=8 |
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# END Parameters |
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# BEGIN Extra information |
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MISC pkg_timestamp=2013-03-26T22:44:59Z |
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# END Extra information |
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GENERATE |
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# CRC: c6d481e1 |