Rev Author Line No. Line
3091 miho 1 ##############################################################
2 #
3 # Xilinx Core Generator version 14.5
4 # Date: Thu Jun 20 12:55:33 2013
5 #
6 ##############################################################
7 #
8 # This file contains the customisation parameters for a
9 # Xilinx CORE Generator IP GUI. It is strongly recommended
10 # that you do not manually alter this file as it may cause
11 # unexpected and unsupported behavior.
12 #
13 ##############################################################
14 #
15 # Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
16 #
17 ##############################################################
18 #
19 # BEGIN Project Options
20 SET addpads = false
21 SET asysymbol = true
22 SET busformat = BusFormatAngleBracketNotRipped
23 SET createndf = false
24 SET designentry = VHDL
25 SET device = xc3s50an
26 SET devicefamily = spartan3a
27 SET flowvendor = Other
28 SET formalverification = false
29 SET foundationsym = false
30 SET implementationfiletype = Ngc
31 SET package = tqg144
32 SET removerpms = false
33 SET simulationfiles = Behavioral
34 SET speedgrade = -4
35 SET verilogsim = false
36 SET vhdlsim = true
37 # END Project Options
38 # BEGIN Select
39 SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
40 # END Select
41 # BEGIN Parameters
42 CSET asynchronous_input_port_width=8
43 CSET asynchronous_output_port_width=8
44 CSET component_name=ChipScope_VIO_UserOut
45 CSET constraint_type=external
46 CSET enable_asynchronous_input_port=false
47 CSET enable_asynchronous_output_port=false
48 CSET enable_synchronous_input_port=false
49 CSET enable_synchronous_output_port=true
50 CSET example_design=false
51 CSET invert_clock_input=false
52 CSET synchronous_input_port_width=8
53 CSET synchronous_output_port_width=3
54 # END Parameters
55 # BEGIN Extra information
56 MISC pkg_timestamp=2013-03-26T22:44:59Z
57 # END Extra information
58 GENERATE
59 # CRC: 738ddf25