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# Board: www.mlab.cz S3AN01A |
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# Device: XC3S50AN-4TQG144C |
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# Setting: Generate Programming File / Startup Options / Drive Done Pin High: yes |
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# Main Clock (Embedded 100MHz board oscillator) |
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NET "CLK100MHz" LOC = P60 |IOSTANDARD = LVCMOS33; |
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NET "CLK100MHz" TNM_NET = CLK100MHz; |
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TIMESPEC TS_CLK100MHz = PERIOD "CLK100MHz" 100 MHz HIGH 50%; |
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# Enable suboptimal routing of CLK100MHz to DCM input |
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# (the CLK100MHz pin is across the whole chip realtive to DCM) |
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# PIN "DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; |
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# Place BUFGMUX at the appropriate position |
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NET "CLK100MHz" CLOCK_DEDICATED_ROUTE = FALSE; |
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# SPI Flash Vendor Mode Select (for external SPI boot Flash) |
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NET "VS[0]" LOC = P45 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "VS[1]" LOC = P44 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "VS[2]" LOC = P43 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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# DIP Switches (positive signals with pull-down) |
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NET "DIPSW[0]" LOC = P143 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[1]" LOC = P142 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[2]" LOC = P140 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[3]" LOC = P139 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[4]" LOC = P138 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[5]" LOC = P135 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[6]" LOC = P134 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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NET "DIPSW[7]" LOC = P132 |IOSTANDARD = LVCMOS33 |PULLDOWN = YES; |
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# LED String (positive output signals) |
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NET "LED[0]" LOC = P64 |IOSTANDARD = LVCMOS33; |
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NET "LED[1]" LOC = P63 |IOSTANDARD = LVCMOS33; |
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NET "LED[2]" LOC = P51 |IOSTANDARD = LVCMOS33; |
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NET "LED[3]" LOC = P50 |IOSTANDARD = LVCMOS33; |
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NET "LED[4]" LOC = P49 |IOSTANDARD = LVCMOS33; |
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NET "LED[5]" LOC = P48 |IOSTANDARD = LVCMOS33; |
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NET "LED[6]" LOC = P47 |IOSTANDARD = LVCMOS33; |
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NET "LED[7]" LOC = P46 |IOSTANDARD = LVCMOS33; |
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# LED Display Output Signals (negative, multiplexed) - Segments |
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NET "LD_SEG_n[0]" LOC = P15 |IOSTANDARD = LVCMOS33; # Segment A A |
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NET "LD_SEG_n[1]" LOC = P30 |IOSTANDARD = LVCMOS33; # Segment B ----- |
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NET "LD_SEG_n[2]" LOC = P21 |IOSTANDARD = LVCMOS33; # Segment C F | | B |
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NET "LD_SEG_n[3]" LOC = P19 |IOSTANDARD = LVCMOS33; # Segment D | G | |
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NET "LD_SEG_n[4]" LOC = P18 |IOSTANDARD = LVCMOS33; # Segment E ----- |
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NET "LD_SEG_n[5]" LOC = P16 |IOSTANDARD = LVCMOS33; # Segment F E | | C |
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NET "LD_SEG_n[6]" LOC = P24 |IOSTANDARD = LVCMOS33; # Segment G | D | |
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NET "LD_SEG_n[7]" LOC = P20 |IOSTANDARD = LVCMOS33; # Segment DP ----- DP |
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# LED Display Output Signals (negative, multiplexed) - Common Anodas |
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NET "LD_CA_n[0]" LOC = P25 |IOSTANDARD = LVCMOS33; |
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NET "LD_CA_n[1]" LOC = P31 |IOSTANDARD = LVCMOS33; |
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NET "LD_CA_n[2]" LOC = P32 |IOSTANDARD = LVCMOS33; |
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NET "LD_CA_n[3]" LOC = P13 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.13 with U1.33 |
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NET "LD_CA_n[4]" LOC = P27 |IOSTANDARD = LVCMOS33; |
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NET "LD_CA_n[5]" LOC = P29 |IOSTANDARD = LVCMOS33; |
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NET "LD_CA_n[6]" LOC = P28 |IOSTANDARD = LVCMOS33; |
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NET "LD_CA_n[7]" LOC = P12 |IOSTANDARD = LVCMOS33; # For S3AN01A connect U1.12 with U1.35 |
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# Bank 1 Port (input for tests, pull-up) |
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NET "P[0]" LOC = P75 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[1]" LOC = P76 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[2]" LOC = P77 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[3]" LOC = P78 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[4]" LOC = P82 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[5]" LOC = P83 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[6]" LOC = P84 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[7]" LOC = P85 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[8]" LOC = P87 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[9]" LOC = P88 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[10]" LOC = P90 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[11]" LOC = P91 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[12]" LOC = P92 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[13]" LOC = P93 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[14]" LOC = P96 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[15]" LOC = P98 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[16]" LOC = P99 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[17]" LOC = P101 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[18]" LOC = P102 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[19]" LOC = P103 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[20]" LOC = P104 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[21]" LOC = P105 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[22]" LOC = P79 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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NET "P[23]" LOC = P80 |IOSTANDARD = LVCMOS33 |PULLUP = YES; |
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# Diferencial Signals on 4 pin header (J7) |
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NET "DIF1P" LOC = P110 |IOSTANDARD = LVDS_33; |
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NET "DIF1N" LOC = P111 |IOSTANDARD = LVDS_33; |
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NET "DIF2P" LOC = P112 |IOSTANDARD = LVDS_33; |
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NET "DIF2N" LOC = P113 |IOSTANDARD = LVDS_33; |
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# Timing Constraint for Crossing Time Domain |
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# Source is ChipScope_VIO_FreqSel output in CLK_FAST time domain |
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# Destination is SW_SYNC register in CLK100MHz time domain |
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INST "SW_SYNC_?" TNM = "TNM_SW_SYNC"; |
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TIMESPEC "TS_SW_SYNC" = TO "TNM_SW_SYNC" TIG; |
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# Timing Constraint for Crossing Time Domain |
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# Source is SET_CLK_xxx register (FSM) in CLK100MHz time domain |
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# Destination is ChipScope_VIO_FreqSel inputs in CLK_FAST time domain |
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INST "SYNC_IN_?" TNM = "TNM_SET_CLK"; |
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TIMESPEC "TS_SET_CLK" = TO "TNM_SET_CLK" TIG; |
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# Timing Constraint for Clock Switch |
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# Block BUFGMUX is used as Assynchronous switcher |
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PIN "BUFGMUX_CLK_FAST.S" TIG; |