| 3091 |
miho |
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-- ======================================================================== |
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-- |
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-- S3AN01_ChipScope |
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-- |
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-- Logic Analyser based on Xilinx ChipScope IP Core for S3AN01 Board |
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-- |
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-- (c) miho 2013 / http://www.mlab.cz/PermaLink/XILINX_ChipScope |
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-- |
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-- Demo application contains some Clock Logic (DCM block and |
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-- clock switch to be able to set different sample clocks). |
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-- The main function is ChipScope Logic Analyser with 16 data inputs |
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-- (with 24 bit trigger) and storage for 1024 Data Samples. |
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-- |
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-- Sampling clock is selectable to 170/100/50/20/10/5/2/1MHz |
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-- |
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-- To implement the design the ChipScope license is required. |
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-- |
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-- To use (the logic analyser) no speceial license is needed, |
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-- WebPack ISE or Lab Tools is enough). Requires some compatible |
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-- JTAG cable. Compatible with MLAB Xilinx Virtual Cable as well |
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-- http://www.mlab.cz/PermaLink/XILINX_XVC |
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-- |
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-- Device: Spartan3AN XC3S50AN-4TQG144C |
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-- |
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-- Software: ISE WebPack 14.5 |
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-- |
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-- ======================================================================== |
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-- Standard Library |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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use IEEE.numeric_std.ALL; |
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-- Xilinx Library (necessary for DMC and other Xilinx blocks) |
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library UNISIM; |
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use UNISIM.VComponents.all; |
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-- Interface |
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entity S3AN01_ChipScope is |
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generic( |
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ILA_WIDE: boolean := TRUE; -- TRUE/FALSE -> 18bit x 1024 / 9bit x 2048 logic analyser |
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MUXCOUNT: integer := 100_000 -- LED Display Multiplex Clock Divider |
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); |
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port( |
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-- Main Clock |
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CLK100MHz: in std_logic; -- 100MHz external xtal clock source |
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-- Mode Signals (usualy not used) |
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VS: out std_logic_vector(2 downto 0); -- SPI Flash Vendor Mode Select |
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-- Dipswitch Inputs |
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DIPSW: in std_logic_vector(7 downto 0); |
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-- LED Bar Outputs |
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LED: out std_logic_vector(7 downto 0); |
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-- LED Display (8 digits with 7 segments and decimal point) |
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LD_CA_n: out std_logic_vector(7 downto 0); |
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LD_SEG_n: out std_logic_vector(7 downto 0); |
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-- Bank 1 Pins Inputs |
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P: in std_logic_vector(24 downto 0); |
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-- Diferencial Signals on 4 pin header (J7) |
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DIF1P: inout std_logic; |
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DIF1N: inout std_logic; |
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DIF2P: inout std_logic; |
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DIF2N: inout std_logic |
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); |
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end S3AN01_ChipScope; |
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-- Implementation |
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architecture S3AN01_ChipScope_a of S3AN01_ChipScope is |
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-- Clock Signals |
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-- ============= |
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-- DCM Signals |
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signal DCM_CLK0: std_logic; -- DCM output for feedback |
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signal DCM_CLKFX: std_logic; -- DCM output of the fastest clock |
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signal CLK_FAST: std_logic; -- Main clock for ILA |
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signal CLK_FAST_Q: std_logic; -- Auxiliary signal (for CLK_FAST sent to pin) |
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-- 100MHz Clock Switch |
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-- CLK100MHz Clock Domain |
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signal CLK100MHz_CE: std_logic; -- Gate Signal for slow dwn of the 100MHz clock |
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signal CLK100MHz_Gated: std_logic; -- Gated Clocks |
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signal CLK100MHz_CE_Cnt: unsigned(6 downto 0) := (others => '0'); -- Gate Signal Counter (min frequency is 1/100 of CLK100MHz |
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-- 1 Hot Clock Select Signals |
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-- CLK100MHz Clock Domain |
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signal SET_CLK_MAX: std_logic := '0'; -- Clock Select Signal - Maximim (150-170Mhz) |
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signal SET_CLK_100MHz: std_logic := '1'; -- Clock Select Signal - 100MHz |
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signal SET_CLK_50MHz: std_logic := '0'; -- Clock Select Signal - 50MHz |
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signal SET_CLK_20Mhz: std_logic := '0'; -- Clock Select Signal - 20MHz |
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signal SET_CLK_10Mhz: std_logic := '0'; -- Clock Select Signal - 10MHz |
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signal SET_CLK_5Mhz: std_logic := '0'; -- Clock Select Signal - 5MHz |
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signal SET_CLK_2Mhz: std_logic := '0'; -- Clock Select Signal - 2MHz |
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signal SET_CLK_1Mhz: std_logic := '0'; -- Clock Select Signal - 1MHz |
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-- Signals from and to ChipScope Virtual IO (set and display frequency) |
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-- CLK_FAST and CLK100MHz time domain |
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signal SYNC_IN: std_logic_vector(7 downto 0); -- Input to ChipScope VIO |
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signal SYNC_OUT: std_logic_vector(7 downto 0); -- Output from ChipScope VIO |
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signal SW_SYNC: std_logic_vector(7 downto 0) := (others => '0'); -- Asyn inputs synced |
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-- LED Ouput with time multiplex |
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-- ============================= |
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signal WideBCD: std_logic_vector(2*5-1 downto 0); -- Constant width of ILA in BCD (2 char wide) |
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signal FrequencyBCD: std_logic_vector(3*5-1 downto 0); -- Selected frequency in BCD (3 char wide) |
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signal Code: std_logic_vector(4 downto 0); -- BCD to 7 Segment Decoder Output |
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signal Segments: std_logic_vector(0 to 7); -- LED Segment Output |
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-- Time Multiplex |
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signal MuxCounter: unsigned(31 downto 0) := (others => '0'); -- LED Multiplex - Multiplex Clock Divider |
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signal LedEnable: std_logic; -- LED Display Brightness |
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signal Digits: std_logic_vector(7 downto 0) := X"01"; -- LED Multiplex - Digit Counter - LED Digit Output |
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-- Test Generator signals |
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-- ====================== |
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signal Counter: std_logic_vector(7 downto 0); -- Counter |
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-- ChipScope Signals |
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-- ================= |
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-- Input data |
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-- CLK_FAST Clock Domain |
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signal DataReg: std_logic_vector(P'range); -- Data and Trigger input |
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-- Trigger Output |
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signal TriggerOut: std_logic; -- Trigegr output from ChipScope ILA to pin |
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-- User Outputs from ChipScope Virtual IO |
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signal SYNC_OUT_USER: std_logic_vector(2 downto 0); -- Output from ChipScope VIO |
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-- ChipScope Control Signals |
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signal Control0: std_logic_vector(35 downto 0); |
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signal Control1: std_logic_vector(35 downto 0); |
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signal Control2: std_logic_vector(35 downto 0); |
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-- ChipScope Control Block |
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component ChipScope_ICON |
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port ( |
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CONTROL0: inout std_logic_vector(35 downto 0); |
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CONTROL1: inout std_logic_vector(35 downto 0); |
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CONTROL2: inout std_logic_vector(35 downto 0) |
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); |
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end component; |
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-- ChipScope Virtual I/O Block |
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component ChipScope_VIO_FreqSel |
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port ( |
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CONTROL: inout std_logic_vector(35 downto 0); |
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CLK: in std_logic; |
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SYNC_IN: in std_logic_vector(7 downto 0); |
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SYNC_OUT: out std_logic_vector(7 downto 0) |
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); |
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end component; |
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-- ChipScope Virtual I/O Block |
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component ChipScope_VIO_UserOut |
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port ( |
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CONTROL: inout std_logic_vector(35 downto 0); |
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CLK: in std_logic; |
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SYNC_OUT: out std_logic_vector(2 downto 0) |
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); |
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end component; |
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-- ChipScope Integrated Logic Analyser |
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component ChipScope_ILA_18_1024 |
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port ( |
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CONTROL: inout std_logic_vector(35 downto 0); |
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CLK: in std_logic; |
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DATA: in std_logic_vector(17 downto 0); -- 18 bits wide data |
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TRIG0: in std_logic_vector(23 downto 0); |
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TRIG_OUT: out std_logic |
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); |
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end component; |
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-- ChipScope Integrated Logic Analyser |
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component ChipScope_ILA_9_2048 |
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port ( |
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CONTROL: inout std_logic_vector(35 downto 0); |
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CLK: in std_logic; |
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DATA: in std_logic_vector(8 downto 0); -- 9 bits wide data |
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TRIG0: in std_logic_vector(23 downto 0); |
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TRIG_OUT: out std_logic |
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); |
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end component; |
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begin |
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-- =================================================== |
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-- Clock Network and Clock Switching |
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-- =================================================== |
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-- |
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-- The fastest clock signal is generated from 100MHz by DCM. |
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-- The design maximim is 170MHz for selected device. |
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-- |
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-- For lower frequency the 100MHz clocks are gated in BUFGCE |
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-- acording to SET_CLK_xxx signals. |
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-- |
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-- For Logic Analyser we use 170MHz from DCM or gated 100MHz |
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-- switchd by BUFGMUX block. |
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-- DCM_SP: Digital Clock Manager Circuit |
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-- Spartan-3A |
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-- Xilinx HDL Language Template, version 14.5 |
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-- |
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-- CLKFB without BUFG (we do not need phase relation to the original clock) |
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-- |
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-- Design Limits (XC3S50AN-4): |
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-- |
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-- 5/3 -> 166MHz - o.k. (best 5.9ns - 169.5MHz) |
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-- 17/10 -> 170MHz - o.k. (best 5.748ns - 174MHz) <------ Used Here |
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-- 12/7 -> 171MHz - Timing Error |
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-- 7/4 -> 175MHz - Timing Error |
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-- 18/10 -> 180MHz - Timing Error |
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-- |
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DCM_SP_inst: DCM_SP |
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generic map ( |
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 |
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CLKFX_DIVIDE => 10, -- Can be any interger from 1 to 32 |
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CLKFX_MULTIPLY => 17, -- Can be any integer from 2 to 32 |
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CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature |
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CLKIN_PERIOD => 10.0, -- Specify period of input clock |
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CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" |
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CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" |
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15 |
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DLL_FREQUENCY_MODE => "HIGH", -- "HIGH" or "LOW" frequency mode for DLL |
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DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE |
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PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 |
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STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE |
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) |
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port map ( |
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CLK0 => DCM_CLK0, -- 0 degree DCM CLK ouptput |
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-- CLK180 => CLK180, -- 180 degree DCM CLK output |
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-- CLK270 => CLK270, -- 270 degree DCM CLK output |
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-- CLK2X => CLK2X, -- 2X DCM CLK output |
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-- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out |
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-- CLK90 => CLK90, -- 90 degree DCM CLK output |
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-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE) |
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CLKFX => DCM_CLKFX, -- DCM CLK synthesis out (M/D) |
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-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out |
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-- LOCKED => LOCKED, -- DCM LOCK status output |
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-- PSDONE => PSDONE, -- Dynamic phase adjust done output |
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-- STATUS => STATUS, -- 8-bit DCM status bits output |
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CLKFB => DCM_CLK0, -- DCM clock feedback |
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CLKIN => CLK100MHz, -- Clock input (from IBUFG, BUFG or DCM) |
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-- PSCLK => PSCLK, -- Dynamic phase adjust clock input |
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-- PSEN => PSEN, -- Dynamic phase adjust enable input |
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-- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement |
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RST => '0' -- DCM asynchronous reset input |
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); |
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-- Generate Clock Gate signal for 100MHz Clock |
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process (CLK100MHz) |
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begin |
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if rising_edge(CLK100MHz) then |
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if CLK100MHz_CE_Cnt=0 then |
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CLK100MHz_CE <= '1'; |
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if SET_CLK_100MHz='1' then |
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CLK100MHz_CE_Cnt <= to_unsigned(1-1, CLK100MHz_CE_Cnt'length); |
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elsif SET_CLK_50MHz='1' then |
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CLK100MHz_CE_Cnt <= to_unsigned(2-1, CLK100MHz_CE_Cnt'length); |
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elsif SET_CLK_20MHz='1' then |
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CLK100MHz_CE_Cnt <= to_unsigned(5-1, CLK100MHz_CE_Cnt'length); |
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elsif SET_CLK_10MHz='1' then |
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CLK100MHz_CE_Cnt <= to_unsigned(10-1, CLK100MHz_CE_Cnt'length); |
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elsif SET_CLK_5MHz='1' then |
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CLK100MHz_CE_Cnt <= to_unsigned(20-1, CLK100MHz_CE_Cnt'length); |
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elsif SET_CLK_2MHz='1' then |
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CLK100MHz_CE_Cnt <= to_unsigned(50-1, CLK100MHz_CE_Cnt'length); |
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elsif SET_CLK_1MHz='1' then |
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CLK100MHz_CE_Cnt <= to_unsigned(100-1, CLK100MHz_CE_Cnt'length); |
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end if; |
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else |
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CLK100MHz_CE <= '0'; |
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CLK100MHz_CE_Cnt <= CLK100MHz_CE_Cnt-1; |
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end if; |
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end if; |
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end process; |
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-- Gate 100MHz Clocks (to produce 100/50/20/10/5/2/1 MHz) |
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-- Generates 5ns pulses with 10/20/50/100/200/500/1000ns period |
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BUFGCE_CLK100MHz: BUFGCE |
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port map ( |
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I => CLK100MHz, -- Clock buffer input |
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CE => CLK100MHz_CE, -- Clock enable input |
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O => CLK100MHz_Gated -- Clock buffer ouptput |
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); |
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-- Switch (gated) 100MHz and the fastest Clock signal from DCM |
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BUFGMUX_CLK_FAST: BUFGMUX |
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port map ( |
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I0 => CLK100MHz_Gated, -- Clock0 input -- 100/50/20/10/50/20/1MHz |
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I1 => DCM_CLKFX, -- Clock1 input -- 170MHz |
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S => SET_CLK_MAX, -- Clock select input |
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O => CLK_FAST -- Clock MUX output |
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); |
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-- Assynchrnous inputs and inputs from CLK_FAST clock domain must be synchronised |
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-- SYNC_OUT - CLK_FAST clock domain |
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-- DIPSW - External (off-chip) async inputs |
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process (CLK100MHz) |
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begin |
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if rising_edge(CLK100MHz) then |
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SW_SYNC <= SYNC_OUT or DIPSW; |
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end if; |
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end process; |
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-- Ferquency Selector |
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-- FSM - 1 hot |
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process (CLK100MHz) |
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variable TMP: std_logic_vector(SYNC_OUT'range); |
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variable NEW_DATA: std_logic; |
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begin |
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if rising_edge(CLK100MHz) then |
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TMP := (others => '0'); |
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NEW_DATA := '1'; |
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if SW_SYNC(7)='1' then |
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TMP(7) := '1'; |
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elsif SW_SYNC(6)='1' then |
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TMP(6) := '1'; |
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elsif SW_SYNC(5)='1' then |
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TMP(5) := '1'; |
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elsif SW_SYNC(4)='1' then |
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TMP(4) := '1'; |
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elsif SW_SYNC(3)='1' then |
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|
346 |
TMP(3) := '1'; |
|
|
347 |
elsif SW_SYNC(2)='1' then |
|
|
348 |
TMP(2) := '1'; |
|
|
349 |
elsif SW_SYNC(1)='1' then |
|
|
350 |
TMP(1) := '1'; |
|
|
351 |
elsif SW_SYNC(0)='1' then |
|
|
352 |
TMP(0) := '1'; |
|
|
353 |
else |
|
|
354 |
NEW_DATA := '0'; |
|
|
355 |
end if; |
|
|
356 |
if NEW_DATA='1' then |
|
|
357 |
SET_CLK_MAX <= TMP(7); |
|
|
358 |
SET_CLK_100MHz <= TMP(6); |
|
|
359 |
SET_CLK_50MHz <= TMP(5); |
|
|
360 |
SET_CLK_20MHz <= TMP(4); |
|
|
361 |
SET_CLK_10MHz <= TMP(3); |
|
|
362 |
SET_CLK_5MHz <= TMP(2); |
|
|
363 |
SET_CLK_2MHz <= TMP(1); |
|
|
364 |
SET_CLK_1MHz <= TMP(0); |
|
|
365 |
end if; |
|
|
366 |
end if; |
|
|
367 |
end process; |
|
|
368 |
|
|
|
369 |
|
|
|
370 |
-- Send selected frequency to ChipScope Virtual IO |
|
|
371 |
-- Sync it to the CLK_FAST timing domain |
|
|
372 |
SET_CLK_proc: process (CLK_FAST) |
|
|
373 |
begin |
|
|
374 |
if rising_edge(CLK_FAST) then |
|
|
375 |
SYNC_IN(7) <= SET_CLK_MAX; |
|
|
376 |
SYNC_IN(6) <= SET_CLK_100MHz; |
|
|
377 |
SYNC_IN(5) <= SET_CLK_50MHz; |
|
|
378 |
SYNC_IN(4) <= SET_CLK_20Mhz; |
|
|
379 |
SYNC_IN(3) <= SET_CLK_10Mhz; |
|
|
380 |
SYNC_IN(2) <= SET_CLK_5Mhz; |
|
|
381 |
SYNC_IN(1) <= SET_CLK_2Mhz; |
|
|
382 |
SYNC_IN(0) <= SET_CLK_1Mhz; |
|
|
383 |
end if; |
|
|
384 |
end process; |
|
|
385 |
|
|
|
386 |
|
|
|
387 |
-- =================================================== |
|
|
388 |
-- ChipScope Instance - Control / Virtual IO / ILA |
|
|
389 |
-- =================================================== |
|
|
390 |
|
|
|
391 |
|
|
|
392 |
-- ChipScope Instance - Control Block |
|
|
393 |
MyChipScopeICON: ChipScope_ICON |
|
|
394 |
port map ( |
|
|
395 |
CONTROL0 => Control0, |
|
|
396 |
CONTROL1 => Control1, |
|
|
397 |
CONTROL2 => Control2 |
|
|
398 |
); |
|
|
399 |
|
|
|
400 |
|
|
|
401 |
-- ChipScope Instance - Virtual I/O Block |
|
|
402 |
MyChipScopeVIO_FreqSel: ChipScope_VIO_FreqSel |
|
|
403 |
port map ( |
|
|
404 |
CONTROL => Control0, |
|
|
405 |
CLK => CLK_FAST, |
|
|
406 |
SYNC_IN => SYNC_IN, |
|
|
407 |
SYNC_OUT => SYNC_OUT |
|
|
408 |
); |
|
|
409 |
|
|
|
410 |
|
|
|
411 |
-- ChipScope Instance - Virtual I/O Block |
|
|
412 |
MyChipScopeVIO_UserOut: ChipScope_VIO_UserOut |
|
|
413 |
port map ( |
|
|
414 |
CONTROL => Control1, |
|
|
415 |
CLK => CLK_FAST, |
|
|
416 |
SYNC_OUT => SYNC_OUT_USER |
|
|
417 |
); |
|
|
418 |
|
|
|
419 |
|
|
|
420 |
-- ChipScope Instance - Integrated Logic Analyser |
|
|
421 |
ILA_18_1024: if ILA_WIDE generate |
|
|
422 |
begin |
|
|
423 |
MyChipScopeILA: ChipScope_ILA_18_1024 |
|
|
424 |
port map ( |
|
|
425 |
CONTROL => Control2, |
|
|
426 |
CLK => CLK_FAST, |
|
|
427 |
DATA => DataReg(17 downto 0), |
|
|
428 |
TRIG0 => DataReg(23 downto 0), |
|
|
429 |
TRIG_OUT => TriggerOut |
|
|
430 |
); |
|
|
431 |
end generate; |
|
|
432 |
ILA_9_2048: if not ILA_WIDE generate |
|
|
433 |
begin |
|
|
434 |
MyChipScopeILA: ChipScope_ILA_9_2048 |
|
|
435 |
port map ( |
|
|
436 |
CONTROL => Control2, |
|
|
437 |
CLK => CLK_FAST, |
|
|
438 |
DATA => DataReg(8 downto 0), |
|
|
439 |
TRIG0 => DataReg(23 downto 0), |
|
|
440 |
TRIG_OUT => TriggerOut |
|
|
441 |
); |
|
|
442 |
end generate; |
|
|
443 |
|
|
|
444 |
|
|
|
445 |
-- Data inputs (ILA does not like to have data inputs connected to io pins) |
|
|
446 |
process(CLK_FAST) |
|
|
447 |
begin |
|
|
448 |
if rising_edge(CLK_FAST) then |
|
|
449 |
DataReg <= P(DataReg'range); |
|
|
450 |
end if; |
|
|
451 |
end process; |
|
|
452 |
|
|
|
453 |
|
|
|
454 |
-- VIO User Outputs |
|
|
455 |
VS <= SYNC_OUT_USER; |
|
|
456 |
|
|
|
457 |
|
|
|
458 |
-- Trigger Output (Diferencial signal) |
|
|
459 |
OBUFDS_TriggerOut: OBUFDS |
|
|
460 |
generic map ( |
|
|
461 |
IOSTANDARD => "DEFAULT" |
|
|
462 |
) |
|
|
463 |
port map ( |
|
|
464 |
I => TriggerOut, -- Buffer input |
|
|
465 |
O => DIF1P, -- Diff_p output (connect directly to top-level port) |
|
|
466 |
OB => DIF1N -- Diff_n output (connect directly to top-level port) |
|
|
467 |
); |
|
|
468 |
|
|
|
469 |
|
|
|
470 |
-- =================================================== |
|
|
471 |
-- LED Display (multiplexed) |
|
|
472 |
-- =================================================== |
|
|
473 |
|
|
|
474 |
|
|
|
475 |
-- Frequency in BCD |
|
|
476 |
FrequencyBCD <= "00001"&"00111"&"00000" when SET_CLK_MAX='1' else -- 170 MHz |
|
|
477 |
"00001"&"00000"&"00000" when SET_CLK_100MHz='1' else -- 100 MHz |
|
|
478 |
"11111"&"00101"&"00000" when SET_CLK_50MHz='1' else -- 50 MHz |
|
|
479 |
"11111"&"00010"&"00000" when SET_CLK_20MHz='1' else -- 20 MHz |
|
|
480 |
"11111"&"00001"&"00000" when SET_CLK_10MHz='1' else -- 10 MHz |
|
|
481 |
"11111"&"11111"&"00101" when SET_CLK_5MHz='1' else -- 5 MHz |
|
|
482 |
"11111"&"11111"&"00010" when SET_CLK_2MHz='1' else -- 2 MHz |
|
|
483 |
"11111"&"11111"&"00001" when SET_CLK_1MHz='1' else -- 1 MHz |
|
|
484 |
"11111"&"11111"&"11111"; |
|
|
485 |
|
|
|
486 |
|
|
|
487 |
-- ILA width in BCD |
|
|
488 |
ILA_DCD_18_1024: if ILA_WIDE generate |
|
|
489 |
begin |
|
|
490 |
WideBCD <= "00001"&"01000"; |
|
|
491 |
end generate; |
|
|
492 |
ILA_DCD_9_2048: if not ILA_WIDE generate |
|
|
493 |
begin |
|
|
494 |
WideBCD <= "11111"&"01001"; |
|
|
495 |
end generate; |
|
|
496 |
|
|
|
497 |
|
|
|
498 |
-- Input data selector ( WIDE / ILA / FREQ ) |
|
|
499 |
Code <= FrequencyBCD( 4 downto 0) when Digits="00000001" else |
|
|
500 |
FrequencyBCD( 9 downto 5) when Digits="00000010" else |
|
|
501 |
FrequencyBCD(14 downto 10) when Digits="00000100" else |
|
|
502 |
"10010" when Digits="00001000" else -- A |
|
|
503 |
"10001" when Digits="00010000" else -- L |
|
|
504 |
"10000" when Digits="00100000" else -- I |
|
|
505 |
WideBCD( 4 downto 0) when Digits="01000000" else |
|
|
506 |
WideBCD( 9 downto 5) when Digits="10000000" else |
|
|
507 |
"11111"; |
|
|
508 |
|
|
|
509 |
|
|
|
510 |
-- Time Multiplex |
|
|
511 |
process (CLK100MHz) |
|
|
512 |
begin |
|
|
513 |
if rising_edge(CLK100MHz) then |
|
|
514 |
if MuxCounter < MUXCOUNT-1 then |
|
|
515 |
MuxCounter <= MuxCounter + 1; |
|
|
516 |
else |
|
|
517 |
MuxCounter <= (others => '0'); |
|
|
518 |
Digits(7 downto 0) <= Digits(6 downto 0) & Digits(7); -- Rotate Left (1 hot encoded) |
|
|
519 |
end if; |
|
|
520 |
-- Display brightness (1/2) |
|
|
521 |
if MuxCounter > (MUXCOUNT-MUXCOUNT/2) then |
|
|
522 |
LedEnable <= '1'; |
|
|
523 |
else |
|
|
524 |
LedEnable <= '0'; |
|
|
525 |
end if; |
|
|
526 |
end if; |
|
|
527 |
end process; |
|
|
528 |
|
|
|
529 |
|
|
|
530 |
-- BCD to 7 Segmet Decoder |
|
|
531 |
-- -- A |
|
|
532 |
-- | | F B |
|
|
533 |
-- -- G |
|
|
534 |
-- | | E C |
|
|
535 |
-- -- D H |
|
|
536 |
-- HGFEDCBA |
|
|
537 |
Segments <= "00111111" when Code="00000" else -- Digit 0 -- Hex Didits |
|
|
538 |
"00000110" when Code="00001" else -- Digit 1 |
|
|
539 |
"01011011" when Code="00010" else -- Digit 2 |
|
|
540 |
"01001111" when Code="00011" else -- Digit 3 |
|
|
541 |
"01100110" when Code="00100" else -- Digit 4 |
|
|
542 |
"01101101" when Code="00101" else -- Digit 5 |
|
|
543 |
"01111101" when Code="00110" else -- Digit 6 |
|
|
544 |
"00000111" when Code="00111" else -- Digit 7 |
|
|
545 |
"01111111" when Code="01000" else -- Digit 8 |
|
|
546 |
"01101111" when Code="01001" else -- Digit 9 |
|
|
547 |
"01110111" when Code="01010" else -- Digit A |
|
|
548 |
"01111100" when Code="01011" else -- Digit b |
|
|
549 |
"00111001" when Code="01100" else -- Digit C |
|
|
550 |
"01011110" when Code="01101" else -- Digit d |
|
|
551 |
"01111001" when Code="01110" else -- Digit E |
|
|
552 |
"00110001" when Code="01111" else -- Digit F |
|
|
553 |
"00000110" when Code="10000" else -- Digit I -- User Digits |
|
|
554 |
"00111000" when Code="10001" else -- Digit L |
|
|
555 |
"01110111" when Code="10010" else -- Digit A |
|
|
556 |
"00000000"; -- none |
|
|
557 |
|
|
|
558 |
|
|
|
559 |
-- Connect LED Display Output Ports (negative outputs) |
|
|
560 |
LD_CA_n <= not Digits; |
|
|
561 |
LD_SEG_n <= not Segments when LedEnable='1' else "11111111"; |
|
|
562 |
|
|
|
563 |
|
|
|
564 |
-- =================================================== |
|
|
565 |
-- Test generator (counter) |
|
|
566 |
-- =================================================== |
|
|
567 |
|
|
|
568 |
-- Test counter |
|
|
569 |
process(CLK100MHz) |
|
|
570 |
begin |
|
|
571 |
if rising_edge(CLK100MHz) then |
|
|
572 |
Counter <= std_logic_vector(unsigned(Counter) + 1); |
|
|
573 |
end if; |
|
|
574 |
end process; |
|
|
575 |
|
|
|
576 |
|
|
|
577 |
-- Test outputs |
|
|
578 |
LED <= Counter; |
|
|
579 |
|
|
|
580 |
|
|
|
581 |
-- CLK_FAST Output - DDR register |
|
|
582 |
ODDR2_FastClk: ODDR2 |
|
|
583 |
generic map( |
|
|
584 |
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" |
|
|
585 |
INIT => '0', -- Sets initial state of the Q output to '0' or '1' |
|
|
586 |
SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset |
|
|
587 |
) |
|
|
588 |
port map ( |
|
|
589 |
C0 => CLK_FAST, -- 1-bit clock input |
|
|
590 |
C1 => not CLK_FAST, -- 1-bit clock input |
|
|
591 |
CE => '1', -- 1-bit clock enable input |
|
|
592 |
D0 => '0', -- 1-bit data input (associated with C0) |
|
|
593 |
D1 => '1', -- 1-bit data input (associated with C1) |
|
|
594 |
R => '0', -- 1-bit reset input |
|
|
595 |
S => '0', -- 1-bit set input |
|
|
596 |
Q => CLK_FAST_Q -- 1-bit output data |
|
|
597 |
); |
|
|
598 |
|
|
|
599 |
|
|
|
600 |
-- CLK_FAST Output - differncial pin buffer |
|
|
601 |
OBUFDS_FastClkOut: OBUFDS |
|
|
602 |
generic map ( |
|
|
603 |
IOSTANDARD => "DEFAULT" |
|
|
604 |
) |
|
|
605 |
port map ( |
|
|
606 |
I => CLK_FAST_Q, -- Buffer input |
|
|
607 |
O => DIF2P, -- Diff_p output (connect directly to top-level port) |
|
|
608 |
OB => DIF2N -- Diff_n output (connect directly to top-level port) |
|
|
609 |
); |
|
|
610 |
|
|
|
611 |
|
|
|
612 |
end S3AN01_ChipScope_a; |