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@echo off |
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rem Batch to (re)generate IP cores (ChipScope components) |
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rem Run once, takes several minutes to finish. |
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rem |
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rem Do not modify source files directory structure |
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rem |
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rem Tested with Xilinx ISE WebPack 13.3 and 14.5 |
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rem This step does not require ChipScope License |
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rem |
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rem ----- Find and Set Xilinx Tools |
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call FindXilinxTools.cmd |
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rem ----- Run Coregen in paralel (we all have multicore cpu don't we?) |
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rem Unfortunately CoreGen can't be run in parallel. |
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rem There is some conflict (You cenrtainly know what all that cores are good for...) |
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rem start "CoreGen ICON" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r |
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rem start "CoreGen ILA 18x1024" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r |
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rem start "CoreGen ILA 9x2048" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r |
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rem start "CoreGen VIO FreqSel" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r |
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rem start "CoreGen VIO UserOut" coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r |
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rem ----- Run CoreGen one after one for all components |
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coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ICON.xco -r |
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if %errorlevel% NEQ 0 ( |
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echo. |
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echo. |
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echo ERROR in coregen ChipScope_ICON |
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echo =============================== |
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pause |
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exit 1 |
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) |
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coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_18_1024.xco -r |
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if %errorlevel% NEQ 0 ( |
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echo. |
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echo. |
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echo ERROR in coregen ChipScope_ILA_18_1024 |
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echo ====================================== |
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pause |
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exit 1 |
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) |
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coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_ILA_9_2048.xco -r |
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if %errorlevel% NEQ 0 ( |
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echo. |
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echo. |
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echo ERROR in coregen ChipScope_ILA_9_2048 |
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echo ===================================== |
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pause |
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exit 1 |
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) |
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coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_FreqSel.xco -r |
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if %errorlevel% NEQ 0 ( |
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echo. |
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echo. |
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echo ERROR in coregen ChipScope_VIO_FreqSel |
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echo ====================================== |
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pause |
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exit 1 |
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) |
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coregen -p ..\COREGEN -b ..\COREGEN\ChipScope_VIO_UserOut.xco -r |
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if %errorlevel% NEQ 0 ( |
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echo. |
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echo. |
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echo ERROR in coregen ChipScope_VIO_UserOut |
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echo ====================================== |
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pause |
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exit 1 |
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) |
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rem ----- Finished |
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rm coregen.log |
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echo. |
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echo CoreGen Finished with no Errors |