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[InfoShortDescription.en] |
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PECL Clock divider |
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[InfoShortDescription.cs] |
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Dělička hodin s PECL vstupem |
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[InfoLongDescription.en] |
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Multiple division ration can be selected by FSEL pin. Possible division ration are: (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) every output is synchronous each other. The common enable (EN) is synchronous so that the |
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internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. |
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[InfoLongDescription.cs] |
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Může být nastaveno více dělících poměrů. Možnosti jsou (÷1, ÷2, ÷4) nebo (÷2, ÷4, ÷8). EN vstup je synchronní s interními hodinami, proto dojde k vypnutí při návratu na nulu. |
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[End] |