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mija |
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/* mija 2008 |
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defines for module RFM01 - RX 868MHz |
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*/ |
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#define CMD_SETTING 0x8000 // b1, b0, eb, et, ex, x3..x0, i2..i0, dc |
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#define CMD_FREQUENCY 0xA000 // f11..f0 860+F*0.005 MHz 36..3903 |
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#define CMD_RATE 0xC800 // cs, r6..r0 BR=10M/29/(R+1)/1+cs*7) |
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#define CMD_RX 0xC000 // d1, d0, g1, g0, r2..r0, en |
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#define CMD_FILTER 0xC420 // al, ml, s1, s0, f2..f0 |
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#define CMD_FIFO 0xCE00 // f3..f0, s1, s0, ff, fe |
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#define CMD_AFC 0xC600 // a1, a0, rl1, rl0, st, fi, oe, en |
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#define CMD_WAKE_UP 0xE000 // r4..r0, m7..m0 T=M*2^R [ms] |
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#define CMD_DUTY 0xCC00 // d6..d0 D.C.= (D*2+1)/M*100% |
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#define CMD_BATTERY 0xC200 // d2..d0, t4..t0 |
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#define CMD_STATUS 0x0000 // for read status |
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// CMD_SETTING |
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#define BAND_315 0x0000 |
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#define BAND_433 0x800 |
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#define BAND_868 0x1000 |
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#define BADN_915 0x1800 |
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#define SETTING_EB 0x400 // enable low battery detect |
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#define SETTING_ET 0x200 // enable wake-up timer |
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#define SETTING_EX 0x100 // enable crystal oscilator |
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#define C_8_5pF 0x00 |
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#define C_9pF 0x10 |
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#define C_9_5pF 0x20 |
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#define C_10pF 0x30 |
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#define C_10_5pF 0x40 |
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#define C_11pF 0x50 |
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#define C_11_5pF 0x60 |
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#define C_12pF 0x70 |
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#define C_12_5pF 0x80 |
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#define C_13pF 0x90 |
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#define C_13_5pF 0xA0 |
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#define C_14pF 0xB0 |
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#define C_14_5pF 0xC0 |
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#define C_15pF 0xD0 |
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#define C_15_5pF 0xE0 |
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#define C_16pF 0xF0 |
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#define BANDWIDTH_400 0x02 // baseband bandwidth[kHz] |
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#define BANDWIDTH_340 0x04 |
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#define BANDWIDTH_270 0x06 |
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#define BANDWIDTH_200 0x08 |
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#define BANDWIDTH_134 0x0A |
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#define BANDWIDTH_67 0x0C |
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#define SETTING_DC 0x01 // disable siglanl of CLK pin |
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// CMD_FREQUENCY |
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#define FREQUENCY_867 0x578 |
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#define FREQUENCY_868 0x640 |
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#define FREQUENCY_869 0x708 |
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// CMD_RATE |
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#define RATE_1200 0x123 |
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#define RATE_2400 0x8F |
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#define RATE_4800 0x47 |
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#define RATE_CS_4800 0x108 |
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#define RATE_9600 0x23 |
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#define RATE_19200 0x11 |
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#define RATE_38400 0x8 |
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#define RATE_57600 0x5 |
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#define RATE_115200 0x2 |
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// CMD_RX |
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#define VDI_RSSI 0x00 // VDI response time |
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#define VDI_DQD 0x40 |
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#define VDI_CLOCK 0x80 |
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#define VDI_ALWAYS_ON 0xC0 |
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#define LNA_GAIN_0 0x00 // LNA_GAIN |
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#define LNA_GAIN_6 0x10 // -6dBm |
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#define LNA_GAIN_14 0x20 // -14dBm |
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#define LNA_GAIN_20 0x30 // -20dBm |
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#define DRSSI_103 0x00 // RSSI= DRSSI + LNA_GAIN -103dBm |
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#define DRSSI_97 0x02 // -97dBm |
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#define DRSSI_91 0x04 // -91dBm |
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#define DRSSI_85 0x06 // -85dBm |
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#define DRSSI_79 0x08 // -79dBm |
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#define DRSSI_73 0x0A // -73dBm |
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#define DRSSI_67 0x0C // -67dBm |
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#define DRSSI_61 0x0E // -61dBm |
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#define RX_EN 0x01 // enablel receiver |
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// CMD_FILTER |
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#define FILTER_AL 0x80 // enable clock recovery atuo-lock |
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#define FILTER_ML 0x40 // enable clock recovery fast mode |
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#define FILTER_S0 0x08 // enable digital filter |
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#define DQD_7 0x7 |
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#define DQD_6 0x6 |
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#define DQD_5 0x5 |
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#define DQD_4 0x4 |
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#define DQD_3 0x3 |
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#define DQD_2 0x2 |
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#define DQD_1 0x1 |
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#define DQD_0 0x0 |
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// CMD_FIFO |
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#define FIFO_16 0x00 // FIFO level |
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#define FIFO_15 0xF0 |
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#define FIFO_14 0xE0 |
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#define FIFO_13 0xD0 |
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#define FIFO_12 0xC0 |
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#define FIFO_11 0xB0 |
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#define FIFO_10 0xA0 |
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#define FIFO_9 0x90 |
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#define FIFO_8 0x80 |
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#define FIFO_7 0x70 |
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#define FIFO_6 0x60 |
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#define FIFO_5 0x50 |
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#define FIFO_4 0x40 |
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#define FIFO_3 0x30 |
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#define FIFO_2 0x20 |
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#define FIFO_1 0x10 |
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#define FIFO_VDI 0x00 // FIFO start VDI |
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#define FIFO_SYNC_WORD 0x04 // |
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#define FIFO_VDI_WORD 0x08 // |
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#define FIFO_ALWAYS 0x0C // |
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#define FIFO_FF 0x02 // enable FIFO fill |
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#define FIFO_FE 0x01 // enable FIFO function |
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// CMD_AFC |
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#define AFC_MCU 0x00 // AFC auto_mode by MCU |
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#define AFC_POWER_ON 0x40 // AFC at poweron |
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#define AFC_OFFSET 0x80 // AFC keep offset when VDI hi |
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#define AFC_VDI 0xC0 // AFC keeps independently from VDI |
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#define AFC_NORESTR 0x00 // range limit no restriction |
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#define AFC_RANG_16 0x10 // range limit +15/-16 |
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#define AFC_RANG_8 0x20 // range limit +7/-8 |
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#define AFC_RANG_4 0x30 // range limit +3/-4 |
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#define AFC_ST 0x08 // store offset into outpur register |
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#define AFC_FI 0x04 // enable AFC hi accuracy mode |
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#define AFC_OE 0x02 // enable AFC output register |
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#define AFC_EN 0x01 // enable AFC function |
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