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/****************************************************************************** |
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* @file: core_cm3.h |
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* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File |
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* @version: V1.20 |
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* @date: 22. May 2009 |
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*---------------------------------------------------------------------------- |
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* |
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* Copyright (C) 2009 ARM Limited. All rights reserved. |
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* |
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* ARM Limited (ARM) is supplying this software for use with Cortex-Mx |
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* processor based microcontrollers. This file can be freely distributed |
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* within development tools that are supporting such ARM based processors. |
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* |
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
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* |
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******************************************************************************/ |
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#ifndef __CM3_CORE_H__ |
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#define __CM3_CORE_H__ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ |
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#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ |
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#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
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#define __CORTEX_M (0x03) /*!< Cortex core */ |
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/** |
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* Lint configuration \n |
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* ----------------------- \n |
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* |
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* The following Lint messages will be suppressed and not shown: \n |
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* \n |
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* --- Error 10: --- \n |
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* register uint32_t __regBasePri __asm("basepri"); \n |
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* Error 10: Expecting ';' \n |
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* \n |
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* --- Error 530: --- \n |
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* return(__regBasePri); \n |
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* Warning 530: Symbol '__regBasePri' (line 264) not initialized \n |
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* \n |
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* --- Error 550: --- \n |
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* __regBasePri = (basePri & 0x1ff); \n |
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* } \n |
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* Warning 550: Symbol '__regBasePri' (line 271) not accessed \n |
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* \n |
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* --- Error 754: --- \n |
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* uint32_t RESERVED0[24]; \n |
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* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n |
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* \n |
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* --- Error 750: --- \n |
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* #define __CM3_CORE_H__ \n |
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* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n |
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* \n |
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* --- Error 528: --- \n |
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* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n |
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* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n |
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* \n |
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* --- Error 751: --- \n |
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* } InterruptType_Type; \n |
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* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n |
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* \n |
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* \n |
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* Note: To re-enable a Message, insert a space before 'lint' * \n |
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* |
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*/ |
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/*lint -save */ |
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/*lint -e10 */ |
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/*lint -e530 */ |
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/*lint -e550 */ |
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/*lint -e754 */ |
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/*lint -e750 */ |
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/*lint -e528 */ |
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/*lint -e751 */ |
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#include <stdint.h> /* Include standard types */ |
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#if defined (__ICCARM__) |
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#include <intrinsics.h> /* IAR Intrinsics */ |
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#endif |
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#ifndef __NVIC_PRIO_BITS |
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#define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ |
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#endif |
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/** |
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* IO definitions |
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* |
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* define access restrictions to peripheral registers |
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*/ |
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#ifdef __cplusplus |
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#define __I volatile /*!< defines 'read only' permissions */ |
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#else |
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#define __I volatile const /*!< defines 'read only' permissions */ |
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#endif |
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#define __O volatile /*!< defines 'write only' permissions */ |
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#define __IO volatile /*!< defines 'read / write' permissions */ |
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/******************************************************************************* |
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* Register Abstraction |
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******************************************************************************/ |
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/* System Reset */ |
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#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ |
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#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ |
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#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ |
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#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ |
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/* Core Debug */ |
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#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */ |
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#define ITM_TCR_ITMENA 1 /*!< ITM enable */ |
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/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ |
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typedef struct |
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{ |
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__IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */ |
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uint32_t RESERVED0[24]; |
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__IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */ |
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uint32_t RSERVED1[24]; |
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__IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */ |
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uint32_t RESERVED2[24]; |
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__IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */ |
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uint32_t RESERVED3[24]; |
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__IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */ |
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uint32_t RESERVED4[56]; |
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__IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */ |
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uint32_t RESERVED5[644]; |
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__O uint32_t STIR; /*!< Software Trigger Interrupt Register */ |
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} NVIC_Type; |
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/* memory mapping struct for System Control Block */ |
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typedef struct |
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{ |
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__I uint32_t CPUID; /*!< CPU ID Base Register */ |
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__IO uint32_t ICSR; /*!< Interrupt Control State Register */ |
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__IO uint32_t VTOR; /*!< Vector Table Offset Register */ |
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__IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ |
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__IO uint32_t SCR; /*!< System Control Register */ |
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__IO uint32_t CCR; /*!< Configuration Control Register */ |
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__IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
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__IO uint32_t SHCSR; /*!< System Handler Control and State Register */ |
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__IO uint32_t CFSR; /*!< Configurable Fault Status Register */ |
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__IO uint32_t HFSR; /*!< Hard Fault Status Register */ |
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__IO uint32_t DFSR; /*!< Debug Fault Status Register */ |
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__IO uint32_t MMFAR; /*!< Mem Manage Address Register */ |
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__IO uint32_t BFAR; /*!< Bus Fault Address Register */ |
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__IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */ |
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__I uint32_t PFR[2]; /*!< Processor Feature Register */ |
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__I uint32_t DFR; /*!< Debug Feature Register */ |
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__I uint32_t ADR; /*!< Auxiliary Feature Register */ |
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__I uint32_t MMFR[4]; /*!< Memory Model Feature Register */ |
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__I uint32_t ISAR[5]; /*!< ISA Feature Register */ |
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} SCB_Type; |
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/* memory mapping struct for SysTick */ |
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typedef struct |
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{ |
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__IO uint32_t CTRL; /*!< SysTick Control and Status Register */ |
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__IO uint32_t LOAD; /*!< SysTick Reload Value Register */ |
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__IO uint32_t VAL; /*!< SysTick Current Value Register */ |
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__I uint32_t CALIB; /*!< SysTick Calibration Register */ |
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} SysTick_Type; |
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/* memory mapping structur for ITM */ |
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typedef struct |
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{ |
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__O union |
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{ |
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__O uint8_t u8; /*!< ITM Stimulus Port 8-bit */ |
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__O uint16_t u16; /*!< ITM Stimulus Port 16-bit */ |
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__O uint32_t u32; /*!< ITM Stimulus Port 32-bit */ |
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} PORT [32]; /*!< ITM Stimulus Port Registers */ |
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uint32_t RESERVED0[864]; |
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__IO uint32_t TER; /*!< ITM Trace Enable Register */ |
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uint32_t RESERVED1[15]; |
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__IO uint32_t TPR; /*!< ITM Trace Privilege Register */ |
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uint32_t RESERVED2[15]; |
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__IO uint32_t TCR; /*!< ITM Trace Control Register */ |
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uint32_t RESERVED3[29]; |
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__IO uint32_t IWR; /*!< ITM Integration Write Register */ |
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__IO uint32_t IRR; /*!< ITM Integration Read Register */ |
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__IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */ |
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uint32_t RESERVED4[43]; |
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__IO uint32_t LAR; /*!< ITM Lock Access Register */ |
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__IO uint32_t LSR; /*!< ITM Lock Status Register */ |
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uint32_t RESERVED5[6]; |
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__I uint32_t PID4; /*!< ITM Product ID Registers */ |
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__I uint32_t PID5; |
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__I uint32_t PID6; |
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__I uint32_t PID7; |
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__I uint32_t PID0; |
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__I uint32_t PID1; |
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__I uint32_t PID2; |
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__I uint32_t PID3; |
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__I uint32_t CID0; |
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__I uint32_t CID1; |
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__I uint32_t CID2; |
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__I uint32_t CID3; |
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} ITM_Type; |
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/* memory mapped struct for Interrupt Type */ |
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typedef struct |
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{ |
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uint32_t RESERVED0; |
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__I uint32_t ICTR; /*!< Interrupt Control Type Register */ |
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#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) |
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__IO uint32_t ACTLR; /*!< Auxiliary Control Register */ |
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#else |
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uint32_t RESERVED1; |
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#endif |
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} InterruptType_Type; |
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/* Memory Protection Unit */ |
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) |
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typedef struct |
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{ |
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__I uint32_t TYPE; /*!< MPU Type Register */ |
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__IO uint32_t CTRL; /*!< MPU Control Register */ |
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__IO uint32_t RNR; /*!< MPU Region RNRber Register */ |
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__IO uint32_t RBAR; /*!< MPU Region Base Address Register */ |
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__IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */ |
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__IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */ |
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__IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */ |
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__IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */ |
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__IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */ |
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__IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */ |
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__IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */ |
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} MPU_Type; |
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#endif |
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/* Core Debug Register */ |
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typedef struct |
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{ |
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__IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ |
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__O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ |
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__IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ |
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__IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ |
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} CoreDebug_Type; |
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/* Memory mapping of Cortex-M3 Hardware */ |
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#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ |
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#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ |
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#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ |
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#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ |
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#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ |
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#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ |
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#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ |
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#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ |
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#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ |
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#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ |
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#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ |
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#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) |
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#define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ |
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#define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ |
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#endif |
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/******************************************************************************* |
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* Hardware Abstraction Layer |
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******************************************************************************/ |
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#if defined ( __CC_ARM ) |
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#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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#elif defined ( __ICCARM__ ) |
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#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
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#elif defined ( __GNUC__ ) |
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#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
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#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
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#elif defined ( __TASKING__ ) |
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
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#endif |
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/* ################### Compiler specific Intrinsics ########################### */ |
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
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/* ARM armcc specific functions */ |
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#define __enable_fault_irq __enable_fiq |
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#define __disable_fault_irq __disable_fiq |
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#define __NOP __nop |
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#define __WFI __wfi |
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#define __WFE __wfe |
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#define __SEV __sev |
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#define __ISB() __isb(0) |
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#define __DSB() __dsb(0) |
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#define __DMB() __dmb(0) |
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#define __REV __rev |
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#define __RBIT __rbit |
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#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) |
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#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) |
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#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) |
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#define __STREXB(value, ptr) __strex(value, ptr) |
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#define __STREXH(value, ptr) __strex(value, ptr) |
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#define __STREXW(value, ptr) __strex(value, ptr) |
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/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ |
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/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ |
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/* intrinsic void __enable_irq(); */ |
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/* intrinsic void __disable_irq(); */ |
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/** |
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* @brief Return the Process Stack Pointer |
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* |
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* @param none |
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* @return uint32_t ProcessStackPointer |
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* |
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* Return the actual process stack pointer |
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*/ |
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extern uint32_t __get_PSP(void); |
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/** |
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* @brief Set the Process Stack Pointer |
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* |
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* @param uint32_t Process Stack Pointer |
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* @return none |
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* |
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360 |
* Assign the value ProcessStackPointer to the MSP |
|
|
361 |
* (process stack pointer) Cortex processor register |
|
|
362 |
*/ |
|
|
363 |
extern void __set_PSP(uint32_t topOfProcStack); |
|
|
364 |
|
|
|
365 |
/** |
|
|
366 |
* @brief Return the Main Stack Pointer |
|
|
367 |
* |
|
|
368 |
* @param none |
|
|
369 |
* @return uint32_t Main Stack Pointer |
|
|
370 |
* |
|
|
371 |
* Return the current value of the MSP (main stack pointer) |
|
|
372 |
* Cortex processor register |
|
|
373 |
*/ |
|
|
374 |
extern uint32_t __get_MSP(void); |
|
|
375 |
|
|
|
376 |
/** |
|
|
377 |
* @brief Set the Main Stack Pointer |
|
|
378 |
* |
|
|
379 |
* @param uint32_t Main Stack Pointer |
|
|
380 |
* @return none |
|
|
381 |
* |
|
|
382 |
* Assign the value mainStackPointer to the MSP |
|
|
383 |
* (main stack pointer) Cortex processor register |
|
|
384 |
*/ |
|
|
385 |
extern void __set_MSP(uint32_t topOfMainStack); |
|
|
386 |
|
|
|
387 |
/** |
|
|
388 |
* @brief Reverse byte order in unsigned short value |
|
|
389 |
* |
|
|
390 |
* @param uint16_t value to reverse |
|
|
391 |
* @return uint32_t reversed value |
|
|
392 |
* |
|
|
393 |
* Reverse byte order in unsigned short value |
|
|
394 |
*/ |
|
|
395 |
extern uint32_t __REV16(uint16_t value); |
|
|
396 |
|
|
|
397 |
/* |
|
|
398 |
* @brief Reverse byte order in signed short value with sign extension to integer |
|
|
399 |
* |
|
|
400 |
* @param int16_t value to reverse |
|
|
401 |
* @return int32_t reversed value |
|
|
402 |
* |
|
|
403 |
* Reverse byte order in signed short value with sign extension to integer |
|
|
404 |
*/ |
|
|
405 |
extern int32_t __REVSH(int16_t value); |
|
|
406 |
|
|
|
407 |
|
|
|
408 |
#if (__ARMCC_VERSION < 400000) |
|
|
409 |
|
|
|
410 |
/** |
|
|
411 |
* @brief Remove the exclusive lock created by ldrex |
|
|
412 |
* |
|
|
413 |
* @param none |
|
|
414 |
* @return none |
|
|
415 |
* |
|
|
416 |
* Removes the exclusive lock which is created by ldrex. |
|
|
417 |
*/ |
|
|
418 |
extern void __CLREX(void); |
|
|
419 |
|
|
|
420 |
/** |
|
|
421 |
* @brief Return the Base Priority value |
|
|
422 |
* |
|
|
423 |
* @param none |
|
|
424 |
* @return uint32_t BasePriority |
|
|
425 |
* |
|
|
426 |
* Return the content of the base priority register |
|
|
427 |
*/ |
|
|
428 |
extern uint32_t __get_BASEPRI(void); |
|
|
429 |
|
|
|
430 |
/** |
|
|
431 |
* @brief Set the Base Priority value |
|
|
432 |
* |
|
|
433 |
* @param uint32_t BasePriority |
|
|
434 |
* @return none |
|
|
435 |
* |
|
|
436 |
* Set the base priority register |
|
|
437 |
*/ |
|
|
438 |
extern void __set_BASEPRI(uint32_t basePri); |
|
|
439 |
|
|
|
440 |
/** |
|
|
441 |
* @brief Return the Priority Mask value |
|
|
442 |
* |
|
|
443 |
* @param none |
|
|
444 |
* @return uint32_t PriMask |
|
|
445 |
* |
|
|
446 |
* Return the state of the priority mask bit from the priority mask |
|
|
447 |
* register |
|
|
448 |
*/ |
|
|
449 |
extern uint32_t __get_PRIMASK(void); |
|
|
450 |
|
|
|
451 |
/** |
|
|
452 |
* @brief Set the Priority Mask value |
|
|
453 |
* |
|
|
454 |
* @param uint32_t PriMask |
|
|
455 |
* @return none |
|
|
456 |
* |
|
|
457 |
* Set the priority mask bit in the priority mask register |
|
|
458 |
*/ |
|
|
459 |
extern void __set_PRIMASK(uint32_t priMask); |
|
|
460 |
|
|
|
461 |
/** |
|
|
462 |
* @brief Return the Fault Mask value |
|
|
463 |
* |
|
|
464 |
* @param none |
|
|
465 |
* @return uint32_t FaultMask |
|
|
466 |
* |
|
|
467 |
* Return the content of the fault mask register |
|
|
468 |
*/ |
|
|
469 |
extern uint32_t __get_FAULTMASK(void); |
|
|
470 |
|
|
|
471 |
/** |
|
|
472 |
* @brief Set the Fault Mask value |
|
|
473 |
* |
|
|
474 |
* @param uint32_t faultMask value |
|
|
475 |
* @return none |
|
|
476 |
* |
|
|
477 |
* Set the fault mask register |
|
|
478 |
*/ |
|
|
479 |
extern void __set_FAULTMASK(uint32_t faultMask); |
|
|
480 |
|
|
|
481 |
/** |
|
|
482 |
* @brief Return the Control Register value |
|
|
483 |
* |
|
|
484 |
* @param none |
|
|
485 |
* @return uint32_t Control value |
|
|
486 |
* |
|
|
487 |
* Return the content of the control register |
|
|
488 |
*/ |
|
|
489 |
extern uint32_t __get_CONTROL(void); |
|
|
490 |
|
|
|
491 |
/** |
|
|
492 |
* @brief Set the Control Register value |
|
|
493 |
* |
|
|
494 |
* @param uint32_t Control value |
|
|
495 |
* @return none |
|
|
496 |
* |
|
|
497 |
* Set the control register |
|
|
498 |
*/ |
|
|
499 |
extern void __set_CONTROL(uint32_t control); |
|
|
500 |
|
|
|
501 |
#else /* (__ARMCC_VERSION >= 400000) */ |
|
|
502 |
|
|
|
503 |
|
|
|
504 |
/** |
|
|
505 |
* @brief Remove the exclusive lock created by ldrex |
|
|
506 |
* |
|
|
507 |
* @param none |
|
|
508 |
* @return none |
|
|
509 |
* |
|
|
510 |
* Removes the exclusive lock which is created by ldrex. |
|
|
511 |
*/ |
|
|
512 |
#define __CLREX __clrex |
|
|
513 |
|
|
|
514 |
/** |
|
|
515 |
* @brief Return the Base Priority value |
|
|
516 |
* |
|
|
517 |
* @param none |
|
|
518 |
* @return uint32_t BasePriority |
|
|
519 |
* |
|
|
520 |
* Return the content of the base priority register |
|
|
521 |
*/ |
|
|
522 |
static __INLINE uint32_t __get_BASEPRI(void) |
|
|
523 |
{ |
|
|
524 |
register uint32_t __regBasePri __ASM("basepri"); |
|
|
525 |
return(__regBasePri); |
|
|
526 |
} |
|
|
527 |
|
|
|
528 |
/** |
|
|
529 |
* @brief Set the Base Priority value |
|
|
530 |
* |
|
|
531 |
* @param uint32_t BasePriority |
|
|
532 |
* @return none |
|
|
533 |
* |
|
|
534 |
* Set the base priority register |
|
|
535 |
*/ |
|
|
536 |
static __INLINE void __set_BASEPRI(uint32_t basePri) |
|
|
537 |
{ |
|
|
538 |
register uint32_t __regBasePri __ASM("basepri"); |
|
|
539 |
__regBasePri = (basePri & 0x1ff); |
|
|
540 |
} |
|
|
541 |
|
|
|
542 |
/** |
|
|
543 |
* @brief Return the Priority Mask value |
|
|
544 |
* |
|
|
545 |
* @param none |
|
|
546 |
* @return uint32_t PriMask |
|
|
547 |
* |
|
|
548 |
* Return the state of the priority mask bit from the priority mask |
|
|
549 |
* register |
|
|
550 |
*/ |
|
|
551 |
static __INLINE uint32_t __get_PRIMASK(void) |
|
|
552 |
{ |
|
|
553 |
register uint32_t __regPriMask __ASM("primask"); |
|
|
554 |
return(__regPriMask); |
|
|
555 |
} |
|
|
556 |
|
|
|
557 |
/** |
|
|
558 |
* @brief Set the Priority Mask value |
|
|
559 |
* |
|
|
560 |
* @param uint32_t PriMask |
|
|
561 |
* @return none |
|
|
562 |
* |
|
|
563 |
* Set the priority mask bit in the priority mask register |
|
|
564 |
*/ |
|
|
565 |
static __INLINE void __set_PRIMASK(uint32_t priMask) |
|
|
566 |
{ |
|
|
567 |
register uint32_t __regPriMask __ASM("primask"); |
|
|
568 |
__regPriMask = (priMask); |
|
|
569 |
} |
|
|
570 |
|
|
|
571 |
/** |
|
|
572 |
* @brief Return the Fault Mask value |
|
|
573 |
* |
|
|
574 |
* @param none |
|
|
575 |
* @return uint32_t FaultMask |
|
|
576 |
* |
|
|
577 |
* Return the content of the fault mask register |
|
|
578 |
*/ |
|
|
579 |
static __INLINE uint32_t __get_FAULTMASK(void) |
|
|
580 |
{ |
|
|
581 |
register uint32_t __regFaultMask __ASM("faultmask"); |
|
|
582 |
return(__regFaultMask); |
|
|
583 |
} |
|
|
584 |
|
|
|
585 |
/** |
|
|
586 |
* @brief Set the Fault Mask value |
|
|
587 |
* |
|
|
588 |
* @param uint32_t faultMask value |
|
|
589 |
* @return none |
|
|
590 |
* |
|
|
591 |
* Set the fault mask register |
|
|
592 |
*/ |
|
|
593 |
static __INLINE void __set_FAULTMASK(uint32_t faultMask) |
|
|
594 |
{ |
|
|
595 |
register uint32_t __regFaultMask __ASM("faultmask"); |
|
|
596 |
__regFaultMask = (faultMask & 1); |
|
|
597 |
} |
|
|
598 |
|
|
|
599 |
/** |
|
|
600 |
* @brief Return the Control Register value |
|
|
601 |
* |
|
|
602 |
* @param none |
|
|
603 |
* @return uint32_t Control value |
|
|
604 |
* |
|
|
605 |
* Return the content of the control register |
|
|
606 |
*/ |
|
|
607 |
static __INLINE uint32_t __get_CONTROL(void) |
|
|
608 |
{ |
|
|
609 |
register uint32_t __regControl __ASM("control"); |
|
|
610 |
return(__regControl); |
|
|
611 |
} |
|
|
612 |
|
|
|
613 |
/** |
|
|
614 |
* @brief Set the Control Register value |
|
|
615 |
* |
|
|
616 |
* @param uint32_t Control value |
|
|
617 |
* @return none |
|
|
618 |
* |
|
|
619 |
* Set the control register |
|
|
620 |
*/ |
|
|
621 |
static __INLINE void __set_CONTROL(uint32_t control) |
|
|
622 |
{ |
|
|
623 |
register uint32_t __regControl __ASM("control"); |
|
|
624 |
__regControl = control; |
|
|
625 |
} |
|
|
626 |
|
|
|
627 |
#endif /* __ARMCC_VERSION */ |
|
|
628 |
|
|
|
629 |
|
|
|
630 |
|
|
|
631 |
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
|
|
632 |
/* IAR iccarm specific functions */ |
|
|
633 |
|
|
|
634 |
#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ |
|
|
635 |
#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ |
|
|
636 |
|
|
|
637 |
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } |
|
|
638 |
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } |
|
|
639 |
|
|
|
640 |
#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ |
|
|
641 |
static __INLINE void __WFI() { __ASM ("wfi"); } |
|
|
642 |
static __INLINE void __WFE() { __ASM ("wfe"); } |
|
|
643 |
static __INLINE void __SEV() { __ASM ("sev"); } |
|
|
644 |
static __INLINE void __CLREX() { __ASM ("clrex"); } |
|
|
645 |
|
|
|
646 |
/* intrinsic void __ISB(void) */ |
|
|
647 |
/* intrinsic void __DSB(void) */ |
|
|
648 |
/* intrinsic void __DMB(void) */ |
|
|
649 |
/* intrinsic void __set_PRIMASK(); */ |
|
|
650 |
/* intrinsic void __get_PRIMASK(); */ |
|
|
651 |
/* intrinsic void __set_FAULTMASK(); */ |
|
|
652 |
/* intrinsic void __get_FAULTMASK(); */ |
|
|
653 |
/* intrinsic uint32_t __REV(uint32_t value); */ |
|
|
654 |
/* intrinsic uint32_t __REVSH(uint32_t value); */ |
|
|
655 |
/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ |
|
|
656 |
/* intrinsic unsigned long __LDREX(unsigned long *); */ |
|
|
657 |
|
|
|
658 |
|
|
|
659 |
/** |
|
|
660 |
* @brief Return the Process Stack Pointer |
|
|
661 |
* |
|
|
662 |
* @param none |
|
|
663 |
* @return uint32_t ProcessStackPointer |
|
|
664 |
* |
|
|
665 |
* Return the actual process stack pointer |
|
|
666 |
*/ |
|
|
667 |
extern uint32_t __get_PSP(void); |
|
|
668 |
|
|
|
669 |
/** |
|
|
670 |
* @brief Set the Process Stack Pointer |
|
|
671 |
* |
|
|
672 |
* @param uint32_t Process Stack Pointer |
|
|
673 |
* @return none |
|
|
674 |
* |
|
|
675 |
* Assign the value ProcessStackPointer to the MSP |
|
|
676 |
* (process stack pointer) Cortex processor register |
|
|
677 |
*/ |
|
|
678 |
extern void __set_PSP(uint32_t topOfProcStack); |
|
|
679 |
|
|
|
680 |
/** |
|
|
681 |
* @brief Return the Main Stack Pointer |
|
|
682 |
* |
|
|
683 |
* @param none |
|
|
684 |
* @return uint32_t Main Stack Pointer |
|
|
685 |
* |
|
|
686 |
* Return the current value of the MSP (main stack pointer) |
|
|
687 |
* Cortex processor register |
|
|
688 |
*/ |
|
|
689 |
extern uint32_t __get_MSP(void); |
|
|
690 |
|
|
|
691 |
/** |
|
|
692 |
* @brief Set the Main Stack Pointer |
|
|
693 |
* |
|
|
694 |
* @param uint32_t Main Stack Pointer |
|
|
695 |
* @return none |
|
|
696 |
* |
|
|
697 |
* Assign the value mainStackPointer to the MSP |
|
|
698 |
* (main stack pointer) Cortex processor register |
|
|
699 |
*/ |
|
|
700 |
extern void __set_MSP(uint32_t topOfMainStack); |
|
|
701 |
|
|
|
702 |
/** |
|
|
703 |
* @brief Reverse byte order in unsigned short value |
|
|
704 |
* |
|
|
705 |
* @param uint16_t value to reverse |
|
|
706 |
* @return uint32_t reversed value |
|
|
707 |
* |
|
|
708 |
* Reverse byte order in unsigned short value |
|
|
709 |
*/ |
|
|
710 |
extern uint32_t __REV16(uint16_t value); |
|
|
711 |
|
|
|
712 |
/** |
|
|
713 |
* @brief Reverse bit order of value |
|
|
714 |
* |
|
|
715 |
* @param uint32_t value to reverse |
|
|
716 |
* @return uint32_t reversed value |
|
|
717 |
* |
|
|
718 |
* Reverse bit order of value |
|
|
719 |
*/ |
|
|
720 |
extern uint32_t __RBIT(uint32_t value); |
|
|
721 |
|
|
|
722 |
/** |
|
|
723 |
* @brief LDR Exclusive |
|
|
724 |
* |
|
|
725 |
* @param uint8_t* address |
|
|
726 |
* @return uint8_t value of (*address) |
|
|
727 |
* |
|
|
728 |
* Exclusive LDR command |
|
|
729 |
*/ |
|
|
730 |
extern uint8_t __LDREXB(uint8_t *addr); |
|
|
731 |
|
|
|
732 |
/** |
|
|
733 |
* @brief LDR Exclusive |
|
|
734 |
* |
|
|
735 |
* @param uint16_t* address |
|
|
736 |
* @return uint16_t value of (*address) |
|
|
737 |
* |
|
|
738 |
* Exclusive LDR command |
|
|
739 |
*/ |
|
|
740 |
extern uint16_t __LDREXH(uint16_t *addr); |
|
|
741 |
|
|
|
742 |
/** |
|
|
743 |
* @brief LDR Exclusive |
|
|
744 |
* |
|
|
745 |
* @param uint32_t* address |
|
|
746 |
* @return uint32_t value of (*address) |
|
|
747 |
* |
|
|
748 |
* Exclusive LDR command |
|
|
749 |
*/ |
|
|
750 |
extern uint32_t __LDREXW(uint32_t *addr); |
|
|
751 |
|
|
|
752 |
/** |
|
|
753 |
* @brief STR Exclusive |
|
|
754 |
* |
|
|
755 |
* @param uint8_t *address |
|
|
756 |
* @param uint8_t value to store |
|
|
757 |
* @return uint32_t successful / failed |
|
|
758 |
* |
|
|
759 |
* Exclusive STR command |
|
|
760 |
*/ |
|
|
761 |
extern uint32_t __STREXB(uint8_t value, uint8_t *addr); |
|
|
762 |
|
|
|
763 |
/** |
|
|
764 |
* @brief STR Exclusive |
|
|
765 |
* |
|
|
766 |
* @param uint16_t *address |
|
|
767 |
* @param uint16_t value to store |
|
|
768 |
* @return uint32_t successful / failed |
|
|
769 |
* |
|
|
770 |
* Exclusive STR command |
|
|
771 |
*/ |
|
|
772 |
extern uint32_t __STREXH(uint16_t value, uint16_t *addr); |
|
|
773 |
|
|
|
774 |
/** |
|
|
775 |
* @brief STR Exclusive |
|
|
776 |
* |
|
|
777 |
* @param uint32_t *address |
|
|
778 |
* @param uint32_t value to store |
|
|
779 |
* @return uint32_t successful / failed |
|
|
780 |
* |
|
|
781 |
* Exclusive STR command |
|
|
782 |
*/ |
|
|
783 |
extern uint32_t __STREXW(uint32_t value, uint32_t *addr); |
|
|
784 |
|
|
|
785 |
|
|
|
786 |
|
|
|
787 |
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
|
|
788 |
/* GNU gcc specific functions */ |
|
|
789 |
|
|
|
790 |
static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } |
|
|
791 |
static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } |
|
|
792 |
|
|
|
793 |
static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } |
|
|
794 |
static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } |
|
|
795 |
|
|
|
796 |
static __INLINE void __NOP() { __ASM volatile ("nop"); } |
|
|
797 |
static __INLINE void __WFI() { __ASM volatile ("wfi"); } |
|
|
798 |
static __INLINE void __WFE() { __ASM volatile ("wfe"); } |
|
|
799 |
static __INLINE void __SEV() { __ASM volatile ("sev"); } |
|
|
800 |
static __INLINE void __ISB() { __ASM volatile ("isb"); } |
|
|
801 |
static __INLINE void __DSB() { __ASM volatile ("dsb"); } |
|
|
802 |
static __INLINE void __DMB() { __ASM volatile ("dmb"); } |
|
|
803 |
static __INLINE void __CLREX() { __ASM volatile ("clrex"); } |
|
|
804 |
|
|
|
805 |
|
|
|
806 |
/** |
|
|
807 |
* @brief Return the Process Stack Pointer |
|
|
808 |
* |
|
|
809 |
* @param none |
|
|
810 |
* @return uint32_t ProcessStackPointer |
|
|
811 |
* |
|
|
812 |
* Return the actual process stack pointer |
|
|
813 |
*/ |
|
|
814 |
extern uint32_t __get_PSP(void); |
|
|
815 |
|
|
|
816 |
/** |
|
|
817 |
* @brief Set the Process Stack Pointer |
|
|
818 |
* |
|
|
819 |
* @param uint32_t Process Stack Pointer |
|
|
820 |
* @return none |
|
|
821 |
* |
|
|
822 |
* Assign the value ProcessStackPointer to the MSP |
|
|
823 |
* (process stack pointer) Cortex processor register |
|
|
824 |
*/ |
|
|
825 |
extern void __set_PSP(uint32_t topOfProcStack); |
|
|
826 |
|
|
|
827 |
/** |
|
|
828 |
* @brief Return the Main Stack Pointer |
|
|
829 |
* |
|
|
830 |
* @param none |
|
|
831 |
* @return uint32_t Main Stack Pointer |
|
|
832 |
* |
|
|
833 |
* Return the current value of the MSP (main stack pointer) |
|
|
834 |
* Cortex processor register |
|
|
835 |
*/ |
|
|
836 |
extern uint32_t __get_MSP(void); |
|
|
837 |
|
|
|
838 |
/** |
|
|
839 |
* @brief Set the Main Stack Pointer |
|
|
840 |
* |
|
|
841 |
* @param uint32_t Main Stack Pointer |
|
|
842 |
* @return none |
|
|
843 |
* |
|
|
844 |
* Assign the value mainStackPointer to the MSP |
|
|
845 |
* (main stack pointer) Cortex processor register |
|
|
846 |
*/ |
|
|
847 |
extern void __set_MSP(uint32_t topOfMainStack); |
|
|
848 |
|
|
|
849 |
/** |
|
|
850 |
* @brief Return the Base Priority value |
|
|
851 |
* |
|
|
852 |
* @param none |
|
|
853 |
* @return uint32_t BasePriority |
|
|
854 |
* |
|
|
855 |
* Return the content of the base priority register |
|
|
856 |
*/ |
|
|
857 |
extern uint32_t __get_BASEPRI(void); |
|
|
858 |
|
|
|
859 |
/** |
|
|
860 |
* @brief Set the Base Priority value |
|
|
861 |
* |
|
|
862 |
* @param uint32_t BasePriority |
|
|
863 |
* @return none |
|
|
864 |
* |
|
|
865 |
* Set the base priority register |
|
|
866 |
*/ |
|
|
867 |
extern void __set_BASEPRI(uint32_t basePri); |
|
|
868 |
|
|
|
869 |
/** |
|
|
870 |
* @brief Return the Priority Mask value |
|
|
871 |
* |
|
|
872 |
* @param none |
|
|
873 |
* @return uint32_t PriMask |
|
|
874 |
* |
|
|
875 |
* Return the state of the priority mask bit from the priority mask |
|
|
876 |
* register |
|
|
877 |
*/ |
|
|
878 |
extern uint32_t __get_PRIMASK(void); |
|
|
879 |
|
|
|
880 |
/** |
|
|
881 |
* @brief Set the Priority Mask value |
|
|
882 |
* |
|
|
883 |
* @param uint32_t PriMask |
|
|
884 |
* @return none |
|
|
885 |
* |
|
|
886 |
* Set the priority mask bit in the priority mask register |
|
|
887 |
*/ |
|
|
888 |
extern void __set_PRIMASK(uint32_t priMask); |
|
|
889 |
|
|
|
890 |
/** |
|
|
891 |
* @brief Return the Fault Mask value |
|
|
892 |
* |
|
|
893 |
* @param none |
|
|
894 |
* @return uint32_t FaultMask |
|
|
895 |
* |
|
|
896 |
* Return the content of the fault mask register |
|
|
897 |
*/ |
|
|
898 |
extern uint32_t __get_FAULTMASK(void); |
|
|
899 |
|
|
|
900 |
/** |
|
|
901 |
* @brief Set the Fault Mask value |
|
|
902 |
* |
|
|
903 |
* @param uint32_t faultMask value |
|
|
904 |
* @return none |
|
|
905 |
* |
|
|
906 |
* Set the fault mask register |
|
|
907 |
*/ |
|
|
908 |
extern void __set_FAULTMASK(uint32_t faultMask); |
|
|
909 |
|
|
|
910 |
/** |
|
|
911 |
* @brief Return the Control Register value |
|
|
912 |
* |
|
|
913 |
* @param none |
|
|
914 |
* @return uint32_t Control value |
|
|
915 |
* |
|
|
916 |
* Return the content of the control register |
|
|
917 |
*/ |
|
|
918 |
extern uint32_t __get_CONTROL(void); |
|
|
919 |
|
|
|
920 |
/** |
|
|
921 |
* @brief Set the Control Register value |
|
|
922 |
* |
|
|
923 |
* @param uint32_t Control value |
|
|
924 |
* @return none |
|
|
925 |
* |
|
|
926 |
* Set the control register |
|
|
927 |
*/ |
|
|
928 |
extern void __set_CONTROL(uint32_t control); |
|
|
929 |
|
|
|
930 |
/** |
|
|
931 |
* @brief Reverse byte order in integer value |
|
|
932 |
* |
|
|
933 |
* @param uint32_t value to reverse |
|
|
934 |
* @return uint32_t reversed value |
|
|
935 |
* |
|
|
936 |
* Reverse byte order in integer value |
|
|
937 |
*/ |
|
|
938 |
extern uint32_t __REV(uint32_t value); |
|
|
939 |
|
|
|
940 |
/** |
|
|
941 |
* @brief Reverse byte order in unsigned short value |
|
|
942 |
* |
|
|
943 |
* @param uint16_t value to reverse |
|
|
944 |
* @return uint32_t reversed value |
|
|
945 |
* |
|
|
946 |
* Reverse byte order in unsigned short value |
|
|
947 |
*/ |
|
|
948 |
extern uint32_t __REV16(uint16_t value); |
|
|
949 |
|
|
|
950 |
/* |
|
|
951 |
* Reverse byte order in signed short value with sign extension to integer |
|
|
952 |
* |
|
|
953 |
* @param int16_t value to reverse |
|
|
954 |
* @return int32_t reversed value |
|
|
955 |
* |
|
|
956 |
* @brief Reverse byte order in signed short value with sign extension to integer |
|
|
957 |
*/ |
|
|
958 |
extern int32_t __REVSH(int16_t value); |
|
|
959 |
|
|
|
960 |
/** |
|
|
961 |
* @brief Reverse bit order of value |
|
|
962 |
* |
|
|
963 |
* @param uint32_t value to reverse |
|
|
964 |
* @return uint32_t reversed value |
|
|
965 |
* |
|
|
966 |
* Reverse bit order of value |
|
|
967 |
*/ |
|
|
968 |
extern uint32_t __RBIT(uint32_t value); |
|
|
969 |
|
|
|
970 |
/** |
|
|
971 |
* @brief LDR Exclusive |
|
|
972 |
* |
|
|
973 |
* @param uint8_t* address |
|
|
974 |
* @return uint8_t value of (*address) |
|
|
975 |
* |
|
|
976 |
* Exclusive LDR command |
|
|
977 |
*/ |
|
|
978 |
extern uint8_t __LDREXB(uint8_t *addr); |
|
|
979 |
|
|
|
980 |
/** |
|
|
981 |
* @brief LDR Exclusive |
|
|
982 |
* |
|
|
983 |
* @param uint16_t* address |
|
|
984 |
* @return uint16_t value of (*address) |
|
|
985 |
* |
|
|
986 |
* Exclusive LDR command |
|
|
987 |
*/ |
|
|
988 |
extern uint16_t __LDREXH(uint16_t *addr); |
|
|
989 |
|
|
|
990 |
/** |
|
|
991 |
* @brief LDR Exclusive |
|
|
992 |
* |
|
|
993 |
* @param uint32_t* address |
|
|
994 |
* @return uint32_t value of (*address) |
|
|
995 |
* |
|
|
996 |
* Exclusive LDR command |
|
|
997 |
*/ |
|
|
998 |
extern uint32_t __LDREXW(uint32_t *addr); |
|
|
999 |
|
|
|
1000 |
/** |
|
|
1001 |
* @brief STR Exclusive |
|
|
1002 |
* |
|
|
1003 |
* @param uint8_t *address |
|
|
1004 |
* @param uint8_t value to store |
|
|
1005 |
* @return uint32_t successful / failed |
|
|
1006 |
* |
|
|
1007 |
* Exclusive STR command |
|
|
1008 |
*/ |
|
|
1009 |
extern uint32_t __STREXB(uint8_t value, uint8_t *addr); |
|
|
1010 |
|
|
|
1011 |
/** |
|
|
1012 |
* @brief STR Exclusive |
|
|
1013 |
* |
|
|
1014 |
* @param uint16_t *address |
|
|
1015 |
* @param uint16_t value to store |
|
|
1016 |
* @return uint32_t successful / failed |
|
|
1017 |
* |
|
|
1018 |
* Exclusive STR command |
|
|
1019 |
*/ |
|
|
1020 |
extern uint32_t __STREXH(uint16_t value, uint16_t *addr); |
|
|
1021 |
|
|
|
1022 |
/** |
|
|
1023 |
* @brief STR Exclusive |
|
|
1024 |
* |
|
|
1025 |
* @param uint32_t *address |
|
|
1026 |
* @param uint32_t value to store |
|
|
1027 |
* @return uint32_t successful / failed |
|
|
1028 |
* |
|
|
1029 |
* Exclusive STR command |
|
|
1030 |
*/ |
|
|
1031 |
extern uint32_t __STREXW(uint32_t value, uint32_t *addr); |
|
|
1032 |
|
|
|
1033 |
|
|
|
1034 |
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
|
|
1035 |
/* TASKING carm specific functions */ |
|
|
1036 |
|
|
|
1037 |
/* |
|
|
1038 |
* The CMSIS functions have been implemented as intrinsics in the compiler. |
|
|
1039 |
* Please use "carm -?i" to get an up to date list of all instrinsics, |
|
|
1040 |
* Including the CMSIS ones. |
|
|
1041 |
*/ |
|
|
1042 |
|
|
|
1043 |
#endif |
|
|
1044 |
|
|
|
1045 |
|
|
|
1046 |
|
|
|
1047 |
/* ########################## NVIC functions #################################### */ |
|
|
1048 |
|
|
|
1049 |
|
|
|
1050 |
/** |
|
|
1051 |
* @brief Set the Priority Grouping in NVIC Interrupt Controller |
|
|
1052 |
* |
|
|
1053 |
* @param uint32_t priority_grouping is priority grouping field |
|
|
1054 |
* @return none |
|
|
1055 |
* |
|
|
1056 |
* Set the priority grouping field using the required unlock sequence. |
|
|
1057 |
* The parameter priority_grouping is assigned to the field |
|
|
1058 |
* SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. |
|
|
1059 |
* In case of a conflict between priority grouping and available |
|
|
1060 |
* priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
|
|
1061 |
*/ |
|
|
1062 |
static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
|
|
1063 |
{ |
|
|
1064 |
uint32_t reg_value; |
|
|
1065 |
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
|
|
1066 |
|
|
|
1067 |
reg_value = SCB->AIRCR; /* read old register configuration */ |
|
|
1068 |
reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ |
|
|
1069 |
reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */ |
|
|
1070 |
SCB->AIRCR = reg_value; |
|
|
1071 |
} |
|
|
1072 |
|
|
|
1073 |
/** |
|
|
1074 |
* @brief Get the Priority Grouping from NVIC Interrupt Controller |
|
|
1075 |
* |
|
|
1076 |
* @param none |
|
|
1077 |
* @return uint32_t priority grouping field |
|
|
1078 |
* |
|
|
1079 |
* Get the priority grouping from NVIC Interrupt Controller. |
|
|
1080 |
* priority grouping is SCB->AIRCR [10:8] PRIGROUP field. |
|
|
1081 |
*/ |
|
|
1082 |
static __INLINE uint32_t NVIC_GetPriorityGrouping(void) |
|
|
1083 |
{ |
|
|
1084 |
return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */ |
|
|
1085 |
} |
|
|
1086 |
|
|
|
1087 |
/** |
|
|
1088 |
* @brief Enable Interrupt in NVIC Interrupt Controller |
|
|
1089 |
* |
|
|
1090 |
* @param IRQn_Type IRQn specifies the interrupt number |
|
|
1091 |
* @return none |
|
|
1092 |
* |
|
|
1093 |
* Enable a device specific interupt in the NVIC interrupt controller. |
|
|
1094 |
* The interrupt number cannot be a negative value. |
|
|
1095 |
*/ |
|
|
1096 |
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
|
|
1097 |
{ |
|
|
1098 |
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ |
|
|
1099 |
} |
|
|
1100 |
|
|
|
1101 |
/** |
|
|
1102 |
* @brief Disable the interrupt line for external interrupt specified |
|
|
1103 |
* |
|
|
1104 |
* @param IRQn_Type IRQn is the positive number of the external interrupt |
|
|
1105 |
* @return none |
|
|
1106 |
* |
|
|
1107 |
* Disable a device specific interupt in the NVIC interrupt controller. |
|
|
1108 |
* The interrupt number cannot be a negative value. |
|
|
1109 |
*/ |
|
|
1110 |
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
|
|
1111 |
{ |
|
|
1112 |
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ |
|
|
1113 |
} |
|
|
1114 |
|
|
|
1115 |
/** |
|
|
1116 |
* @brief Read the interrupt pending bit for a device specific interrupt source |
|
|
1117 |
* |
|
|
1118 |
* @param IRQn_Type IRQn is the number of the device specifc interrupt |
|
|
1119 |
* @return uint32_t 1 if pending interrupt else 0 |
|
|
1120 |
* |
|
|
1121 |
* Read the pending register in NVIC and return 1 if its status is pending, |
|
|
1122 |
* otherwise it returns 0 |
|
|
1123 |
*/ |
|
|
1124 |
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
|
|
1125 |
{ |
|
|
1126 |
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ |
|
|
1127 |
} |
|
|
1128 |
|
|
|
1129 |
/** |
|
|
1130 |
* @brief Set the pending bit for an external interrupt |
|
|
1131 |
* |
|
|
1132 |
* @param IRQn_Type IRQn is the Number of the interrupt |
|
|
1133 |
* @return none |
|
|
1134 |
* |
|
|
1135 |
* Set the pending bit for the specified interrupt. |
|
|
1136 |
* The interrupt number cannot be a negative value. |
|
|
1137 |
*/ |
|
|
1138 |
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
|
|
1139 |
{ |
|
|
1140 |
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ |
|
|
1141 |
} |
|
|
1142 |
|
|
|
1143 |
/** |
|
|
1144 |
* @brief Clear the pending bit for an external interrupt |
|
|
1145 |
* |
|
|
1146 |
* @param IRQn_Type IRQn is the Number of the interrupt |
|
|
1147 |
* @return none |
|
|
1148 |
* |
|
|
1149 |
* Clear the pending bit for the specified interrupt. |
|
|
1150 |
* The interrupt number cannot be a negative value. |
|
|
1151 |
*/ |
|
|
1152 |
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
|
|
1153 |
{ |
|
|
1154 |
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
|
|
1155 |
} |
|
|
1156 |
|
|
|
1157 |
/** |
|
|
1158 |
* @brief Read the active bit for an external interrupt |
|
|
1159 |
* |
|
|
1160 |
* @param IRQn_Type IRQn is the Number of the interrupt |
|
|
1161 |
* @return uint32_t 1 if active else 0 |
|
|
1162 |
* |
|
|
1163 |
* Read the active register in NVIC and returns 1 if its status is active, |
|
|
1164 |
* otherwise it returns 0. |
|
|
1165 |
*/ |
|
|
1166 |
static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) |
|
|
1167 |
{ |
|
|
1168 |
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ |
|
|
1169 |
} |
|
|
1170 |
|
|
|
1171 |
/** |
|
|
1172 |
* @brief Set the priority for an interrupt |
|
|
1173 |
* |
|
|
1174 |
* @param IRQn_Type IRQn is the Number of the interrupt |
|
|
1175 |
* @param priority is the priority for the interrupt |
|
|
1176 |
* @return none |
|
|
1177 |
* |
|
|
1178 |
* Set the priority for the specified interrupt. The interrupt |
|
|
1179 |
* number can be positive to specify an external (device specific) |
|
|
1180 |
* interrupt, or negative to specify an internal (core) interrupt. \n |
|
|
1181 |
* |
|
|
1182 |
* Note: The priority cannot be set for every core interrupt. |
|
|
1183 |
*/ |
|
|
1184 |
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
|
|
1185 |
{ |
|
|
1186 |
if(IRQn < 0) { |
|
|
1187 |
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ |
|
|
1188 |
else { |
|
|
1189 |
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ |
|
|
1190 |
} |
|
|
1191 |
|
|
|
1192 |
/** |
|
|
1193 |
* @brief Read the priority for an interrupt |
|
|
1194 |
* |
|
|
1195 |
* @param IRQn_Type IRQn is the Number of the interrupt |
|
|
1196 |
* @return uint32_t priority is the priority for the interrupt |
|
|
1197 |
* |
|
|
1198 |
* Read the priority for the specified interrupt. The interrupt |
|
|
1199 |
* number can be positive to specify an external (device specific) |
|
|
1200 |
* interrupt, or negative to specify an internal (core) interrupt. |
|
|
1201 |
* |
|
|
1202 |
* The returned priority value is automatically aligned to the implemented |
|
|
1203 |
* priority bits of the microcontroller. |
|
|
1204 |
* |
|
|
1205 |
* Note: The priority cannot be set for every core interrupt. |
|
|
1206 |
*/ |
|
|
1207 |
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
|
|
1208 |
{ |
|
|
1209 |
|
|
|
1210 |
if(IRQn < 0) { |
|
|
1211 |
return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ |
|
|
1212 |
else { |
|
|
1213 |
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
|
|
1214 |
} |
|
|
1215 |
|
|
|
1216 |
|
|
|
1217 |
/** |
|
|
1218 |
* @brief Encode the priority for an interrupt |
|
|
1219 |
* |
|
|
1220 |
* @param uint32_t PriorityGroup is the used priority group |
|
|
1221 |
* @param uint32_t PreemptPriority is the preemptive priority value (starting from 0) |
|
|
1222 |
* @param uint32_t SubPriority is the sub priority value (starting from 0) |
|
|
1223 |
* @return uint32_t the priority for the interrupt |
|
|
1224 |
* |
|
|
1225 |
* Encode the priority for an interrupt with the given priority group, |
|
|
1226 |
* preemptive priority value and sub priority value. |
|
|
1227 |
* In case of a conflict between priority grouping and available |
|
|
1228 |
* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. |
|
|
1229 |
* |
|
|
1230 |
* The returned priority value can be used for NVIC_SetPriority(...) function |
|
|
1231 |
*/ |
|
|
1232 |
static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
|
|
1233 |
{ |
|
|
1234 |
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
|
|
1235 |
uint32_t PreemptPriorityBits; |
|
|
1236 |
uint32_t SubPriorityBits; |
|
|
1237 |
|
|
|
1238 |
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
|
|
1239 |
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
|
|
1240 |
|
|
|
1241 |
return ( |
|
|
1242 |
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | |
|
|
1243 |
((SubPriority & ((1 << (SubPriorityBits )) - 1))) |
|
|
1244 |
); |
|
|
1245 |
} |
|
|
1246 |
|
|
|
1247 |
|
|
|
1248 |
/** |
|
|
1249 |
* @brief Decode the priority of an interrupt |
|
|
1250 |
* |
|
|
1251 |
* @param uint32_t Priority the priority for the interrupt |
|
|
1252 |
* @param uint32_t PrioGroup is the used priority group |
|
|
1253 |
* @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0) |
|
|
1254 |
* @param uint32_t* pSubPrio is the sub priority value (starting from 0) |
|
|
1255 |
* @return none |
|
|
1256 |
* |
|
|
1257 |
* Decode an interrupt priority value with the given priority group to |
|
|
1258 |
* preemptive priority value and sub priority value. |
|
|
1259 |
* In case of a conflict between priority grouping and available |
|
|
1260 |
* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. |
|
|
1261 |
* |
|
|
1262 |
* The priority value can be retrieved with NVIC_GetPriority(...) function |
|
|
1263 |
*/ |
|
|
1264 |
static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
|
|
1265 |
{ |
|
|
1266 |
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
|
|
1267 |
uint32_t PreemptPriorityBits; |
|
|
1268 |
uint32_t SubPriorityBits; |
|
|
1269 |
|
|
|
1270 |
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
|
|
1271 |
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
|
|
1272 |
|
|
|
1273 |
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); |
|
|
1274 |
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); |
|
|
1275 |
} |
|
|
1276 |
|
|
|
1277 |
|
|
|
1278 |
|
|
|
1279 |
/* ################################## SysTick function ############################################ */ |
|
|
1280 |
|
|
|
1281 |
#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) |
|
|
1282 |
|
|
|
1283 |
/* SysTick constants */ |
|
|
1284 |
#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ |
|
|
1285 |
#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ |
|
|
1286 |
#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ |
|
|
1287 |
#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ |
|
|
1288 |
|
|
|
1289 |
/** |
|
|
1290 |
* @brief Initialize and start the SysTick counter and its interrupt. |
|
|
1291 |
* |
|
|
1292 |
* @param uint32_t ticks is the number of ticks between two interrupts |
|
|
1293 |
* @return none |
|
|
1294 |
* |
|
|
1295 |
* Initialise the system tick timer and its interrupt and start the |
|
|
1296 |
* system tick timer / counter in free running mode to generate |
|
|
1297 |
* periodical interrupts. |
|
|
1298 |
*/ |
|
|
1299 |
static __INLINE uint32_t SysTick_Config(uint32_t ticks) |
|
|
1300 |
{ |
|
|
1301 |
if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ |
|
|
1302 |
|
|
|
1303 |
SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ |
|
|
1304 |
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ |
|
|
1305 |
SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ |
|
|
1306 |
SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */ |
|
|
1307 |
return (0); /* Function successful */ |
|
|
1308 |
} |
|
|
1309 |
|
|
|
1310 |
#endif |
|
|
1311 |
|
|
|
1312 |
|
|
|
1313 |
|
|
|
1314 |
|
|
|
1315 |
|
|
|
1316 |
/* ################################## Reset function ############################################ */ |
|
|
1317 |
|
|
|
1318 |
/** |
|
|
1319 |
* @brief Initiate a system reset request. |
|
|
1320 |
* |
|
|
1321 |
* @param none |
|
|
1322 |
* @return none |
|
|
1323 |
* |
|
|
1324 |
* Initialize a system reset request to reset the MCU |
|
|
1325 |
*/ |
|
|
1326 |
static __INLINE void NVIC_SystemReset(void) |
|
|
1327 |
{ |
|
|
1328 |
SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */ |
|
|
1329 |
__DSB(); /* Ensure completion of memory access */ |
|
|
1330 |
while(1); /* wait until reset */ |
|
|
1331 |
} |
|
|
1332 |
|
|
|
1333 |
|
|
|
1334 |
/* ################################## Debug Output function ############################################ */ |
|
|
1335 |
|
|
|
1336 |
|
|
|
1337 |
/** |
|
|
1338 |
* @brief Outputs a character via the ITM channel 0 |
|
|
1339 |
* |
|
|
1340 |
* @param uint32_t character to output |
|
|
1341 |
* @return uint32_t input character |
|
|
1342 |
* |
|
|
1343 |
* The function outputs a character via the ITM channel 0. |
|
|
1344 |
* The function returns when no debugger is connected that has booked the output. |
|
|
1345 |
* It is blocking when a debugger is connected, but the previous character send is not transmitted. |
|
|
1346 |
*/ |
|
|
1347 |
static __INLINE uint32_t ITM_SendChar (uint32_t ch) |
|
|
1348 |
{ |
|
|
1349 |
if (ch == '\n') ITM_SendChar('\r'); |
|
|
1350 |
|
|
|
1351 |
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && |
|
|
1352 |
(ITM->TCR & ITM_TCR_ITMENA) && |
|
|
1353 |
(ITM->TER & (1UL << 0)) ) |
|
|
1354 |
{ |
|
|
1355 |
while (ITM->PORT[0].u32 == 0); |
|
|
1356 |
ITM->PORT[0].u8 = (uint8_t) ch; |
|
|
1357 |
} |
|
|
1358 |
return (ch); |
|
|
1359 |
} |
|
|
1360 |
|
|
|
1361 |
#ifdef __cplusplus |
|
|
1362 |
} |
|
|
1363 |
#endif |
|
|
1364 |
|
|
|
1365 |
#endif /* __CM3_CORE_H__ */ |
|
|
1366 |
|
|
|
1367 |
/*lint -restore */ |