Rev Author Line No. Line
3328 povik 1 /**
2 ******************************************************************************
3 * @file startup_stm32f10x_cl.s
4 * @author MCD Application Team
5 * @version V3.1.2
6 * @date 09/28/2009
7 * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
8 * This module performs:
9 * - Set the initial SP
10 * - Set the initial PC == Reset_Handler,
11 * - Set the vector table entries with the exceptions ISR
12 * address.
13 * - Branches to main in the C library (which eventually
14 * calls main()).
15 * After Reset the Cortex-M3 processor is in Thread mode,
16 * priority is Privileged, and the Stack is set to Main.
17 *******************************************************************************
18 * @copy
19 *
20 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
21 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
22 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
23 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
24 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
25 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
26 *
27 * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
28 */
29  
30 .syntax unified
31 .cpu cortex-m3
32 .fpu softvfp
33 .thumb
34  
35 .global g_pfnVectors
36 .global Default_Handler
37  
38 /* start address for the initialization values of the .data section.
39 defined in linker script */
40 .word _sidata
41 /* start address for the .data section. defined in linker script */
42 .word _sdata
43 /* end address for the .data section. defined in linker script */
44 .word _edata
45 /* start address for the .bss section. defined in linker script */
46 .word _sbss
47 /* end address for the .bss section. defined in linker script */
48 .word _ebss
49  
50 .equ BootRAM, 0xF1E0F85F
51 /**
52 * @brief This is the code that gets called when the processor first
53 * starts execution following a reset event. Only the absolutely
54 * necessary set is performed, after which the application
55 * supplied main() routine is called.
56 * @param None
57 * @retval : None
58 */
59  
60 .section .text.Reset_Handler
61 .weak Reset_Handler
62 .type Reset_Handler, %function
63 Reset_Handler:
64  
65 /* Copy the data segment initializers from flash to SRAM */
66 movs r1, #0
67 b LoopCopyDataInit
68  
69 CopyDataInit:
70 ldr r3, =_sidata
71 ldr r3, [r3, r1]
72 str r3, [r0, r1]
73 adds r1, r1, #4
74  
75 LoopCopyDataInit:
76 ldr r0, =_sdata
77 ldr r3, =_edata
78 adds r2, r0, r1
79 cmp r2, r3
80 bcc CopyDataInit
81 ldr r2, =_sbss
82 b LoopFillZerobss
83  
84 /* Zero fill the bss segment. */
85 FillZerobss:
86 movs r3, #0
87 str r3, [r2], #4
88  
89 LoopFillZerobss:
90 ldr r3, = _ebss
91 cmp r2, r3
92 bcc FillZerobss
93 /* Call the application's entry point.*/
94 bl main
95 bx lr
96 .size Reset_Handler, .-Reset_Handler
97  
98 /**
99 * @brief This is the code that gets called when the processor receives an
100 * unexpected interrupt. This simply enters an infinite loop, preserving
101 * the system state for examination by a debugger.
102 *
103 * @param None
104 * @retval : None
105 */
106 .section .text.Default_Handler,"ax",%progbits
107 Default_Handler:
108 Infinite_Loop:
109 b Infinite_Loop
110 .size Default_Handler, .-Default_Handler
111  
112 /******************************************************************************
113 *
114 * The minimal vector table for a Cortex M3. Note that the proper constructs
115 * must be placed on this to ensure that it ends up at physical address
116 * 0x0000.0000.
117 *
118 ******************************************************************************/
119 .section .isr_vector,"a",%progbits
120 .type g_pfnVectors, %object
121 .size g_pfnVectors, .-g_pfnVectors
122  
123  
124 g_pfnVectors:
125 .word _estack
126 .word Reset_Handler
127 .word NMI_Handler
128 .word HardFault_Handler
129 .word MemManage_Handler
130 .word BusFault_Handler
131 .word UsageFault_Handler
132 .word 0
133 .word 0
134 .word 0
135 .word 0
136 .word SVC_Handler
137 .word DebugMon_Handler
138 .word 0
139 .word PendSV_Handler
140 .word SysTick_Handler
141 .word WWDG_IRQHandler
142 .word PVD_IRQHandler
143 .word TAMPER_IRQHandler
144 .word RTC_IRQHandler
145 .word FLASH_IRQHandler
146 .word RCC_IRQHandler
147 .word EXTI0_IRQHandler
148 .word EXTI1_IRQHandler
149 .word EXTI2_IRQHandler
150 .word EXTI3_IRQHandler
151 .word EXTI4_IRQHandler
152 .word DMA1_Channel1_IRQHandler
153 .word DMA1_Channel2_IRQHandler
154 .word DMA1_Channel3_IRQHandler
155 .word DMA1_Channel4_IRQHandler
156 .word DMA1_Channel5_IRQHandler
157 .word DMA1_Channel6_IRQHandler
158 .word DMA1_Channel7_IRQHandler
159 .word ADC1_2_IRQHandler
160 .word CAN1_TX_IRQHandler
161 .word CAN1_RX0_IRQHandler
162 .word CAN1_RX1_IRQHandler
163 .word CAN1_SCE_IRQHandler
164 .word EXTI9_5_IRQHandler
165 .word TIM1_BRK_IRQHandler
166 .word TIM1_UP_IRQHandler
167 .word TIM1_TRG_COM_IRQHandler
168 .word TIM1_CC_IRQHandler
169 .word TIM2_IRQHandler
170 .word TIM3_IRQHandler
171 .word TIM4_IRQHandler
172 .word I2C1_EV_IRQHandler
173 .word I2C1_ER_IRQHandler
174 .word I2C2_EV_IRQHandler
175 .word I2C2_ER_IRQHandler
176 .word SPI1_IRQHandler
177 .word SPI2_IRQHandler
178 .word USART1_IRQHandler
179 .word USART2_IRQHandler
180 .word USART3_IRQHandler
181 .word EXTI15_10_IRQHandler
182 .word RTCAlarm_IRQHandler
183 .word OTG_FS_WKUP_IRQHandler
184 .word 0
185 .word 0
186 .word 0
187 .word 0
188 .word 0
189 .word 0
190 .word 0
191 .word TIM5_IRQHandler
192 .word SPI3_IRQHandler
193 .word UART4_IRQHandler
194 .word UART5_IRQHandler
195 .word TIM6_IRQHandler
196 .word TIM7_IRQHandler
197 .word DMA2_Channel1_IRQHandler
198 .word DMA2_Channel2_IRQHandler
199 .word DMA2_Channel3_IRQHandler
200 .word DMA2_Channel4_IRQHandler
201 .word DMA2_Channel5_IRQHandler
202 .word ETH_IRQHandler
203 .word ETH_WKUP_IRQHandler
204 .word CAN2_TX_IRQHandler
205 .word CAN2_RX0_IRQHandler
206 .word CAN2_RX1_IRQHandler
207 .word CAN2_SCE_IRQHandler
208 .word OTG_FS_IRQHandler
209 .word 0
210 .word 0
211 .word 0
212 .word 0
213 .word 0
214 .word 0
215 .word 0
216 .word 0
217 .word 0
218 .word 0
219 .word 0
220 .word 0
221 .word 0
222 .word 0
223 .word 0
224 .word 0
225 .word 0
226 .word 0
227 .word 0
228 .word 0
229 .word 0
230 .word 0
231 .word 0
232 .word 0
233 .word 0
234 .word 0
235 .word 0
236 .word 0
237 .word 0
238 .word 0
239 .word 0
240 .word 0
241 .word 0
242 .word 0
243 .word 0
244 .word 0
245 .word BootRAM /* @0x1E0. This is for boot in RAM mode for
246 STM32F10x Connectivity line Devices. */
247  
248 /*******************************************************************************
249 *
250 * Provide weak aliases for each Exception handler to the Default_Handler.
251 * As they are weak aliases, any function with the same name will override
252 * this definition.
253 *
254 *******************************************************************************/
255 .weak NMI_Handler
256 .thumb_set NMI_Handler,Default_Handler
257  
258 .weak HardFault_Handler
259 .thumb_set HardFault_Handler,Default_Handler
260  
261 .weak MemManage_Handler
262 .thumb_set MemManage_Handler,Default_Handler
263  
264 .weak BusFault_Handler
265 .thumb_set BusFault_Handler,Default_Handler
266  
267 .weak UsageFault_Handler
268 .thumb_set UsageFault_Handler,Default_Handler
269  
270 .weak SVC_Handler
271 .thumb_set SVC_Handler,Default_Handler
272  
273 .weak DebugMon_Handler
274 .thumb_set DebugMon_Handler,Default_Handler
275  
276 .weak PendSV_Handler
277 .thumb_set PendSV_Handler,Default_Handler
278  
279 .weak SysTick_Handler
280 .thumb_set SysTick_Handler,Default_Handler
281  
282 .weak WWDG_IRQHandler
283 .thumb_set WWDG_IRQHandler,Default_Handler
284  
285 .weak PVD_IRQHandler
286 .thumb_set PVD_IRQHandler,Default_Handler
287  
288 .weak TAMPER_IRQHandler
289 .thumb_set TAMPER_IRQHandler,Default_Handler
290  
291 .weak RTC_IRQHandler
292 .thumb_set RTC_IRQHandler,Default_Handler
293  
294 .weak FLASH_IRQHandler
295 .thumb_set FLASH_IRQHandler,Default_Handler
296  
297 .weak RCC_IRQHandler
298 .thumb_set RCC_IRQHandler,Default_Handler
299  
300 .weak EXTI0_IRQHandler
301 .thumb_set EXTI0_IRQHandler,Default_Handler
302  
303 .weak EXTI1_IRQHandler
304 .thumb_set EXTI1_IRQHandler,Default_Handler
305  
306 .weak EXTI2_IRQHandler
307 .thumb_set EXTI2_IRQHandler,Default_Handler
308  
309 .weak EXTI3_IRQHandler
310 .thumb_set EXTI3_IRQHandler,Default_Handler
311  
312 .weak EXTI4_IRQHandler
313 .thumb_set EXTI4_IRQHandler,Default_Handler
314  
315 .weak DMA1_Channel1_IRQHandler
316 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
317  
318 .weak DMA1_Channel2_IRQHandler
319 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
320  
321 .weak DMA1_Channel3_IRQHandler
322 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
323  
324 .weak DMA1_Channel4_IRQHandler
325 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
326  
327 .weak DMA1_Channel5_IRQHandler
328 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
329  
330 .weak DMA1_Channel6_IRQHandler
331 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
332  
333 .weak DMA1_Channel7_IRQHandler
334 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
335  
336 .weak ADC1_2_IRQHandler
337 .thumb_set ADC1_2_IRQHandler,Default_Handler
338  
339 .weak CAN1_TX_IRQHandler
340 .thumb_set CAN1_TX_IRQHandler,Default_Handler
341  
342 .weak CAN1_RX0_IRQHandler
343 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
344  
345 .weak CAN1_RX1_IRQHandler
346 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
347  
348 .weak CAN1_SCE_IRQHandler
349 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
350  
351 .weak EXTI9_5_IRQHandler
352 .thumb_set EXTI9_5_IRQHandler,Default_Handler
353  
354 .weak TIM1_BRK_IRQHandler
355 .thumb_set TIM1_BRK_IRQHandler,Default_Handler
356  
357 .weak TIM1_UP_IRQHandler
358 .thumb_set TIM1_UP_IRQHandler,Default_Handler
359  
360 .weak TIM1_TRG_COM_IRQHandler
361 .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
362  
363 .weak TIM1_CC_IRQHandler
364 .thumb_set TIM1_CC_IRQHandler,Default_Handler
365  
366 .weak TIM2_IRQHandler
367 .thumb_set TIM2_IRQHandler,Default_Handler
368  
369 .weak TIM3_IRQHandler
370 .thumb_set TIM3_IRQHandler,Default_Handler
371  
372 .weak TIM4_IRQHandler
373 .thumb_set TIM4_IRQHandler,Default_Handler
374  
375 .weak I2C1_EV_IRQHandler
376 .thumb_set I2C1_EV_IRQHandler,Default_Handler
377  
378 .weak I2C1_ER_IRQHandler
379 .thumb_set I2C1_ER_IRQHandler,Default_Handler
380  
381 .weak I2C2_EV_IRQHandler
382 .thumb_set I2C2_EV_IRQHandler,Default_Handler
383  
384 .weak I2C2_ER_IRQHandler
385 .thumb_set I2C2_ER_IRQHandler,Default_Handler
386  
387 .weak SPI1_IRQHandler
388 .thumb_set SPI1_IRQHandler,Default_Handler
389  
390 .weak SPI2_IRQHandler
391 .thumb_set SPI2_IRQHandler,Default_Handler
392  
393 .weak USART1_IRQHandler
394 .thumb_set USART1_IRQHandler,Default_Handler
395  
396 .weak USART2_IRQHandler
397 .thumb_set USART2_IRQHandler,Default_Handler
398  
399 .weak USART3_IRQHandler
400 .thumb_set USART3_IRQHandler,Default_Handler
401  
402 .weak EXTI15_10_IRQHandler
403 .thumb_set EXTI15_10_IRQHandler,Default_Handler
404  
405 .weak RTCAlarm_IRQHandler
406 .thumb_set RTCAlarm_IRQHandler,Default_Handler
407  
408 .weak OTG_FS_WKUP_IRQHandler
409 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
410  
411 .weak TIM5_IRQHandler
412 .thumb_set TIM5_IRQHandler,Default_Handler
413  
414 .weak SPI3_IRQHandler
415 .thumb_set SPI3_IRQHandler,Default_Handler
416  
417 .weak UART4_IRQHandler
418 .thumb_set UART4_IRQHandler,Default_Handler
419  
420 .weak UART5_IRQHandler
421 .thumb_set UART5_IRQHandler,Default_Handler
422  
423 .weak TIM6_IRQHandler
424 .thumb_set TIM6_IRQHandler,Default_Handler
425  
426 .weak TIM7_IRQHandler
427 .thumb_set TIM7_IRQHandler,Default_Handler
428  
429 .weak DMA2_Channel1_IRQHandler
430 .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
431  
432 .weak DMA2_Channel2_IRQHandler
433 .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
434  
435 .weak DMA2_Channel3_IRQHandler
436 .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
437  
438 .weak DMA2_Channel4_IRQHandler
439 .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
440  
441 .weak DMA2_Channel5_IRQHandler
442 .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
443  
444 .weak ETH_IRQHandler
445 .thumb_set ETH_IRQHandler,Default_Handler
446  
447 .weak ETH_WKUP_IRQHandler
448 .thumb_set ETH_WKUP_IRQHandler,Default_Handler
449  
450 .weak CAN2_TX_IRQHandler
451 .thumb_set CAN2_TX_IRQHandler,Default_Handler
452  
453 .weak CAN2_RX0_IRQHandler
454 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
455  
456 .weak CAN2_RX1_IRQHandler
457 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
458  
459 .weak CAN2_SCE_IRQHandler
460 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
461  
462 .weak OTG_FS_IRQHandler
463 .thumb_set OTG_FS_IRQHandler ,Default_Handler
464