Rev Author Line No. Line
3328 povik 1 /**
2 ******************************************************************************
3 * @file stm32f10x.h
4 * @author MCD Application Team
5 * @version V3.1.2
6 * @date 09/28/2009
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for STM32F10x Connectivity line, High
10 * density, Medium density and Low density devices.
11 ******************************************************************************
12 *
13 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
14 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
15 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
16 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
17 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
18 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 *
20 * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
21 ******************************************************************************
22 */
23  
24 /** @addtogroup CMSIS
25 * @{
26 */
27  
28 /** @addtogroup stm32f10x
29 * @{
30 */
31  
32 #ifndef __STM32F10x_H
33 #define __STM32F10x_H
34  
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38  
39 /** @addtogroup Library_configuration_section
40 * @{
41 */
42  
43 /* Uncomment the line below according to the target STM32 device used in your
44 application
45 */
46  
47 #if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)
48 /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
49 /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
50 /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
51 #define STM32F10X_CL /*!< STM32F10X_CL: STM32 Connectivity line devices */
52 #endif
53 /* Tip: To avoid modifying this file each time you need to switch between these
54 devices, you can define the device in your toolchain compiler preprocessor.
55  
56 - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
57 where the Flash memory density ranges between 16 and 32 Kbytes.
58 - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
59 where the Flash memory density ranges between 64 and 128 Kbytes.
60 - High density devices are STM32F101xx and STM32F103xx microcontrollers where
61 the Flash memory density ranges between 256 and 512 Kbytes.
62 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
63 */
64  
65 #if !defined USE_STDPERIPH_DRIVER
66 /**
67 * @brief Comment the line below if you will not use the peripherals drivers.
68 In this case, these drivers will not be included and the application code will
69 be based on direct access to peripherals registers
70 */
71 /*#define USE_STDPERIPH_DRIVER*/
72 #endif
73  
74 /**
75 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
76 used in your application
77  
78 Tip: To avoid modifying this file each time you need to use different HSE, you
79 can define the HSE value in your toolchain compiler preprocessor.
80 */
81 #if !defined HSE_Value
82 #ifdef STM32F10X_CL
83 #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
84 #else
85 #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
86 #endif /* STM32F10X_CL */
87 #endif /* HSE_Value */
88  
89  
90 /**
91 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
92 Timeout value
93 */
94 #define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
95  
96 #define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
97  
98 /**
99 * @brief STM32F10x Standard Peripheral Library version number
100 */
101 #define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
102 #define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
103 #define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
104 #define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
105 | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
106 | __STM32F10X_STDPERIPH_VERSION_SUB2)
107  
108 /**
109 * @}
110 */
111  
112 /** @addtogroup Configuration_section_for_CMSIS
113 * @{
114 */
115  
116 /**
117 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
118 */
119 #define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */
120 #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
121 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
122  
123 /**
124 * @brief STM32F10x Interrupt Number Definition, according to the selected device
125 * in @ref Library_configuration_section
126 */
127 typedef enum IRQn
128 {
129 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
130 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
131 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
132 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
133 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
134 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
135 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
136 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
137 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
138  
139 /****** STM32 specific Interrupt Numbers *********************************************************/
140 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
141 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
142 TAMPER_IRQn = 2, /*!< Tamper Interrupt */
143 RTC_IRQn = 3, /*!< RTC global Interrupt */
144 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
145 RCC_IRQn = 5, /*!< RCC global Interrupt */
146 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
147 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
148 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
149 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
150 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
151 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
152 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
153 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
154 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
155 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
156 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
157 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
158 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
159  
160 #ifdef STM32F10X_LD
161 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
162 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
163 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
164 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
165 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
166 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
167 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
168 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
169 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
170 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
171 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
172 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
173 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
174 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
175 USART1_IRQn = 37, /*!< USART1 global Interrupt */
176 USART2_IRQn = 38, /*!< USART2 global Interrupt */
177 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
178 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
179 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
180 #endif /* STM32F10X_LD */
181  
182 #ifdef STM32F10X_MD
183 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
184 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
185 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
186 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
187 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
188 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
189 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
190 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
191 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
192 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
193 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
194 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
195 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
196 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
197 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
198 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
199 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
200 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
201 USART1_IRQn = 37, /*!< USART1 global Interrupt */
202 USART2_IRQn = 38, /*!< USART2 global Interrupt */
203 USART3_IRQn = 39, /*!< USART3 global Interrupt */
204 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
205 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
206 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
207 #endif /* STM32F10X_MD */
208  
209 #ifdef STM32F10X_HD
210 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
211 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
212 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
213 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
214 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
215 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
216 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
217 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
218 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
219 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
220 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
221 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
222 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
223 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
224 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
225 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
226 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
227 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
228 USART1_IRQn = 37, /*!< USART1 global Interrupt */
229 USART2_IRQn = 38, /*!< USART2 global Interrupt */
230 USART3_IRQn = 39, /*!< USART3 global Interrupt */
231 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
232 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
233 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
234 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
235 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
236 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
237 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
238 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
239 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
240 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
241 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
242 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
243 UART4_IRQn = 52, /*!< UART4 global Interrupt */
244 UART5_IRQn = 53, /*!< UART5 global Interrupt */
245 TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
246 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
247 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
248 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
249 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
250 DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
251 #endif /* STM32F10X_HD */
252  
253 #ifdef STM32F10X_CL
254 CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
255 CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
256 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
257 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
258 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
259 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
260 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
261 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
262 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
263 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
264 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
265 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
266 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
267 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
268 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
269 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
270 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
271 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
272 USART1_IRQn = 37, /*!< USART1 global Interrupt */
273 USART2_IRQn = 38, /*!< USART2 global Interrupt */
274 USART3_IRQn = 39, /*!< USART3 global Interrupt */
275 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
276 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
277 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
278 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
279 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
280 UART4_IRQn = 52, /*!< UART4 global Interrupt */
281 UART5_IRQn = 53, /*!< UART5 global Interrupt */
282 TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
283 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
284 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
285 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
286 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
287 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
288 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
289 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
290 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
291 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
292 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
293 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
294 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
295 OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
296 #endif /* STM32F10X_CL */
297 } IRQn_Type;
298  
299 /**
300 * @}
301 */
302  
303 #include "core_cm3.h"
304 #include "system_stm32f10x.h"
305 #include <stdint.h>
306  
307 /** @addtogroup Exported_types
308 * @{
309 */
310  
311 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
312 typedef int32_t s32;
313 typedef int16_t s16;
314 typedef int8_t s8;
315  
316 typedef const int32_t sc32; /*!< Read Only */
317 typedef const int16_t sc16; /*!< Read Only */
318 typedef const int8_t sc8; /*!< Read Only */
319  
320 typedef __IO int32_t vs32;
321 typedef __IO int16_t vs16;
322 typedef __IO int8_t vs8;
323  
324 typedef __I int32_t vsc32; /*!< Read Only */
325 typedef __I int16_t vsc16; /*!< Read Only */
326 typedef __I int8_t vsc8; /*!< Read Only */
327  
328 typedef uint32_t u32;
329 typedef uint16_t u16;
330 typedef uint8_t u8;
331  
332 typedef const uint32_t uc32; /*!< Read Only */
333 typedef const uint16_t uc16; /*!< Read Only */
334 typedef const uint8_t uc8; /*!< Read Only */
335  
336 typedef __IO uint32_t vu32;
337 typedef __IO uint16_t vu16;
338 typedef __IO uint8_t vu8;
339  
340 typedef __I uint32_t vuc32; /*!< Read Only */
341 typedef __I uint16_t vuc16; /*!< Read Only */
342 typedef __I uint8_t vuc8; /*!< Read Only */
343  
344 #ifndef __cplusplus
345 typedef enum {FALSE = 0, TRUE = !FALSE} bool;
346 #endif
347  
348 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
349  
350 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
351 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
352  
353 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
354  
355 /**
356 * @}
357 */
358  
359 /** @addtogroup Peripheral_registers_structures
360 * @{
361 */
362  
363 /**
364 * @brief Analog to Digital Converter
365 */
366  
367 typedef struct
368 {
369 __IO uint32_t SR;
370 __IO uint32_t CR1;
371 __IO uint32_t CR2;
372 __IO uint32_t SMPR1;
373 __IO uint32_t SMPR2;
374 __IO uint32_t JOFR1;
375 __IO uint32_t JOFR2;
376 __IO uint32_t JOFR3;
377 __IO uint32_t JOFR4;
378 __IO uint32_t HTR;
379 __IO uint32_t LTR;
380 __IO uint32_t SQR1;
381 __IO uint32_t SQR2;
382 __IO uint32_t SQR3;
383 __IO uint32_t JSQR;
384 __IO uint32_t JDR1;
385 __IO uint32_t JDR2;
386 __IO uint32_t JDR3;
387 __IO uint32_t JDR4;
388 __IO uint32_t DR;
389 } ADC_TypeDef;
390  
391 /**
392 * @brief Backup Registers
393 */
394  
395 typedef struct
396 {
397 uint32_t RESERVED0;
398 __IO uint16_t DR1;
399 uint16_t RESERVED1;
400 __IO uint16_t DR2;
401 uint16_t RESERVED2;
402 __IO uint16_t DR3;
403 uint16_t RESERVED3;
404 __IO uint16_t DR4;
405 uint16_t RESERVED4;
406 __IO uint16_t DR5;
407 uint16_t RESERVED5;
408 __IO uint16_t DR6;
409 uint16_t RESERVED6;
410 __IO uint16_t DR7;
411 uint16_t RESERVED7;
412 __IO uint16_t DR8;
413 uint16_t RESERVED8;
414 __IO uint16_t DR9;
415 uint16_t RESERVED9;
416 __IO uint16_t DR10;
417 uint16_t RESERVED10;
418 __IO uint16_t RTCCR;
419 uint16_t RESERVED11;
420 __IO uint16_t CR;
421 uint16_t RESERVED12;
422 __IO uint16_t CSR;
423 uint16_t RESERVED13[5];
424 __IO uint16_t DR11;
425 uint16_t RESERVED14;
426 __IO uint16_t DR12;
427 uint16_t RESERVED15;
428 __IO uint16_t DR13;
429 uint16_t RESERVED16;
430 __IO uint16_t DR14;
431 uint16_t RESERVED17;
432 __IO uint16_t DR15;
433 uint16_t RESERVED18;
434 __IO uint16_t DR16;
435 uint16_t RESERVED19;
436 __IO uint16_t DR17;
437 uint16_t RESERVED20;
438 __IO uint16_t DR18;
439 uint16_t RESERVED21;
440 __IO uint16_t DR19;
441 uint16_t RESERVED22;
442 __IO uint16_t DR20;
443 uint16_t RESERVED23;
444 __IO uint16_t DR21;
445 uint16_t RESERVED24;
446 __IO uint16_t DR22;
447 uint16_t RESERVED25;
448 __IO uint16_t DR23;
449 uint16_t RESERVED26;
450 __IO uint16_t DR24;
451 uint16_t RESERVED27;
452 __IO uint16_t DR25;
453 uint16_t RESERVED28;
454 __IO uint16_t DR26;
455 uint16_t RESERVED29;
456 __IO uint16_t DR27;
457 uint16_t RESERVED30;
458 __IO uint16_t DR28;
459 uint16_t RESERVED31;
460 __IO uint16_t DR29;
461 uint16_t RESERVED32;
462 __IO uint16_t DR30;
463 uint16_t RESERVED33;
464 __IO uint16_t DR31;
465 uint16_t RESERVED34;
466 __IO uint16_t DR32;
467 uint16_t RESERVED35;
468 __IO uint16_t DR33;
469 uint16_t RESERVED36;
470 __IO uint16_t DR34;
471 uint16_t RESERVED37;
472 __IO uint16_t DR35;
473 uint16_t RESERVED38;
474 __IO uint16_t DR36;
475 uint16_t RESERVED39;
476 __IO uint16_t DR37;
477 uint16_t RESERVED40;
478 __IO uint16_t DR38;
479 uint16_t RESERVED41;
480 __IO uint16_t DR39;
481 uint16_t RESERVED42;
482 __IO uint16_t DR40;
483 uint16_t RESERVED43;
484 __IO uint16_t DR41;
485 uint16_t RESERVED44;
486 __IO uint16_t DR42;
487 uint16_t RESERVED45;
488 } BKP_TypeDef;
489  
490 /**
491 * @brief Controller Area Network TxMailBox
492 */
493  
494 typedef struct
495 {
496 __IO uint32_t TIR;
497 __IO uint32_t TDTR;
498 __IO uint32_t TDLR;
499 __IO uint32_t TDHR;
500 } CAN_TxMailBox_TypeDef;
501  
502 /**
503 * @brief Controller Area Network FIFOMailBox
504 */
505  
506 typedef struct
507 {
508 __IO uint32_t RIR;
509 __IO uint32_t RDTR;
510 __IO uint32_t RDLR;
511 __IO uint32_t RDHR;
512 } CAN_FIFOMailBox_TypeDef;
513  
514 /**
515 * @brief Controller Area Network FilterRegister
516 */
517  
518 typedef struct
519 {
520 __IO uint32_t FR1;
521 __IO uint32_t FR2;
522 } CAN_FilterRegister_TypeDef;
523  
524 /**
525 * @brief Controller Area Network
526 */
527  
528 typedef struct
529 {
530 __IO uint32_t MCR;
531 __IO uint32_t MSR;
532 __IO uint32_t TSR;
533 __IO uint32_t RF0R;
534 __IO uint32_t RF1R;
535 __IO uint32_t IER;
536 __IO uint32_t ESR;
537 __IO uint32_t BTR;
538 uint32_t RESERVED0[88];
539 CAN_TxMailBox_TypeDef sTxMailBox[3];
540 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
541 uint32_t RESERVED1[12];
542 __IO uint32_t FMR;
543 __IO uint32_t FM1R;
544 uint32_t RESERVED2;
545 __IO uint32_t FS1R;
546 uint32_t RESERVED3;
547 __IO uint32_t FFA1R;
548 uint32_t RESERVED4;
549 __IO uint32_t FA1R;
550 uint32_t RESERVED5[8];
551 #ifndef STM32F10X_CL
552 CAN_FilterRegister_TypeDef sFilterRegister[14];
553 #else
554 CAN_FilterRegister_TypeDef sFilterRegister[28];
555 #endif /* STM32F10X_CL */
556 } CAN_TypeDef;
557  
558 /**
559 * @brief CRC calculation unit
560 */
561  
562 typedef struct
563 {
564 __IO uint32_t DR;
565 __IO uint8_t IDR;
566 uint8_t RESERVED0;
567 uint16_t RESERVED1;
568 __IO uint32_t CR;
569 } CRC_TypeDef;
570  
571 /**
572 * @brief Digital to Analog Converter
573 */
574  
575 typedef struct
576 {
577 __IO uint32_t CR;
578 __IO uint32_t SWTRIGR;
579 __IO uint32_t DHR12R1;
580 __IO uint32_t DHR12L1;
581 __IO uint32_t DHR8R1;
582 __IO uint32_t DHR12R2;
583 __IO uint32_t DHR12L2;
584 __IO uint32_t DHR8R2;
585 __IO uint32_t DHR12RD;
586 __IO uint32_t DHR12LD;
587 __IO uint32_t DHR8RD;
588 __IO uint32_t DOR1;
589 __IO uint32_t DOR2;
590 } DAC_TypeDef;
591  
592 /**
593 * @brief Debug MCU
594 */
595  
596 typedef struct
597 {
598 __IO uint32_t IDCODE;
599 __IO uint32_t CR;
600 }DBGMCU_TypeDef;
601  
602 /**
603 * @brief DMA Controller
604 */
605  
606 typedef struct
607 {
608 __IO uint32_t CCR;
609 __IO uint32_t CNDTR;
610 __IO uint32_t CPAR;
611 __IO uint32_t CMAR;
612 } DMA_Channel_TypeDef;
613  
614 typedef struct
615 {
616 __IO uint32_t ISR;
617 __IO uint32_t IFCR;
618 } DMA_TypeDef;
619  
620 /**
621 * @brief Ethernet MAC
622 */
623  
624 typedef struct
625 {
626 __IO uint32_t MACCR;
627 __IO uint32_t MACFFR;
628 __IO uint32_t MACHTHR;
629 __IO uint32_t MACHTLR;
630 __IO uint32_t MACMIIAR;
631 __IO uint32_t MACMIIDR;
632 __IO uint32_t MACFCR;
633 __IO uint32_t MACVLANTR; /* 8 */
634 uint32_t RESERVED0[2];
635 __IO uint32_t MACRWUFFR; /* 11 */
636 __IO uint32_t MACPMTCSR;
637 uint32_t RESERVED1[2];
638 __IO uint32_t MACSR; /* 15 */
639 __IO uint32_t MACIMR;
640 __IO uint32_t MACA0HR;
641 __IO uint32_t MACA0LR;
642 __IO uint32_t MACA1HR;
643 __IO uint32_t MACA1LR;
644 __IO uint32_t MACA2HR;
645 __IO uint32_t MACA2LR;
646 __IO uint32_t MACA3HR;
647 __IO uint32_t MACA3LR; /* 24 */
648 uint32_t RESERVED2[40];
649 __IO uint32_t MMCCR; /* 65 */
650 __IO uint32_t MMCRIR;
651 __IO uint32_t MMCTIR;
652 __IO uint32_t MMCRIMR;
653 __IO uint32_t MMCTIMR; /* 69 */
654 uint32_t RESERVED3[14];
655 __IO uint32_t MMCTGFSCCR; /* 84 */
656 __IO uint32_t MMCTGFMSCCR;
657 uint32_t RESERVED4[5];
658 __IO uint32_t MMCTGFCR;
659 uint32_t RESERVED5[10];
660 __IO uint32_t MMCRFCECR;
661 __IO uint32_t MMCRFAECR;
662 uint32_t RESERVED6[10];
663 __IO uint32_t MMCRGUFCR;
664 uint32_t RESERVED7[334];
665 __IO uint32_t PTPTSCR;
666 __IO uint32_t PTPSSIR;
667 __IO uint32_t PTPTSHR;
668 __IO uint32_t PTPTSLR;
669 __IO uint32_t PTPTSHUR;
670 __IO uint32_t PTPTSLUR;
671 __IO uint32_t PTPTSAR;
672 __IO uint32_t PTPTTHR;
673 __IO uint32_t PTPTTLR;
674 uint32_t RESERVED8[567];
675 __IO uint32_t DMABMR;
676 __IO uint32_t DMATPDR;
677 __IO uint32_t DMARPDR;
678 __IO uint32_t DMARDLAR;
679 __IO uint32_t DMATDLAR;
680 __IO uint32_t DMASR;
681 __IO uint32_t DMAOMR;
682 __IO uint32_t DMAIER;
683 __IO uint32_t DMAMFBOCR;
684 uint32_t RESERVED9[9];
685 __IO uint32_t DMACHTDR;
686 __IO uint32_t DMACHRDR;
687 __IO uint32_t DMACHTBAR;
688 __IO uint32_t DMACHRBAR;
689 } ETH_TypeDef;
690  
691 /**
692 * @brief External Interrupt/Event Controller
693 */
694  
695 typedef struct
696 {
697 __IO uint32_t IMR;
698 __IO uint32_t EMR;
699 __IO uint32_t RTSR;
700 __IO uint32_t FTSR;
701 __IO uint32_t SWIER;
702 __IO uint32_t PR;
703 } EXTI_TypeDef;
704  
705 /**
706 * @brief FLASH Registers
707 */
708  
709 typedef struct
710 {
711 __IO uint32_t ACR;
712 __IO uint32_t KEYR;
713 __IO uint32_t OPTKEYR;
714 __IO uint32_t SR;
715 __IO uint32_t CR;
716 __IO uint32_t AR;
717 __IO uint32_t RESERVED;
718 __IO uint32_t OBR;
719 __IO uint32_t WRPR;
720 } FLASH_TypeDef;
721  
722 /**
723 * @brief Option Bytes Registers
724 */
725  
726 typedef struct
727 {
728 __IO uint16_t RDP;
729 __IO uint16_t USER;
730 __IO uint16_t Data0;
731 __IO uint16_t Data1;
732 __IO uint16_t WRP0;
733 __IO uint16_t WRP1;
734 __IO uint16_t WRP2;
735 __IO uint16_t WRP3;
736 } OB_TypeDef;
737  
738 /**
739 * @brief Flexible Static Memory Controller
740 */
741  
742 typedef struct
743 {
744 __IO uint32_t BTCR[8];
745 } FSMC_Bank1_TypeDef;
746  
747 /**
748 * @brief Flexible Static Memory Controller Bank1E
749 */
750  
751 typedef struct
752 {
753 __IO uint32_t BWTR[7];
754 } FSMC_Bank1E_TypeDef;
755  
756 /**
757 * @brief Flexible Static Memory Controller Bank2
758 */
759  
760 typedef struct
761 {
762 __IO uint32_t PCR2;
763 __IO uint32_t SR2;
764 __IO uint32_t PMEM2;
765 __IO uint32_t PATT2;
766 uint32_t RESERVED0;
767 __IO uint32_t ECCR2;
768 } FSMC_Bank2_TypeDef;
769  
770 /**
771 * @brief Flexible Static Memory Controller Bank3
772 */
773  
774 typedef struct
775 {
776 __IO uint32_t PCR3;
777 __IO uint32_t SR3;
778 __IO uint32_t PMEM3;
779 __IO uint32_t PATT3;
780 uint32_t RESERVED0;
781 __IO uint32_t ECCR3;
782 } FSMC_Bank3_TypeDef;
783  
784 /**
785 * @brief Flexible Static Memory Controller Bank4
786 */
787  
788 typedef struct
789 {
790 __IO uint32_t PCR4;
791 __IO uint32_t SR4;
792 __IO uint32_t PMEM4;
793 __IO uint32_t PATT4;
794 __IO uint32_t PIO4;
795 } FSMC_Bank4_TypeDef;
796  
797 /**
798 * @brief General Purpose I/O
799 */
800  
801 typedef struct
802 {
803 __IO uint32_t CRL;
804 __IO uint32_t CRH;
805 __IO uint32_t IDR;
806 __IO uint32_t ODR;
807 __IO uint32_t BSRR;
808 __IO uint32_t BRR;
809 __IO uint32_t LCKR;
810 } GPIO_TypeDef;
811  
812 /**
813 * @brief Alternate Function I/O
814 */
815  
816 typedef struct
817 {
818 __IO uint32_t EVCR;
819 __IO uint32_t MAPR;
820 __IO uint32_t EXTICR[4];
821 } AFIO_TypeDef;
822 /**
823 * @brief Inter-integrated Circuit Interface
824 */
825  
826 typedef struct
827 {
828 __IO uint16_t CR1;
829 uint16_t RESERVED0;
830 __IO uint16_t CR2;
831 uint16_t RESERVED1;
832 __IO uint16_t OAR1;
833 uint16_t RESERVED2;
834 __IO uint16_t OAR2;
835 uint16_t RESERVED3;
836 __IO uint16_t DR;
837 uint16_t RESERVED4;
838 __IO uint16_t SR1;
839 uint16_t RESERVED5;
840 __IO uint16_t SR2;
841 uint16_t RESERVED6;
842 __IO uint16_t CCR;
843 uint16_t RESERVED7;
844 __IO uint16_t TRISE;
845 uint16_t RESERVED8;
846 } I2C_TypeDef;
847  
848 /**
849 * @brief Independent WATCHDOG
850 */
851  
852 typedef struct
853 {
854 __IO uint32_t KR;
855 __IO uint32_t PR;
856 __IO uint32_t RLR;
857 __IO uint32_t SR;
858 } IWDG_TypeDef;
859  
860 /**
861 * @brief Power Control
862 */
863  
864 typedef struct
865 {
866 __IO uint32_t CR;
867 __IO uint32_t CSR;
868 } PWR_TypeDef;
869  
870 /**
871 * @brief Reset and Clock Control
872 */
873  
874 typedef struct
875 {
876 __IO uint32_t CR;
877 __IO uint32_t CFGR;
878 __IO uint32_t CIR;
879 __IO uint32_t APB2RSTR;
880 __IO uint32_t APB1RSTR;
881 __IO uint32_t AHBENR;
882 __IO uint32_t APB2ENR;
883 __IO uint32_t APB1ENR;
884 __IO uint32_t BDCR;
885 __IO uint32_t CSR;
886 #ifdef STM32F10X_CL
887 __IO uint32_t AHBRSTR;
888 __IO uint32_t CFGR2;
889 #endif /* STM32F10X_CL */
890 } RCC_TypeDef;
891  
892 /**
893 * @brief Real-Time Clock
894 */
895  
896 typedef struct
897 {
898 __IO uint16_t CRH;
899 uint16_t RESERVED0;
900 __IO uint16_t CRL;
901 uint16_t RESERVED1;
902 __IO uint16_t PRLH;
903 uint16_t RESERVED2;
904 __IO uint16_t PRLL;
905 uint16_t RESERVED3;
906 __IO uint16_t DIVH;
907 uint16_t RESERVED4;
908 __IO uint16_t DIVL;
909 uint16_t RESERVED5;
910 __IO uint16_t CNTH;
911 uint16_t RESERVED6;
912 __IO uint16_t CNTL;
913 uint16_t RESERVED7;
914 __IO uint16_t ALRH;
915 uint16_t RESERVED8;
916 __IO uint16_t ALRL;
917 uint16_t RESERVED9;
918 } RTC_TypeDef;
919  
920 /**
921 * @brief SD host Interface
922 */
923  
924 typedef struct
925 {
926 __IO uint32_t POWER;
927 __IO uint32_t CLKCR;
928 __IO uint32_t ARG;
929 __IO uint32_t CMD;
930 __I uint32_t RESPCMD;
931 __I uint32_t RESP1;
932 __I uint32_t RESP2;
933 __I uint32_t RESP3;
934 __I uint32_t RESP4;
935 __IO uint32_t DTIMER;
936 __IO uint32_t DLEN;
937 __IO uint32_t DCTRL;
938 __I uint32_t DCOUNT;
939 __I uint32_t STA;
940 __IO uint32_t ICR;
941 __IO uint32_t MASK;
942 uint32_t RESERVED0[2];
943 __I uint32_t FIFOCNT;
944 uint32_t RESERVED1[13];
945 __IO uint32_t FIFO;
946 } SDIO_TypeDef;
947  
948 /**
949 * @brief Serial Peripheral Interface
950 */
951  
952 typedef struct
953 {
954 __IO uint16_t CR1;
955 uint16_t RESERVED0;
956 __IO uint16_t CR2;
957 uint16_t RESERVED1;
958 __IO uint16_t SR;
959 uint16_t RESERVED2;
960 __IO uint16_t DR;
961 uint16_t RESERVED3;
962 __IO uint16_t CRCPR;
963 uint16_t RESERVED4;
964 __IO uint16_t RXCRCR;
965 uint16_t RESERVED5;
966 __IO uint16_t TXCRCR;
967 uint16_t RESERVED6;
968 __IO uint16_t I2SCFGR;
969 uint16_t RESERVED7;
970 __IO uint16_t I2SPR;
971 uint16_t RESERVED8;
972 } SPI_TypeDef;
973  
974 /**
975 * @brief TIM
976 */
977  
978 typedef struct
979 {
980 __IO uint16_t CR1;
981 uint16_t RESERVED0;
982 __IO uint16_t CR2;
983 uint16_t RESERVED1;
984 __IO uint16_t SMCR;
985 uint16_t RESERVED2;
986 __IO uint16_t DIER;
987 uint16_t RESERVED3;
988 __IO uint16_t SR;
989 uint16_t RESERVED4;
990 __IO uint16_t EGR;
991 uint16_t RESERVED5;
992 __IO uint16_t CCMR1;
993 uint16_t RESERVED6;
994 __IO uint16_t CCMR2;
995 uint16_t RESERVED7;
996 __IO uint16_t CCER;
997 uint16_t RESERVED8;
998 __IO uint16_t CNT;
999 uint16_t RESERVED9;
1000 __IO uint16_t PSC;
1001 uint16_t RESERVED10;
1002 __IO uint16_t ARR;
1003 uint16_t RESERVED11;
1004 __IO uint16_t RCR;
1005 uint16_t RESERVED12;
1006 __IO uint16_t CCR1;
1007 uint16_t RESERVED13;
1008 __IO uint16_t CCR2;
1009 uint16_t RESERVED14;
1010 __IO uint16_t CCR3;
1011 uint16_t RESERVED15;
1012 __IO uint16_t CCR4;
1013 uint16_t RESERVED16;
1014 __IO uint16_t BDTR;
1015 uint16_t RESERVED17;
1016 __IO uint16_t DCR;
1017 uint16_t RESERVED18;
1018 __IO uint16_t DMAR;
1019 uint16_t RESERVED19;
1020 } TIM_TypeDef;
1021  
1022 /**
1023 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1024 */
1025  
1026 typedef struct
1027 {
1028 __IO uint16_t SR;
1029 uint16_t RESERVED0;
1030 __IO uint16_t DR;
1031 uint16_t RESERVED1;
1032 __IO uint16_t BRR;
1033 uint16_t RESERVED2;
1034 __IO uint16_t CR1;
1035 uint16_t RESERVED3;
1036 __IO uint16_t CR2;
1037 uint16_t RESERVED4;
1038 __IO uint16_t CR3;
1039 uint16_t RESERVED5;
1040 __IO uint16_t GTPR;
1041 uint16_t RESERVED6;
1042 } USART_TypeDef;
1043  
1044 /**
1045 * @brief Window WATCHDOG
1046 */
1047  
1048 typedef struct
1049 {
1050 __IO uint32_t CR;
1051 __IO uint32_t CFR;
1052 __IO uint32_t SR;
1053 } WWDG_TypeDef;
1054  
1055 /**
1056 * @}
1057 */
1058  
1059 /** @addtogroup Peripheral_memory_map
1060 * @{
1061 */
1062  
1063 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
1064 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
1065  
1066 #define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
1067 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
1068  
1069 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
1070  
1071 /*!< Peripheral memory map */
1072 #define APB1PERIPH_BASE PERIPH_BASE
1073 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
1074 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
1075  
1076 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1077 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1078 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1079 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1080 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1081 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1082 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1083 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1084 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1085 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1086 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1087 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1088 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1089 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1090 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1091 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1092 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1093 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1094 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1095 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
1096 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1097 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1098  
1099 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
1100 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
1101 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
1102 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
1103 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
1104 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
1105 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
1106 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
1107 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
1108 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
1109 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
1110 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
1111 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1112 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
1113 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
1114 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
1115  
1116 #define SDIO_BASE (PERIPH_BASE + 0x18000)
1117  
1118 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
1119 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
1120 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
1121 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
1122 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
1123 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
1124 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
1125 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
1126 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
1127 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
1128 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
1129 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
1130 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
1131 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
1132 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
1133 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
1134  
1135 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
1136 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
1137  
1138 #define ETH_BASE (AHBPERIPH_BASE + 0x8000)
1139 #define ETH_MAC_BASE (ETH_BASE)
1140 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
1141 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
1142 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
1143  
1144 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
1145 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
1146 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
1147 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
1148 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
1149  
1150 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
1151  
1152 /**
1153 * @}
1154 */
1155  
1156 /** @addtogroup Peripheral_declaration
1157 * @{
1158 */
1159  
1160 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1161 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1162 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1163 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1164 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1165 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1166 #define RTC ((RTC_TypeDef *) RTC_BASE)
1167 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1168 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1169 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1170 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1171 #define USART2 ((USART_TypeDef *) USART2_BASE)
1172 #define USART3 ((USART_TypeDef *) USART3_BASE)
1173 #define UART4 ((USART_TypeDef *) UART4_BASE)
1174 #define UART5 ((USART_TypeDef *) UART5_BASE)
1175 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1176 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1177 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1178 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1179 #define BKP ((BKP_TypeDef *) BKP_BASE)
1180 #define PWR ((PWR_TypeDef *) PWR_BASE)
1181 #define DAC ((DAC_TypeDef *) DAC_BASE)
1182 #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
1183 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1184 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1185 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1186 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1187 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1188 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1189 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1190 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1191 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1192 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1193 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1194 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1195 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1196 #define USART1 ((USART_TypeDef *) USART1_BASE)
1197 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1198 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1199 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1200 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1201 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1202 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1203 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1204 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1205 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1206 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1207 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1208 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1209 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1210 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1211 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1212 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1213 #define RCC ((RCC_TypeDef *) RCC_BASE)
1214 #define CRC ((CRC_TypeDef *) CRC_BASE)
1215 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1216 #define OB ((OB_TypeDef *) OB_BASE)
1217 #define ETH ((ETH_TypeDef *) ETH_BASE)
1218 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1219 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1220 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1221 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1222 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1223 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1224  
1225 /**
1226 * @}
1227 */
1228  
1229 /** @addtogroup Exported_constants
1230 * @{
1231 */
1232  
1233 /** @addtogroup Peripheral_Registers_Bits_Definition
1234 * @{
1235 */
1236  
1237 /******************************************************************************/
1238 /* Peripheral Registers_Bits_Definition */
1239 /******************************************************************************/
1240  
1241 /******************************************************************************/
1242 /* */
1243 /* CRC calculation unit */
1244 /* */
1245 /******************************************************************************/
1246  
1247 /******************* Bit definition for CRC_DR register *********************/
1248 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
1249  
1250  
1251 /******************* Bit definition for CRC_IDR register ********************/
1252 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
1253  
1254  
1255 /******************** Bit definition for CRC_CR register ********************/
1256 #define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
1257  
1258 /******************************************************************************/
1259 /* */
1260 /* Power Control */
1261 /* */
1262 /******************************************************************************/
1263  
1264 /******************** Bit definition for PWR_CR register ********************/
1265 #define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
1266 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
1267 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
1268 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
1269 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
1270  
1271 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
1272 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
1273 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
1274 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
1275  
1276 /*!< PVD level configuration */
1277 #define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
1278 #define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
1279 #define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
1280 #define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
1281 #define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
1282 #define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
1283 #define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
1284 #define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
1285  
1286 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
1287  
1288  
1289 /******************* Bit definition for PWR_CSR register ********************/
1290 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
1291 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
1292 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
1293 #define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
1294  
1295 /******************************************************************************/
1296 /* */
1297 /* Backup registers */
1298 /* */
1299 /******************************************************************************/
1300  
1301 /******************* Bit definition for BKP_DR1 register ********************/
1302 #define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
1303  
1304 /******************* Bit definition for BKP_DR2 register ********************/
1305 #define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
1306  
1307 /******************* Bit definition for BKP_DR3 register ********************/
1308 #define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
1309  
1310 /******************* Bit definition for BKP_DR4 register ********************/
1311 #define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
1312  
1313 /******************* Bit definition for BKP_DR5 register ********************/
1314 #define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
1315  
1316 /******************* Bit definition for BKP_DR6 register ********************/
1317 #define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
1318  
1319 /******************* Bit definition for BKP_DR7 register ********************/
1320 #define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
1321  
1322 /******************* Bit definition for BKP_DR8 register ********************/
1323 #define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
1324  
1325 /******************* Bit definition for BKP_DR9 register ********************/
1326 #define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
1327  
1328 /******************* Bit definition for BKP_DR10 register *******************/
1329 #define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
1330  
1331 /******************* Bit definition for BKP_DR11 register *******************/
1332 #define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
1333  
1334 /******************* Bit definition for BKP_DR12 register *******************/
1335 #define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
1336  
1337 /******************* Bit definition for BKP_DR13 register *******************/
1338 #define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
1339  
1340 /******************* Bit definition for BKP_DR14 register *******************/
1341 #define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
1342  
1343 /******************* Bit definition for BKP_DR15 register *******************/
1344 #define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
1345  
1346 /******************* Bit definition for BKP_DR16 register *******************/
1347 #define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
1348  
1349 /******************* Bit definition for BKP_DR17 register *******************/
1350 #define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
1351  
1352 /****************** Bit definition for BKP_DR18 register ********************/
1353 #define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
1354  
1355 /******************* Bit definition for BKP_DR19 register *******************/
1356 #define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
1357  
1358 /******************* Bit definition for BKP_DR20 register *******************/
1359 #define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
1360  
1361 /******************* Bit definition for BKP_DR21 register *******************/
1362 #define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
1363  
1364 /******************* Bit definition for BKP_DR22 register *******************/
1365 #define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
1366  
1367 /******************* Bit definition for BKP_DR23 register *******************/
1368 #define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
1369  
1370 /******************* Bit definition for BKP_DR24 register *******************/
1371 #define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
1372  
1373 /******************* Bit definition for BKP_DR25 register *******************/
1374 #define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
1375  
1376 /******************* Bit definition for BKP_DR26 register *******************/
1377 #define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
1378  
1379 /******************* Bit definition for BKP_DR27 register *******************/
1380 #define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
1381  
1382 /******************* Bit definition for BKP_DR28 register *******************/
1383 #define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
1384  
1385 /******************* Bit definition for BKP_DR29 register *******************/
1386 #define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
1387  
1388 /******************* Bit definition for BKP_DR30 register *******************/
1389 #define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
1390  
1391 /******************* Bit definition for BKP_DR31 register *******************/
1392 #define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
1393  
1394 /******************* Bit definition for BKP_DR32 register *******************/
1395 #define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
1396  
1397 /******************* Bit definition for BKP_DR33 register *******************/
1398 #define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
1399  
1400 /******************* Bit definition for BKP_DR34 register *******************/
1401 #define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
1402  
1403 /******************* Bit definition for BKP_DR35 register *******************/
1404 #define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
1405  
1406 /******************* Bit definition for BKP_DR36 register *******************/
1407 #define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
1408  
1409 /******************* Bit definition for BKP_DR37 register *******************/
1410 #define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
1411  
1412 /******************* Bit definition for BKP_DR38 register *******************/
1413 #define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
1414  
1415 /******************* Bit definition for BKP_DR39 register *******************/
1416 #define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
1417  
1418 /******************* Bit definition for BKP_DR40 register *******************/
1419 #define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
1420  
1421 /******************* Bit definition for BKP_DR41 register *******************/
1422 #define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
1423  
1424 /******************* Bit definition for BKP_DR42 register *******************/
1425 #define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
1426  
1427 /****************** Bit definition for BKP_RTCCR register *******************/
1428 #define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
1429 #define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
1430 #define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
1431 #define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
1432  
1433 /******************** Bit definition for BKP_CR register ********************/
1434 #define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
1435 #define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
1436  
1437 /******************* Bit definition for BKP_CSR register ********************/
1438 #define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
1439 #define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
1440 #define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
1441 #define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
1442 #define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
1443  
1444 /******************************************************************************/
1445 /* */
1446 /* Reset and Clock Control */
1447 /* */
1448 /******************************************************************************/
1449  
1450 /******************** Bit definition for RCC_CR register ********************/
1451 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
1452 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
1453 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
1454 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
1455 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
1456 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
1457 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
1458 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
1459 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
1460 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
1461  
1462 #ifdef STM32F10X_CL
1463 #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
1464 #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
1465 #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
1466 #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
1467 #endif /* STM32F10X_CL */
1468  
1469 /******************* Bit definition for RCC_CFGR register *******************/
1470 /*!< SW configuration */
1471 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
1472 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1473 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1474  
1475 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
1476 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
1477 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
1478  
1479 /*!< SWS configuration */
1480 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
1481 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
1482 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
1483  
1484 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
1485 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
1486 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
1487  
1488 /*!< HPRE configuration */
1489 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
1490 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
1491 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
1492 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
1493 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
1494  
1495 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
1496 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
1497 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
1498 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
1499 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
1500 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
1501 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
1502 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
1503 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
1504  
1505 /*!< PPRE1 configuration */
1506 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
1507 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1508 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1509 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
1510  
1511 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
1512 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
1513 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
1514 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
1515 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
1516  
1517 /*!< PPRE2 configuration */
1518 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
1519 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
1520 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
1521 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
1522  
1523 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
1524 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
1525 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
1526 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
1527 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
1528  
1529 /*!< ADCPPRE configuration */
1530 #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
1531 #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
1532 #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
1533  
1534 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
1535 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
1536 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
1537 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
1538  
1539 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
1540  
1541 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
1542  
1543 /*!< PLLMUL configuration */
1544 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
1545 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
1546 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1547 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
1548 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
1549  
1550 #ifdef STM32F10X_CL
1551 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
1552 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
1553  
1554 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
1555 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
1556  
1557 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
1558 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
1559 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
1560 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
1561 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
1562 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
1563 #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
1564  
1565 #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */
1566  
1567 /*!< MCO configuration */
1568 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
1569 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1570 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1571 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1572 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
1573  
1574 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1575 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
1576 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
1577 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
1578 #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
1579 #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
1580 #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
1581 #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
1582 #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
1583 #else
1584 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
1585 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
1586  
1587 #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
1588 #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
1589  
1590 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
1591 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
1592 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
1593 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
1594 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
1595 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
1596 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
1597 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
1598 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
1599 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
1600 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
1601 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
1602 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
1603 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
1604 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
1605 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
1606  
1607 /*!< MCO configuration */
1608 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1609 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1610 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1611 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1612  
1613 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1614 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
1615 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
1616 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
1617 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
1618 #endif /* STM32F10X_CL */
1619  
1620 /*!<****************** Bit definition for RCC_CIR register ********************/
1621 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
1622 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
1623 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
1624 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
1625 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
1626 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
1627 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
1628 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
1629 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
1630 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
1631 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
1632 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
1633 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
1634 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
1635 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
1636 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
1637 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
1638  
1639 #ifdef STM32F10X_CL
1640 #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
1641 #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
1642 #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
1643 #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
1644 #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
1645 #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
1646 #endif /* STM32F10X_CL */
1647  
1648 /***************** Bit definition for RCC_APB2RSTR register *****************/
1649 #define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */
1650 #define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */
1651 #define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */
1652 #define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */
1653 #define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */
1654 #define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */
1655 #define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */
1656 #define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */
1657 #define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */
1658 #define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */
1659  
1660 #ifndef STM32F10X_LD
1661 #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */
1662 #endif /* STM32F10X_HD */
1663  
1664 #ifdef STM32F10X_HD
1665 #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */
1666 #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */
1667 #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */
1668 #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */
1669 #endif /* STM32F10X_HD */
1670  
1671 /***************** Bit definition for RCC_APB1RSTR register *****************/
1672 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
1673 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
1674 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
1675 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
1676 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
1677 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
1678 #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
1679 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
1680  
1681 #ifndef STM32F10X_LD
1682 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
1683 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
1684 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
1685 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
1686 #endif /* STM32F10X_HD */
1687  
1688 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
1689 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
1690 #endif
1691  
1692 #if defined (STM32F10X_HD) || defined (STM32F10X_CL)
1693 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
1694 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
1695 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
1696 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
1697 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
1698 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
1699 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
1700 #endif
1701  
1702 #ifdef STM32F10X_CL
1703 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */
1704 #endif /* STM32F10X_CL */
1705  
1706 /****************** Bit definition for RCC_AHBENR register ******************/
1707 #define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
1708 #define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
1709 #define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
1710 #define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
1711  
1712 #if defined (STM32F10X_HD) || defined (STM32F10X_CL)
1713 #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
1714 #endif
1715  
1716 #ifdef STM32F10X_HD
1717 #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
1718 #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
1719 #endif /* STM32F10X_HD */
1720  
1721 #ifdef STM32F10X_CL
1722 #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
1723 #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
1724 #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
1725 #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
1726 #endif /* STM32F10X_CL */
1727  
1728 /****************** Bit definition for RCC_APB2ENR register *****************/
1729 #define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */
1730 #define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */
1731 #define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */
1732 #define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */
1733 #define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */
1734 #define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */
1735 #define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */
1736 #define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */
1737 #define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */
1738 #define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */
1739  
1740 #ifndef STM32F10X_LD
1741 #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */
1742 #endif /* STM32F10X_HD */
1743  
1744 #ifdef STM32F10X_HD
1745 #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */
1746 #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */
1747 #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */
1748 #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */
1749 #endif /* STM32F10X_HD */
1750  
1751 /***************** Bit definition for RCC_APB1ENR register ******************/
1752 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
1753 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
1754 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
1755 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
1756 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
1757 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
1758 #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
1759 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
1760  
1761 #ifndef STM32F10X_LD
1762 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
1763 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
1764 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
1765 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
1766 #endif /* STM32F10X_HD */
1767  
1768 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
1769 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
1770 #endif
1771  
1772 #if defined (STM32F10X_HD) || defined (STM32F10X_CL)
1773 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
1774 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
1775 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
1776 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
1777 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
1778 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
1779 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
1780 #endif
1781  
1782 #ifdef STM32F10X_CL
1783 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */
1784 #endif /* STM32F10X_CL */
1785  
1786 /******************* Bit definition for RCC_BDCR register *******************/
1787 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
1788 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
1789 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
1790  
1791 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
1792 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1793 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1794  
1795 /*!< RTC congiguration */
1796 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1797 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
1798 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
1799 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
1800  
1801 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
1802 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
1803  
1804 /******************* Bit definition for RCC_CSR register ********************/
1805 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
1806 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
1807 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
1808 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
1809 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
1810 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
1811 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
1812 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
1813 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
1814  
1815 #ifdef STM32F10X_CL
1816 /******************* Bit definition for RCC_AHBRSTR register ****************/
1817 #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
1818 #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
1819  
1820 /******************* Bit definition for RCC_CFGR2 register ******************/
1821 /*!< PREDIV1 configuration */
1822 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
1823 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1824 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1825 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
1826 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
1827  
1828 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
1829 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
1830 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
1831 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
1832 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
1833 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
1834 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
1835 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
1836 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
1837 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
1838 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
1839 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
1840 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
1841 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
1842 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
1843 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
1844  
1845 /*!< PREDIV2 configuration */
1846 #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
1847 #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
1848 #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
1849 #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
1850 #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
1851  
1852 #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
1853 #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
1854 #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
1855 #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
1856 #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
1857 #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
1858 #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
1859 #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
1860 #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
1861 #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
1862 #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
1863 #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
1864 #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
1865 #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
1866 #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
1867 #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
1868  
1869 /*!< PLL2MUL configuration */
1870 #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
1871 #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1872 #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1873 #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
1874 #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
1875  
1876 #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
1877 #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
1878 #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
1879 #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
1880 #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
1881 #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
1882 #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
1883 #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
1884 #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
1885  
1886 /*!< PLL3MUL configuration */
1887 #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
1888 #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1889 #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1890 #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
1891 #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
1892  
1893 #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
1894 #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
1895 #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
1896 #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
1897 #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
1898 #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
1899 #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
1900 #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
1901 #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
1902  
1903 #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
1904 #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
1905 #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
1906 #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
1907 #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
1908 #endif /* STM32F10X_CL */
1909  
1910 /******************************************************************************/
1911 /* */
1912 /* General Purpose and Alternate Function I/O */
1913 /* */
1914 /******************************************************************************/
1915  
1916 /******************* Bit definition for GPIO_CRL register *******************/
1917 #define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
1918  
1919 #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
1920 #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1921 #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1922  
1923 #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
1924 #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
1925 #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
1926  
1927 #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
1928 #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1929 #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1930  
1931 #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
1932 #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1933 #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1934  
1935 #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
1936 #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
1937 #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
1938  
1939 #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
1940 #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
1941 #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
1942  
1943 #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
1944 #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1945 #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1946  
1947 #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
1948 #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
1949 #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
1950  
1951 #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
1952  
1953 #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
1954 #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
1955 #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
1956  
1957 #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
1958 #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
1959 #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
1960  
1961 #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
1962 #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1963 #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1964  
1965 #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
1966 #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
1967 #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
1968  
1969 #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
1970 #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
1971 #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1972  
1973 #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
1974 #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
1975 #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
1976  
1977 #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
1978 #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
1979 #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
1980  
1981 #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
1982 #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
1983 #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
1984  
1985 /******************* Bit definition for GPIO_CRH register *******************/
1986 #define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
1987  
1988 #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
1989 #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1990 #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1991  
1992 #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
1993 #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
1994 #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
1995  
1996 #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
1997 #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1998 #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1999  
2000 #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
2001 #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2002 #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2003  
2004 #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
2005 #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2006 #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2007  
2008 #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
2009 #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
2010 #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
2011  
2012 #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
2013 #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2014 #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2015  
2016 #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
2017 #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
2018 #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
2019  
2020 #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
2021  
2022 #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
2023 #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2024 #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2025  
2026 #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
2027 #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
2028 #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
2029  
2030 #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
2031 #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
2032 #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
2033  
2034 #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
2035 #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2036 #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2037  
2038 #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
2039 #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2040 #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2041  
2042 #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
2043 #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
2044 #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
2045  
2046 #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
2047 #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
2048 #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
2049  
2050 #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
2051 #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
2052 #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
2053  
2054 /*!<****************** Bit definition for GPIO_IDR register *******************/
2055 #define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
2056 #define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
2057 #define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
2058 #define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
2059 #define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
2060 #define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
2061 #define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
2062 #define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
2063 #define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
2064 #define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
2065 #define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
2066 #define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
2067 #define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
2068 #define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
2069 #define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
2070 #define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
2071  
2072 /******************* Bit definition for GPIO_ODR register *******************/
2073 #define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
2074 #define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
2075 #define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
2076 #define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
2077 #define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
2078 #define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
2079 #define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
2080 #define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
2081 #define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
2082 #define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
2083 #define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
2084 #define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
2085 #define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
2086 #define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
2087 #define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
2088 #define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
2089  
2090 /****************** Bit definition for GPIO_BSRR register *******************/
2091 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
2092 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
2093 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
2094 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
2095 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
2096 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
2097 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
2098 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
2099 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
2100 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
2101 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
2102 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
2103 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
2104 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
2105 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
2106 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
2107  
2108 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
2109 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
2110 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
2111 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
2112 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
2113 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
2114 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
2115 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
2116 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
2117 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
2118 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
2119 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
2120 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
2121 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
2122 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
2123 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
2124  
2125 /******************* Bit definition for GPIO_BRR register *******************/
2126 #define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
2127 #define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
2128 #define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
2129 #define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
2130 #define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
2131 #define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
2132 #define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
2133 #define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
2134 #define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
2135 #define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
2136 #define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
2137 #define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
2138 #define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
2139 #define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
2140 #define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
2141 #define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
2142  
2143 /****************** Bit definition for GPIO_LCKR register *******************/
2144 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
2145 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
2146 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
2147 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
2148 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
2149 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
2150 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
2151 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
2152 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
2153 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
2154 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
2155 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
2156 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
2157 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
2158 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
2159 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
2160 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
2161  
2162 /*----------------------------------------------------------------------------*/
2163  
2164 /****************** Bit definition for AFIO_EVCR register *******************/
2165 #define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
2166 #define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
2167 #define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
2168 #define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
2169 #define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
2170  
2171 /*!< PIN configuration */
2172 #define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
2173 #define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
2174 #define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
2175 #define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
2176 #define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
2177 #define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
2178 #define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
2179 #define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
2180 #define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
2181 #define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
2182 #define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
2183 #define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
2184 #define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
2185 #define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
2186 #define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
2187 #define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
2188  
2189 #define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
2190 #define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
2191 #define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
2192 #define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
2193  
2194 /*!< PORT configuration */
2195 #define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
2196 #define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
2197 #define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
2198 #define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
2199 #define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
2200  
2201 #define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
2202  
2203 /****************** Bit definition for AFIO_MAPR register *******************/
2204 #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
2205 #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
2206 #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
2207 #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
2208  
2209 #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
2210 #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2211 #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2212  
2213 /* USART3_REMAP configuration */
2214 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
2215 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
2216 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
2217  
2218 #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
2219 #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
2220 #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
2221  
2222 /*!< TIM1_REMAP configuration */
2223 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
2224 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
2225 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
2226  
2227 #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
2228 #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2229 #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2230  
2231 /*!< TIM2_REMAP configuration */
2232 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
2233 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
2234 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
2235 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
2236  
2237 #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
2238 #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
2239 #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
2240  
2241 /*!< TIM3_REMAP configuration */
2242 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2243 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2244 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2245  
2246 #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
2247  
2248 #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
2249 #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
2250 #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
2251  
2252 /*!< CAN_REMAP configuration */
2253 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
2254 #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
2255 #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
2256  
2257 #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2258 #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
2259 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
2260 #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
2261 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
2262 #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
2263  
2264 /*!< SWJ_CFG configuration */
2265 #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2266 #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2267 #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2268 #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
2269  
2270 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
2271 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2272 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
2273 #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
2274  
2275 #ifdef STM32F10X_CL
2276 /*!< ETH_REMAP configuration */
2277 #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
2278  
2279 /*!< CAN2_REMAP configuration */
2280 #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
2281  
2282 /*!< MII_RMII_SEL configuration */
2283 #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
2284  
2285 /*!< SPI3_REMAP configuration */
2286 #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */
2287  
2288 /*!< TIM2ITR1_IREMAP configuration */
2289 #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
2290  
2291 /*!< PTP_PPS_REMAP configuration */
2292 #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
2293 #endif
2294  
2295 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2296 #define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
2297 #define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
2298 #define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
2299 #define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
2300  
2301 /*!< EXTI0 configuration */
2302 #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
2303 #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
2304 #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
2305 #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
2306 #define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
2307 #define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
2308 #define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
2309  
2310 /*!< EXTI1 configuration */
2311 #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
2312 #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
2313 #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
2314 #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
2315 #define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
2316 #define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
2317 #define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
2318  
2319 /*!< EXTI2 configuration */
2320 #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
2321 #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
2322 #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
2323 #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
2324 #define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
2325 #define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
2326 #define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
2327  
2328 /*!< EXTI3 configuration */
2329 #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
2330 #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
2331 #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
2332 #define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
2333 #define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
2334 #define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
2335 #define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
2336  
2337 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2338 #define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
2339 #define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
2340 #define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
2341 #define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
2342  
2343 /*!< EXTI4 configuration */
2344 #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
2345 #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
2346 #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
2347 #define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
2348 #define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
2349 #define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
2350 #define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
2351  
2352 /* EXTI5 configuration */
2353 #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
2354 #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
2355 #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
2356 #define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
2357 #define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
2358 #define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
2359 #define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
2360  
2361 /*!< EXTI6 configuration */
2362 #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
2363 #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
2364 #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
2365 #define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
2366 #define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
2367 #define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
2368 #define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
2369  
2370 /*!< EXTI7 configuration */
2371 #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
2372 #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
2373 #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
2374 #define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
2375 #define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
2376 #define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
2377 #define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
2378  
2379 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2380 #define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
2381 #define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
2382 #define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
2383 #define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
2384  
2385 /*!< EXTI8 configuration */
2386 #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
2387 #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
2388 #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
2389 #define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
2390 #define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
2391 #define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
2392 #define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
2393  
2394 /*!< EXTI9 configuration */
2395 #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
2396 #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
2397 #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
2398 #define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
2399 #define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
2400 #define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
2401 #define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
2402  
2403 /*!< EXTI10 configuration */
2404 #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
2405 #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
2406 #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
2407 #define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
2408 #define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
2409 #define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
2410 #define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
2411  
2412 /*!< EXTI11 configuration */
2413 #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
2414 #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
2415 #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
2416 #define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
2417 #define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
2418 #define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
2419 #define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
2420  
2421 /***************** Bit definition for AFIO_EXTICR4 register *****************/
2422 #define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
2423 #define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
2424 #define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
2425 #define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
2426  
2427 /* EXTI12 configuration */
2428 #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
2429 #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
2430 #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
2431 #define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
2432 #define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
2433 #define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
2434 #define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
2435  
2436 /* EXTI13 configuration */
2437 #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
2438 #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
2439 #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
2440 #define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
2441 #define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
2442 #define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
2443 #define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
2444  
2445 /*!< EXTI14 configuration */
2446 #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
2447 #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
2448 #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
2449 #define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
2450 #define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
2451 #define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
2452 #define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
2453  
2454 /*!< EXTI15 configuration */
2455 #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
2456 #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
2457 #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
2458 #define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
2459 #define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
2460 #define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
2461 #define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
2462  
2463 /******************************************************************************/
2464 /* */
2465 /* SystemTick */
2466 /* */
2467 /******************************************************************************/
2468  
2469 /***************** Bit definition for SysTick_CTRL register *****************/
2470 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
2471 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
2472 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
2473 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
2474  
2475 /***************** Bit definition for SysTick_LOAD register *****************/
2476 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
2477  
2478 /***************** Bit definition for SysTick_VAL register ******************/
2479 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
2480  
2481 /***************** Bit definition for SysTick_CALIB register ****************/
2482 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
2483 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
2484 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
2485  
2486 /******************************************************************************/
2487 /* */
2488 /* Nested Vectored Interrupt Controller */
2489 /* */
2490 /******************************************************************************/
2491  
2492 /****************** Bit definition for NVIC_ISER register *******************/
2493 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
2494 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
2495 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
2496 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
2497 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
2498 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
2499 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
2500 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
2501 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
2502 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
2503 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
2504 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
2505 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
2506 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
2507 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
2508 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
2509 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
2510 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
2511 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
2512 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
2513 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
2514 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
2515 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
2516 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
2517 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
2518 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
2519 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
2520 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
2521 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
2522 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
2523 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
2524 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
2525 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
2526  
2527 /****************** Bit definition for NVIC_ICER register *******************/
2528 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
2529 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
2530 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
2531 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
2532 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
2533 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
2534 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
2535 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
2536 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
2537 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
2538 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
2539 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
2540 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
2541 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
2542 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
2543 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
2544 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
2545 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
2546 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
2547 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
2548 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
2549 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
2550 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
2551 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
2552 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
2553 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
2554 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
2555 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
2556 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
2557 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
2558 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
2559 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
2560 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
2561  
2562 /****************** Bit definition for NVIC_ISPR register *******************/
2563 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
2564 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
2565 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
2566 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
2567 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
2568 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
2569 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
2570 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
2571 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
2572 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
2573 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
2574 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
2575 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
2576 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
2577 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
2578 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
2579 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
2580 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
2581 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
2582 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
2583 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
2584 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
2585 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
2586 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
2587 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
2588 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
2589 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
2590 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
2591 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
2592 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
2593 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
2594 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
2595 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
2596  
2597 /****************** Bit definition for NVIC_ICPR register *******************/
2598 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
2599 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
2600 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
2601 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
2602 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
2603 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
2604 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
2605 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
2606 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
2607 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
2608 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
2609 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
2610 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
2611 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
2612 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
2613 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
2614 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
2615 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
2616 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
2617 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
2618 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
2619 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
2620 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
2621 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
2622 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
2623 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
2624 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
2625 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
2626 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
2627 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
2628 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
2629 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
2630 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
2631  
2632 /****************** Bit definition for NVIC_IABR register *******************/
2633 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
2634 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
2635 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
2636 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
2637 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
2638 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
2639 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
2640 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
2641 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
2642 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
2643 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
2644 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
2645 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
2646 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
2647 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
2648 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
2649 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
2650 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
2651 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
2652 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
2653 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
2654 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
2655 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
2656 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
2657 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
2658 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
2659 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
2660 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
2661 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
2662 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
2663 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
2664 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
2665 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
2666  
2667 /****************** Bit definition for NVIC_PRI0 register *******************/
2668 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
2669 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
2670 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
2671 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
2672  
2673 /****************** Bit definition for NVIC_PRI1 register *******************/
2674 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
2675 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
2676 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
2677 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
2678  
2679 /****************** Bit definition for NVIC_PRI2 register *******************/
2680 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
2681 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
2682 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
2683 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
2684  
2685 /****************** Bit definition for NVIC_PRI3 register *******************/
2686 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
2687 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
2688 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
2689 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
2690  
2691 /****************** Bit definition for NVIC_PRI4 register *******************/
2692 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
2693 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
2694 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
2695 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
2696  
2697 /****************** Bit definition for NVIC_PRI5 register *******************/
2698 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
2699 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
2700 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
2701 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
2702  
2703 /****************** Bit definition for NVIC_PRI6 register *******************/
2704 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
2705 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
2706 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
2707 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
2708  
2709 /****************** Bit definition for NVIC_PRI7 register *******************/
2710 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
2711 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
2712 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
2713 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
2714  
2715 /****************** Bit definition for SCB_CPUID register *******************/
2716 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
2717 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
2718 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
2719 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
2720 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
2721  
2722 /******************* Bit definition for SCB_ICSR register *******************/
2723 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
2724 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
2725 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
2726 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
2727 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
2728 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
2729 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
2730 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
2731 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
2732 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
2733  
2734 /******************* Bit definition for SCB_VTOR register *******************/
2735 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
2736 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
2737  
2738 /*!<***************** Bit definition for SCB_AIRCR register *******************/
2739 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
2740 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
2741 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
2742  
2743 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
2744 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2745 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2746 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
2747  
2748 /* prority group configuration */
2749 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
2750 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
2751 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
2752 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
2753 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
2754 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
2755 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
2756 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
2757  
2758 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
2759 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
2760  
2761 /******************* Bit definition for SCB_SCR register ********************/
2762 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
2763 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
2764 #define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
2765  
2766 /******************** Bit definition for SCB_CCR register *******************/
2767 #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
2768 #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
2769 #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
2770 #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
2771 #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
2772 #define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
2773  
2774 /******************* Bit definition for SCB_SHPR register ********************/
2775 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
2776 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
2777 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
2778 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
2779  
2780 /****************** Bit definition for SCB_SHCSR register *******************/
2781 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
2782 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
2783 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
2784 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
2785 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
2786 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
2787 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
2788 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
2789 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
2790 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
2791 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
2792 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
2793 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
2794 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
2795  
2796 /******************* Bit definition for SCB_CFSR register *******************/
2797 /*!< MFSR */
2798 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
2799 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
2800 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
2801 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
2802 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
2803 /*!< BFSR */
2804 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
2805 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
2806 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
2807 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
2808 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
2809 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
2810 /*!< UFSR */
2811 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
2812 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
2813 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
2814 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
2815 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
2816 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
2817  
2818 /******************* Bit definition for SCB_HFSR register *******************/
2819 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
2820 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
2821 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
2822  
2823 /******************* Bit definition for SCB_DFSR register *******************/
2824 #define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
2825 #define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
2826 #define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
2827 #define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
2828 #define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
2829  
2830 /******************* Bit definition for SCB_MMFAR register ******************/
2831 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
2832  
2833 /******************* Bit definition for SCB_BFAR register *******************/
2834 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
2835  
2836 /******************* Bit definition for SCB_afsr register *******************/
2837 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
2838  
2839 /******************************************************************************/
2840 /* */
2841 /* External Interrupt/Event Controller */
2842 /* */
2843 /******************************************************************************/
2844  
2845 /******************* Bit definition for EXTI_IMR register *******************/
2846 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
2847 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
2848 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
2849 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
2850 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
2851 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
2852 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
2853 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
2854 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
2855 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
2856 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
2857 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
2858 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
2859 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
2860 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
2861 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
2862 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
2863 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
2864 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
2865 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
2866  
2867 /******************* Bit definition for EXTI_EMR register *******************/
2868 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
2869 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
2870 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
2871 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
2872 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
2873 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
2874 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
2875 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
2876 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
2877 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
2878 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
2879 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
2880 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
2881 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
2882 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
2883 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
2884 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
2885 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
2886 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
2887 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
2888  
2889 /****************** Bit definition for EXTI_RTSR register *******************/
2890 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
2891 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
2892 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
2893 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
2894 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
2895 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
2896 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
2897 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
2898 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
2899 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
2900 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
2901 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
2902 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
2903 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
2904 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
2905 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
2906 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
2907 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
2908 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
2909 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
2910  
2911 /****************** Bit definition for EXTI_FTSR register *******************/
2912 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
2913 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
2914 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
2915 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
2916 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
2917 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
2918 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
2919 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
2920 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
2921 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
2922 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
2923 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
2924 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
2925 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
2926 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
2927 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
2928 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
2929 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
2930 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
2931 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
2932  
2933 /****************** Bit definition for EXTI_SWIER register ******************/
2934 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
2935 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
2936 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
2937 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
2938 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
2939 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
2940 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
2941 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
2942 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
2943 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
2944 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
2945 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
2946 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
2947 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
2948 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
2949 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
2950 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
2951 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
2952 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
2953 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
2954  
2955 /******************* Bit definition for EXTI_PR register ********************/
2956 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
2957 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
2958 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
2959 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
2960 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
2961 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
2962 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
2963 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
2964 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
2965 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
2966 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
2967 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
2968 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
2969 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
2970 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
2971 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
2972 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
2973 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
2974 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
2975 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
2976  
2977 /******************************************************************************/
2978 /* */
2979 /* DMA Controller */
2980 /* */
2981 /******************************************************************************/
2982  
2983 /******************* Bit definition for DMA_ISR register ********************/
2984 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
2985 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
2986 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
2987 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
2988 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
2989 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
2990 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
2991 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
2992 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
2993 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
2994 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
2995 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
2996 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
2997 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
2998 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
2999 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
3000 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
3001 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
3002 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
3003 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
3004 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
3005 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
3006 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
3007 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
3008 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
3009 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
3010 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
3011 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
3012  
3013 /******************* Bit definition for DMA_IFCR register *******************/
3014 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
3015 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
3016 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
3017 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
3018 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
3019 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
3020 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
3021 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
3022 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
3023 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
3024 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
3025 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
3026 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
3027 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
3028 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
3029 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
3030 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
3031 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
3032 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
3033 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
3034 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
3035 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
3036 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
3037 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
3038 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
3039 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
3040 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
3041 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
3042  
3043 /******************* Bit definition for DMA_CCR1 register *******************/
3044 #define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
3045 #define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
3046 #define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
3047 #define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
3048 #define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
3049 #define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
3050 #define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
3051 #define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
3052  
3053 #define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
3054 #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
3055 #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
3056  
3057 #define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
3058 #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
3059 #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
3060  
3061 #define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
3062 #define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
3063 #define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
3064  
3065 #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
3066  
3067 /******************* Bit definition for DMA_CCR2 register *******************/
3068 #define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
3069 #define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
3070 #define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
3071 #define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
3072 #define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
3073 #define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
3074 #define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
3075 #define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
3076  
3077 #define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
3078 #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
3079 #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
3080  
3081 #define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
3082 #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
3083 #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
3084  
3085 #define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
3086 #define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
3087 #define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
3088  
3089 #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
3090  
3091 /******************* Bit definition for DMA_CCR3 register *******************/
3092 #define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
3093 #define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
3094 #define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
3095 #define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
3096 #define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
3097 #define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
3098 #define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
3099 #define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
3100  
3101 #define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
3102 #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
3103 #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
3104  
3105 #define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
3106 #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
3107 #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
3108  
3109 #define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
3110 #define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
3111 #define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
3112  
3113 #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
3114  
3115 /*!<****************** Bit definition for DMA_CCR4 register *******************/
3116 #define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */
3117 #define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
3118 #define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
3119 #define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
3120 #define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
3121 #define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */
3122 #define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
3123 #define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
3124  
3125 #define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
3126 #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
3127 #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
3128  
3129 #define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
3130 #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
3131 #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
3132  
3133 #define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
3134 #define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
3135 #define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
3136  
3137 #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
3138  
3139 /****************** Bit definition for DMA_CCR5 register *******************/
3140 #define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */
3141 #define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
3142 #define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
3143 #define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
3144 #define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
3145 #define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */
3146 #define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
3147 #define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
3148  
3149 #define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
3150 #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
3151 #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
3152  
3153 #define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
3154 #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
3155 #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
3156  
3157 #define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
3158 #define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
3159 #define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
3160  
3161 #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
3162  
3163 /******************* Bit definition for DMA_CCR6 register *******************/
3164 #define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */
3165 #define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
3166 #define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
3167 #define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
3168 #define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
3169 #define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */
3170 #define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
3171 #define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
3172  
3173 #define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
3174 #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
3175 #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
3176  
3177 #define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
3178 #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
3179 #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
3180  
3181 #define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
3182 #define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
3183 #define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
3184  
3185 #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
3186  
3187 /******************* Bit definition for DMA_CCR7 register *******************/
3188 #define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */
3189 #define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
3190 #define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
3191 #define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
3192 #define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
3193 #define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */
3194 #define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
3195 #define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
3196  
3197 #define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
3198 #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
3199 #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
3200  
3201 #define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
3202 #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
3203 #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
3204  
3205 #define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
3206 #define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
3207 #define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
3208  
3209 #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
3210  
3211 /****************** Bit definition for DMA_CNDTR1 register ******************/
3212 #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3213  
3214 /****************** Bit definition for DMA_CNDTR2 register ******************/
3215 #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3216  
3217 /****************** Bit definition for DMA_CNDTR3 register ******************/
3218 #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3219  
3220 /****************** Bit definition for DMA_CNDTR4 register ******************/
3221 #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3222  
3223 /****************** Bit definition for DMA_CNDTR5 register ******************/
3224 #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3225  
3226 /****************** Bit definition for DMA_CNDTR6 register ******************/
3227 #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3228  
3229 /****************** Bit definition for DMA_CNDTR7 register ******************/
3230 #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3231  
3232 /****************** Bit definition for DMA_CPAR1 register *******************/
3233 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3234  
3235 /****************** Bit definition for DMA_CPAR2 register *******************/
3236 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3237  
3238 /****************** Bit definition for DMA_CPAR3 register *******************/
3239 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3240  
3241  
3242 /****************** Bit definition for DMA_CPAR4 register *******************/
3243 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3244  
3245 /****************** Bit definition for DMA_CPAR5 register *******************/
3246 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3247  
3248 /****************** Bit definition for DMA_CPAR6 register *******************/
3249 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3250  
3251  
3252 /****************** Bit definition for DMA_CPAR7 register *******************/
3253 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3254  
3255 /****************** Bit definition for DMA_CMAR1 register *******************/
3256 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3257  
3258 /****************** Bit definition for DMA_CMAR2 register *******************/
3259 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3260  
3261 /****************** Bit definition for DMA_CMAR3 register *******************/
3262 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3263  
3264  
3265 /****************** Bit definition for DMA_CMAR4 register *******************/
3266 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3267  
3268 /****************** Bit definition for DMA_CMAR5 register *******************/
3269 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3270  
3271 /****************** Bit definition for DMA_CMAR6 register *******************/
3272 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3273  
3274 /****************** Bit definition for DMA_CMAR7 register *******************/
3275 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3276  
3277 /******************************************************************************/
3278 /* */
3279 /* Analog to Digital Converter */
3280 /* */
3281 /******************************************************************************/
3282  
3283 /******************** Bit definition for ADC_SR register ********************/
3284 #define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
3285 #define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
3286 #define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
3287 #define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
3288 #define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
3289  
3290 /******************* Bit definition for ADC_CR1 register ********************/
3291 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
3292 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3293 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3294 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3295 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3296 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3297  
3298 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
3299 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
3300 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
3301 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
3302 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
3303 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
3304 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
3305 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
3306  
3307 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
3308 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3309 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3310 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3311  
3312 #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */
3313 #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3314 #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3315 #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3316 #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3317  
3318 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
3319 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
3320  
3321  
3322 /******************* Bit definition for ADC_CR2 register ********************/
3323 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
3324 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
3325 #define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */
3326 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */
3327 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
3328 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
3329  
3330 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */
3331 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3332 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3333 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3334  
3335 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */
3336  
3337 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */
3338 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3339 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3340 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3341  
3342 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */
3343 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */
3344 #define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */
3345 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
3346  
3347 /****************** Bit definition for ADC_SMPR1 register *******************/
3348 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
3349 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3350 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3351 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3352  
3353 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
3354 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3355 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3356 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
3357  
3358 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
3359 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
3360 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
3361 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
3362  
3363 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
3364 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3365 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3366 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3367  
3368 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
3369 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3370 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3371 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3372  
3373 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
3374 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3375 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3376 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3377  
3378 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
3379 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
3380 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
3381 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
3382  
3383 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
3384 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
3385 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
3386 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
3387  
3388 /****************** Bit definition for ADC_SMPR2 register *******************/
3389 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
3390 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3391 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3392 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3393  
3394 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
3395 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3396 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3397 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
3398  
3399 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
3400 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
3401 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
3402 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
3403  
3404 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
3405 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3406 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3407 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3408  
3409 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
3410 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3411 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3412 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3413  
3414 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
3415 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3416 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3417 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3418  
3419 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
3420 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
3421 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
3422 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
3423  
3424 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
3425 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
3426 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
3427 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
3428  
3429 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
3430 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3431 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3432 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3433  
3434 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
3435 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
3436 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
3437 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
3438  
3439 /****************** Bit definition for ADC_JOFR1 register *******************/
3440 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
3441  
3442 /****************** Bit definition for ADC_JOFR2 register *******************/
3443 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
3444  
3445 /****************** Bit definition for ADC_JOFR3 register *******************/
3446 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
3447  
3448 /****************** Bit definition for ADC_JOFR4 register *******************/
3449 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
3450  
3451 /******************* Bit definition for ADC_HTR register ********************/
3452 #define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
3453  
3454 /******************* Bit definition for ADC_LTR register ********************/
3455 #define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
3456  
3457 /******************* Bit definition for ADC_SQR1 register *******************/
3458 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
3459 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3460 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3461 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3462 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3463 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3464  
3465 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
3466 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3467 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3468 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3469 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
3470 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
3471  
3472 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
3473 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3474 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3475 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
3476 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
3477 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
3478  
3479 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
3480 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3481 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3482 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3483 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
3484 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
3485  
3486 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
3487 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3488 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3489 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3490 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3491  
3492 /******************* Bit definition for ADC_SQR2 register *******************/
3493 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
3494 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3495 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3496 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3497 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3498 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3499  
3500 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
3501 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3502 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3503 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3504 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
3505 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
3506  
3507 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
3508 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3509 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3510 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
3511 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
3512 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
3513  
3514 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
3515 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3516 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3517 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3518 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
3519 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
3520  
3521 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
3522 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3523 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3524 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3525 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3526 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
3527  
3528 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
3529 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
3530 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
3531 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
3532 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
3533 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
3534  
3535 /******************* Bit definition for ADC_SQR3 register *******************/
3536 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
3537 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3538 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3539 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3540 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3541 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3542  
3543 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
3544 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3545 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3546 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3547 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
3548 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
3549  
3550 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
3551 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3552 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3553 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
3554 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
3555 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
3556  
3557 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
3558 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3559 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3560 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3561 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
3562 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
3563  
3564 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
3565 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3566 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3567 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3568 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3569 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
3570  
3571 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
3572 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
3573 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
3574 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
3575 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
3576 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
3577  
3578 /******************* Bit definition for ADC_JSQR register *******************/
3579 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
3580 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3581 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3582 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3583 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3584 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3585  
3586 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
3587 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3588 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3589 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3590 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
3591 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
3592  
3593 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
3594 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3595 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3596 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
3597 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
3598 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
3599  
3600 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
3601 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3602 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3603 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3604 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
3605 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
3606  
3607 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
3608 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3609 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3610  
3611 /******************* Bit definition for ADC_JDR1 register *******************/
3612 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
3613  
3614 /******************* Bit definition for ADC_JDR2 register *******************/
3615 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
3616  
3617 /******************* Bit definition for ADC_JDR3 register *******************/
3618 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
3619  
3620 /******************* Bit definition for ADC_JDR4 register *******************/
3621 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
3622  
3623 /******************** Bit definition for ADC_DR register ********************/
3624 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
3625 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
3626  
3627 /******************************************************************************/
3628 /* */
3629 /* Digital to Analog Converter */
3630 /* */
3631 /******************************************************************************/
3632  
3633 /******************** Bit definition for DAC_CR register ********************/
3634 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
3635 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
3636 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
3637  
3638 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
3639 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3640 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3641 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
3642  
3643 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3644 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
3645 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
3646  
3647 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3648 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3649 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3650 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3651 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3652  
3653 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
3654 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
3655 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
3656 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
3657  
3658 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3659 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
3660 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
3661 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
3662  
3663 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3664 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
3665 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
3666  
3667 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3668 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3669 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3670 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3671 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3672  
3673 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
3674  
3675 /***************** Bit definition for DAC_SWTRIGR register ******************/
3676 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
3677 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
3678  
3679 /***************** Bit definition for DAC_DHR12R1 register ******************/
3680 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
3681  
3682 /***************** Bit definition for DAC_DHR12L1 register ******************/
3683 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
3684  
3685 /****************** Bit definition for DAC_DHR8R1 register ******************/
3686 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
3687  
3688 /***************** Bit definition for DAC_DHR12R2 register ******************/
3689 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
3690  
3691 /***************** Bit definition for DAC_DHR12L2 register ******************/
3692 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
3693  
3694 /****************** Bit definition for DAC_DHR8R2 register ******************/
3695 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
3696  
3697 /***************** Bit definition for DAC_DHR12RD register ******************/
3698 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
3699 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
3700  
3701 /***************** Bit definition for DAC_DHR12LD register ******************/
3702 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
3703 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
3704  
3705 /****************** Bit definition for DAC_DHR8RD register ******************/
3706 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
3707 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
3708  
3709 /******************* Bit definition for DAC_DOR1 register *******************/
3710 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
3711  
3712 /******************* Bit definition for DAC_DOR2 register *******************/
3713 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
3714  
3715 /******************************************************************************/
3716 /* */
3717 /* TIM */
3718 /* */
3719 /******************************************************************************/
3720  
3721 /******************* Bit definition for TIM_CR1 register ********************/
3722 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
3723 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
3724 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
3725 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
3726 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
3727  
3728 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
3729 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
3730 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
3731  
3732 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
3733  
3734 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
3735 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
3736 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
3737  
3738 /******************* Bit definition for TIM_CR2 register ********************/
3739 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
3740 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
3741 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
3742  
3743 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
3744 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
3745 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
3746 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
3747  
3748 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
3749 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
3750 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
3751 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
3752 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
3753 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
3754 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
3755 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
3756  
3757 /******************* Bit definition for TIM_SMCR register *******************/
3758 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
3759 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
3760 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
3761 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
3762  
3763 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
3764 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
3765 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
3766 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
3767  
3768 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
3769  
3770 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
3771 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
3772 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
3773 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
3774 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
3775  
3776 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
3777 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
3778 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
3779  
3780 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
3781 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
3782  
3783 /******************* Bit definition for TIM_DIER register *******************/
3784 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
3785 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
3786 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
3787 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
3788 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
3789 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
3790 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
3791 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
3792 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
3793 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
3794 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
3795 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
3796 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
3797 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
3798 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
3799  
3800 /******************** Bit definition for TIM_SR register ********************/
3801 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
3802 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
3803 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
3804 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
3805 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
3806 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
3807 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
3808 #define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
3809 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
3810 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
3811 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
3812 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
3813  
3814 /******************* Bit definition for TIM_EGR register ********************/
3815 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
3816 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
3817 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
3818 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
3819 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
3820 #define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
3821 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
3822 #define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
3823  
3824 /****************** Bit definition for TIM_CCMR1 register *******************/
3825 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
3826 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
3827 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
3828  
3829 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
3830 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
3831  
3832 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
3833 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
3834 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
3835 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
3836  
3837 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
3838  
3839 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
3840 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
3841 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
3842  
3843 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
3844 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
3845  
3846 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
3847 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
3848 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
3849 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
3850  
3851 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
3852  
3853 /*----------------------------------------------------------------------------*/
3854  
3855 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
3856 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
3857 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
3858  
3859 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
3860 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
3861 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
3862 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
3863 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
3864  
3865 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
3866 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
3867 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
3868  
3869 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
3870 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
3871 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
3872 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
3873 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
3874  
3875 /****************** Bit definition for TIM_CCMR2 register *******************/
3876 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
3877 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
3878 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
3879  
3880 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
3881 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
3882  
3883 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
3884 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
3885 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
3886 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
3887  
3888 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
3889  
3890 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
3891 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
3892 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
3893  
3894 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
3895 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
3896  
3897 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
3898 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
3899 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
3900 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
3901  
3902 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
3903  
3904 /*----------------------------------------------------------------------------*/
3905  
3906 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
3907 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
3908 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
3909  
3910 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
3911 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
3912 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
3913 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
3914 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
3915  
3916 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
3917 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
3918 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
3919  
3920 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
3921 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
3922 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
3923 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
3924 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
3925  
3926 /******************* Bit definition for TIM_CCER register *******************/
3927 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
3928 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
3929 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
3930 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
3931 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
3932 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
3933 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
3934 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
3935 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
3936 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
3937 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
3938 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
3939 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
3940 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
3941  
3942 /******************* Bit definition for TIM_CNT register ********************/
3943 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
3944  
3945 /******************* Bit definition for TIM_PSC register ********************/
3946 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
3947  
3948 /******************* Bit definition for TIM_ARR register ********************/
3949 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
3950  
3951 /******************* Bit definition for TIM_RCR register ********************/
3952 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
3953  
3954 /******************* Bit definition for TIM_CCR1 register *******************/
3955 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
3956  
3957 /******************* Bit definition for TIM_CCR2 register *******************/
3958 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
3959  
3960 /******************* Bit definition for TIM_CCR3 register *******************/
3961 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
3962  
3963 /******************* Bit definition for TIM_CCR4 register *******************/
3964 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
3965  
3966 /******************* Bit definition for TIM_BDTR register *******************/
3967 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
3968 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
3969 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
3970 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
3971 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
3972 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
3973 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
3974 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
3975 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
3976  
3977 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
3978 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
3979 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
3980  
3981 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
3982 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
3983 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
3984 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
3985 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
3986 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
3987  
3988 /******************* Bit definition for TIM_DCR register ********************/
3989 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
3990 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
3991 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
3992 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
3993 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
3994 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
3995  
3996 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
3997 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
3998 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
3999 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
4000 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
4001 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
4002  
4003 /******************* Bit definition for TIM_DMAR register *******************/
4004 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
4005  
4006 /******************************************************************************/
4007 /* */
4008 /* Real-Time Clock */
4009 /* */
4010 /******************************************************************************/
4011  
4012 /******************* Bit definition for RTC_CRH register ********************/
4013 #define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */
4014 #define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */
4015 #define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */
4016  
4017 /******************* Bit definition for RTC_CRL register ********************/
4018 #define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */
4019 #define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */
4020 #define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */
4021 #define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */
4022 #define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */
4023 #define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */
4024  
4025 /******************* Bit definition for RTC_PRLH register *******************/
4026 #define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */
4027  
4028 /******************* Bit definition for RTC_PRLL register *******************/
4029 #define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */
4030  
4031 /******************* Bit definition for RTC_DIVH register *******************/
4032 #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */
4033  
4034 /******************* Bit definition for RTC_DIVL register *******************/
4035 #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */
4036  
4037 /******************* Bit definition for RTC_CNTH register *******************/
4038 #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */
4039  
4040 /******************* Bit definition for RTC_CNTL register *******************/
4041 #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */
4042  
4043 /******************* Bit definition for RTC_ALRH register *******************/
4044 #define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */
4045  
4046 /******************* Bit definition for RTC_ALRL register *******************/
4047 #define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */
4048  
4049 /******************************************************************************/
4050 /* */
4051 /* Independent WATCHDOG */
4052 /* */
4053 /******************************************************************************/
4054  
4055 /******************* Bit definition for IWDG_KR register ********************/
4056 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
4057  
4058 /******************* Bit definition for IWDG_PR register ********************/
4059 #define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
4060 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
4061 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
4062 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
4063  
4064 /******************* Bit definition for IWDG_RLR register *******************/
4065 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
4066  
4067 /******************* Bit definition for IWDG_SR register ********************/
4068 #define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
4069 #define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
4070  
4071 /******************************************************************************/
4072 /* */
4073 /* Window WATCHDOG */
4074 /* */
4075 /******************************************************************************/
4076  
4077 /******************* Bit definition for WWDG_CR register ********************/
4078 #define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
4079 #define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
4080 #define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
4081 #define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
4082 #define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
4083 #define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
4084 #define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
4085 #define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
4086  
4087 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
4088  
4089 /******************* Bit definition for WWDG_CFR register *******************/
4090 #define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
4091 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
4092 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
4093 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
4094 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
4095 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
4096 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
4097 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
4098  
4099 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
4100 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
4101 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
4102  
4103 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
4104  
4105 /******************* Bit definition for WWDG_SR register ********************/
4106 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
4107  
4108 /******************************************************************************/
4109 /* */
4110 /* Flexible Static Memory Controller */
4111 /* */
4112 /******************************************************************************/
4113  
4114 /****************** Bit definition for FSMC_BCR1 register *******************/
4115 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4116 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4117  
4118 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4119 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4120 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4121  
4122 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4123 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4124 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4125  
4126 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4127 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4128 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4129 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4130 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4131 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4132 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4133 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4134 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4135  
4136 /****************** Bit definition for FSMC_BCR2 register *******************/
4137 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4138 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4139  
4140 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4141 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4142 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4143  
4144 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4145 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4146 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4147  
4148 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4149 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4150 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4151 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4152 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4153 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4154 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4155 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4156 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4157  
4158 /****************** Bit definition for FSMC_BCR3 register *******************/
4159 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4160 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4161  
4162 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4163 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4164 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4165  
4166 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4167 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4168 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4169  
4170 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4171 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4172 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
4173 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4174 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4175 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4176 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4177 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4178 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4179  
4180 /****************** Bit definition for FSMC_BCR4 register *******************/
4181 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4182 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4183  
4184 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4185 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4186 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4187  
4188 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4189 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4190 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4191  
4192 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4193 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4194 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4195 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4196 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4197 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4198 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4199 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4200 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4201  
4202 /****************** Bit definition for FSMC_BTR1 register ******************/
4203 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4204 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4205 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4206 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4207 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4208  
4209 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4210 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4211 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4212 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4213 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4214  
4215 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4216 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4217 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4218 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4219 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4220  
4221 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4222 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4223 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4224 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4225 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4226  
4227 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4228 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4229 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4230 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4231 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4232  
4233 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4234 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4235 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4236 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4237 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4238  
4239 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4240 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4241 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4242  
4243 /****************** Bit definition for FSMC_BTR2 register *******************/
4244 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4245 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4246 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4247 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4248 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4249  
4250 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4251 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4252 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4253 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4254 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4255  
4256 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4257 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4258 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4259 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4260 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4261  
4262 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4263 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4264 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4265 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4266 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4267  
4268 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4269 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4270 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4271 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4272 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4273  
4274 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4275 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4276 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4277 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4278 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4279  
4280 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4281 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4282 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4283  
4284 /******************* Bit definition for FSMC_BTR3 register *******************/
4285 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4286 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4287 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4288 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4289 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4290  
4291 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4292 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4293 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4294 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4295 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4296  
4297 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4298 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4299 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4300 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4301 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4302  
4303 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4304 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4305 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4306 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4307 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4308  
4309 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4310 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4311 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4312 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4313 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4314  
4315 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4316 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4317 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4318 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4319 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4320  
4321 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4322 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4323 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4324  
4325 /****************** Bit definition for FSMC_BTR4 register *******************/
4326 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4327 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4328 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4329 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4330 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4331  
4332 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4333 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4334 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4335 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4336 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4337  
4338 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4339 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4340 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4341 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4342 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4343  
4344 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4345 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4346 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4347 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4348 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4349  
4350 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4351 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4352 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4353 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4354 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4355  
4356 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4357 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4358 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4359 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4360 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4361  
4362 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4363 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4364 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4365  
4366 /****************** Bit definition for FSMC_BWTR1 register ******************/
4367 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4368 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4369 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4370 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4371 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4372  
4373 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4374 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4375 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4376 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4377 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4378  
4379 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4380 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4381 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4382 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4383 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4384  
4385 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4386 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4387 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4388 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4389 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4390  
4391 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4392 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4393 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4394 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4395 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4396  
4397 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4398 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4399 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4400  
4401 /****************** Bit definition for FSMC_BWTR2 register ******************/
4402 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4403 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4404 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4405 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4406 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4407  
4408 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4409 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4410 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4411 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4412 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4413  
4414 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4415 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4416 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4417 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4418 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4419  
4420 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4421 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4422 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
4423 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4424 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4425  
4426 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4427 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4428 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4429 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4430 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4431  
4432 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4433 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4434 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4435  
4436 /****************** Bit definition for FSMC_BWTR3 register ******************/
4437 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4438 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4439 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4440 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4441 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4442  
4443 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4444 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4445 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4446 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4447 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4448  
4449 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4450 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4451 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4452 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4453 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4454  
4455 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4456 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4457 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4458 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4459 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4460  
4461 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4462 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4463 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4464 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4465 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4466  
4467 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4468 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4469 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4470  
4471 /****************** Bit definition for FSMC_BWTR4 register ******************/
4472 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4473 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4474 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4475 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4476 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4477  
4478 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4479 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4480 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4481 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4482 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4483  
4484 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4485 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4486 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4487 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4488 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4489  
4490 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4491 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4492 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4493 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4494 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4495  
4496 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4497 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4498 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4499 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4500 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4501  
4502 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4503 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4504 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4505  
4506 /****************** Bit definition for FSMC_PCR2 register *******************/
4507 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4508 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4509 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4510  
4511 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4512 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4513 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4514  
4515 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4516  
4517 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4518 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4519 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4520 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4521 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4522  
4523 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4524 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4525 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4526 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4527 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4528  
4529 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
4530 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4531 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4532 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4533  
4534 /****************** Bit definition for FSMC_PCR3 register *******************/
4535 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4536 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4537 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4538  
4539 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4540 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4541 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4542  
4543 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4544  
4545 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4546 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4547 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4548 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4549 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4550  
4551 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4552 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4553 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4554 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4555 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4556  
4557 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4558 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4559 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4560 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4561  
4562 /****************** Bit definition for FSMC_PCR4 register *******************/
4563 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4564 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4565 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4566  
4567 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4568 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4569 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4570  
4571 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4572  
4573 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4574 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4575 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4576 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4577 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4578  
4579 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4580 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4581 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4582 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4583 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4584  
4585 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4586 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4587 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4588 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4589  
4590 /******************* Bit definition for FSMC_SR2 register *******************/
4591 #define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
4592 #define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
4593 #define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
4594 #define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4595 #define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
4596 #define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4597 #define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
4598  
4599 /******************* Bit definition for FSMC_SR3 register *******************/
4600 #define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
4601 #define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
4602 #define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
4603 #define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4604 #define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
4605 #define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4606 #define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
4607  
4608 /******************* Bit definition for FSMC_SR4 register *******************/
4609 #define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
4610 #define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
4611 #define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
4612 #define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4613 #define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
4614 #define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4615 #define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
4616  
4617 /****************** Bit definition for FSMC_PMEM2 register ******************/
4618 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
4619 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4620 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4621 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4622 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4623 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4624 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4625 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4626 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4627  
4628 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
4629 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4630 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4631 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4632 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4633 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4634 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4635 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4636 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4637  
4638 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
4639 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4640 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4641 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4642 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4643 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4644 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4645 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4646 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4647  
4648 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
4649 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4650 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4651 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4652 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4653 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4654 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4655 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4656 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4657  
4658 /****************** Bit definition for FSMC_PMEM3 register ******************/
4659 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4660 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4661 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4662 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4663 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4664 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4665 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4666 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4667 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4668  
4669 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4670 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4671 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4672 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4673 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4674 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4675 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4676 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4677 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4678  
4679 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4680 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4681 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4682 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4683 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4684 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4685 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4686 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4687 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4688  
4689 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4690 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4691 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4692 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4693 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4694 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4695 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4696 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4697 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4698  
4699 /****************** Bit definition for FSMC_PMEM4 register ******************/
4700 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
4701 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4702 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4703 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4704 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4705 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4706 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4707 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4708 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4709  
4710 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
4711 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4712 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4713 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4714 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4715 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4716 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4717 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4718 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4719  
4720 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
4721 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4722 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4723 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4724 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4725 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4726 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4727 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4728 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4729  
4730 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
4731 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4732 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4733 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4734 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4735 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4736 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4737 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4738 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4739  
4740 /****************** Bit definition for FSMC_PATT2 register ******************/
4741 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
4742 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4743 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4744 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4745 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4746 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4747 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4748 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4749 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4750  
4751 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
4752 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4753 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4754 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4755 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4756 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4757 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4758 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4759 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4760  
4761 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
4762 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4763 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4764 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4765 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4766 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4767 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4768 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4769 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4770  
4771 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
4772 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4773 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4774 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4775 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4776 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4777 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4778 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4779 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4780  
4781 /****************** Bit definition for FSMC_PATT3 register ******************/
4782 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4783 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4784 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4785 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4786 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4787 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4788 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4789 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4790 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4791  
4792 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4793 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4794 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4795 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4796 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4797 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4798 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4799 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4800 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4801  
4802 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4803 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4804 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4805 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4806 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4807 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4808 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4809 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4810 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4811  
4812 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4813 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4814 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4815 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4816 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4817 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4818 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4819 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4820 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4821  
4822 /****************** Bit definition for FSMC_PATT4 register ******************/
4823 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4824 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4825 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4826 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4827 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4828 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4829 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4830 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4831 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4832  
4833 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4834 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4835 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4836 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4837 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4838 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4839 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4840 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4841 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4842  
4843 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4844 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4845 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4846 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4847 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4848 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4849 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4850 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4851 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4852  
4853 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4854 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4855 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4856 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4857 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4858 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4859 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4860 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4861 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4862  
4863 /****************** Bit definition for FSMC_PIO4 register *******************/
4864 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
4865 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4866 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4867 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4868 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4869 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4870 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4871 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4872 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4873  
4874 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
4875 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4876 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4877 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4878 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4879 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4880 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4881 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4882 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4883  
4884 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
4885 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4886 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4887 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4888 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4889 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4890 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4891 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4892 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4893  
4894 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4895 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4896 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4897 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4898 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4899 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4900 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4901 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4902 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4903  
4904 /****************** Bit definition for FSMC_ECCR2 register ******************/
4905 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4906  
4907 /****************** Bit definition for FSMC_ECCR3 register ******************/
4908 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4909  
4910 /******************************************************************************/
4911 /* */
4912 /* SD host Interface */
4913 /* */
4914 /******************************************************************************/
4915  
4916 /****************** Bit definition for SDIO_POWER register ******************/
4917 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
4918 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
4919 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
4920  
4921 /****************** Bit definition for SDIO_CLKCR register ******************/
4922 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
4923 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
4924 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
4925 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
4926  
4927 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
4928 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
4929 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
4930  
4931 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
4932 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
4933  
4934 /******************* Bit definition for SDIO_ARG register *******************/
4935 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
4936  
4937 /******************* Bit definition for SDIO_CMD register *******************/
4938 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
4939  
4940 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
4941 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
4942 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
4943  
4944 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
4945 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
4946 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
4947 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
4948 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
4949 #define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
4950 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
4951  
4952 /***************** Bit definition for SDIO_RESPCMD register *****************/
4953 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
4954  
4955 /****************** Bit definition for SDIO_RESP0 register ******************/
4956 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
4957  
4958 /****************** Bit definition for SDIO_RESP1 register ******************/
4959 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
4960  
4961 /****************** Bit definition for SDIO_RESP2 register ******************/
4962 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
4963  
4964 /****************** Bit definition for SDIO_RESP3 register ******************/
4965 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
4966  
4967 /****************** Bit definition for SDIO_RESP4 register ******************/
4968 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
4969  
4970 /****************** Bit definition for SDIO_DTIMER register *****************/
4971 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
4972  
4973 /****************** Bit definition for SDIO_DLEN register *******************/
4974 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
4975  
4976 /****************** Bit definition for SDIO_DCTRL register ******************/
4977 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
4978 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
4979 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
4980 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
4981  
4982 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
4983 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
4984 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
4985 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
4986 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
4987  
4988 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
4989 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
4990 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
4991 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
4992  
4993 /****************** Bit definition for SDIO_DCOUNT register *****************/
4994 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
4995  
4996 /****************** Bit definition for SDIO_STA register ********************/
4997 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
4998 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
4999 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
5000 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
5001 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
5002 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
5003 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
5004 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
5005 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
5006 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
5007 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
5008 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
5009 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
5010 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
5011 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5012 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
5013 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
5014 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
5015 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
5016 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
5017 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
5018 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
5019 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
5020 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
5021  
5022 /******************* Bit definition for SDIO_ICR register *******************/
5023 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
5024 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
5025 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
5026 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
5027 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
5028 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
5029 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
5030 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
5031 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
5032 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
5033 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
5034 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
5035 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
5036  
5037 /****************** Bit definition for SDIO_MASK register *******************/
5038 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
5039 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
5040 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
5041 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
5042 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
5043 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
5044 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
5045 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
5046 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
5047 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
5048 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
5049 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
5050 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
5051 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
5052 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
5053 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
5054 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
5055 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
5056 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
5057 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
5058 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
5059 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
5060 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
5061 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
5062  
5063 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5064 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
5065  
5066 /****************** Bit definition for SDIO_FIFO register *******************/
5067 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
5068  
5069 /******************************************************************************/
5070 /* */
5071 /* USB Device FS */
5072 /* */
5073 /******************************************************************************/
5074  
5075 /*!<Endpoint-specific registers */
5076 /******************* Bit definition for USB_EP0R register *******************/
5077 #define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5078  
5079 #define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5080 #define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5081 #define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5082  
5083 #define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5084 #define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5085 #define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5086  
5087 #define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5088 #define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5089 #define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5090  
5091 #define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5092  
5093 #define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5094 #define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5095 #define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5096  
5097 #define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5098 #define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5099  
5100 /******************* Bit definition for USB_EP1R register *******************/
5101 #define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5102  
5103 #define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5104 #define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5105 #define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5106  
5107 #define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5108 #define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5109 #define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5110  
5111 #define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5112 #define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5113 #define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5114  
5115 #define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5116  
5117 #define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5118 #define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5119 #define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5120  
5121 #define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5122 #define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5123  
5124 /******************* Bit definition for USB_EP2R register *******************/
5125 #define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5126  
5127 #define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5128 #define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5129 #define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5130  
5131 #define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5132 #define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5133 #define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5134  
5135 #define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5136 #define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5137 #define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5138  
5139 #define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5140  
5141 #define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5142 #define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5143 #define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5144  
5145 #define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5146 #define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5147  
5148 /******************* Bit definition for USB_EP3R register *******************/
5149 #define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5150  
5151 #define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5152 #define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5153 #define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5154  
5155 #define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5156 #define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5157 #define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5158  
5159 #define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5160 #define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5161 #define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5162  
5163 #define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5164  
5165 #define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5166 #define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5167 #define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5168  
5169 #define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5170 #define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5171  
5172 /******************* Bit definition for USB_EP4R register *******************/
5173 #define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5174  
5175 #define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5176 #define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5177 #define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5178  
5179 #define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5180 #define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5181 #define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5182  
5183 #define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5184 #define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5185 #define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5186  
5187 #define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5188  
5189 #define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5190 #define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5191 #define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5192  
5193 #define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5194 #define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5195  
5196 /******************* Bit definition for USB_EP5R register *******************/
5197 #define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5198  
5199 #define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5200 #define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5201 #define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5202  
5203 #define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5204 #define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5205 #define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5206  
5207 #define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5208 #define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5209 #define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5210  
5211 #define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5212  
5213 #define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5214 #define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5215 #define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5216  
5217 #define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5218 #define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5219  
5220 /******************* Bit definition for USB_EP6R register *******************/
5221 #define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5222  
5223 #define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5224 #define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5225 #define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5226  
5227 #define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5228 #define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5229 #define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5230  
5231 #define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5232 #define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5233 #define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5234  
5235 #define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5236  
5237 #define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5238 #define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5239 #define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5240  
5241 #define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5242 #define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5243  
5244 /******************* Bit definition for USB_EP7R register *******************/
5245 #define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5246  
5247 #define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5248 #define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5249 #define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5250  
5251 #define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5252 #define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5253 #define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5254  
5255 #define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5256 #define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5257 #define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5258  
5259 #define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5260  
5261 #define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5262 #define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5263 #define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5264  
5265 #define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5266 #define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5267  
5268 /*!<Common registers */
5269 /******************* Bit definition for USB_CNTR register *******************/
5270 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
5271 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
5272 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
5273 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
5274 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
5275 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
5276 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
5277 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
5278 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
5279 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
5280 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
5281 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
5282 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
5283  
5284 /******************* Bit definition for USB_ISTR register *******************/
5285 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
5286 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
5287 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
5288 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
5289 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
5290 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
5291 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
5292 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
5293 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
5294 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
5295  
5296 /******************* Bit definition for USB_FNR register ********************/
5297 #define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
5298 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
5299 #define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
5300 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
5301 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
5302  
5303 /****************** Bit definition for USB_DADDR register *******************/
5304 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
5305 #define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
5306 #define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
5307 #define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
5308 #define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
5309 #define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
5310 #define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
5311 #define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
5312  
5313 #define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
5314  
5315 /****************** Bit definition for USB_BTABLE register ******************/
5316 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
5317  
5318 /*!<Buffer descriptor table */
5319 /***************** Bit definition for USB_ADDR0_TX register *****************/
5320 #define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */
5321  
5322 /***************** Bit definition for USB_ADDR1_TX register *****************/
5323 #define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */
5324  
5325 /***************** Bit definition for USB_ADDR2_TX register *****************/
5326 #define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */
5327  
5328 /***************** Bit definition for USB_ADDR3_TX register *****************/
5329 #define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */
5330  
5331 /***************** Bit definition for USB_ADDR4_TX register *****************/
5332 #define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */
5333  
5334 /***************** Bit definition for USB_ADDR5_TX register *****************/
5335 #define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */
5336  
5337 /***************** Bit definition for USB_ADDR6_TX register *****************/
5338 #define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */
5339  
5340 /***************** Bit definition for USB_ADDR7_TX register *****************/
5341 #define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */
5342  
5343 /*----------------------------------------------------------------------------*/
5344  
5345 /***************** Bit definition for USB_COUNT0_TX register ****************/
5346 #define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */
5347  
5348 /***************** Bit definition for USB_COUNT1_TX register ****************/
5349 #define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */
5350  
5351 /***************** Bit definition for USB_COUNT2_TX register ****************/
5352 #define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */
5353  
5354 /***************** Bit definition for USB_COUNT3_TX register ****************/
5355 #define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */
5356  
5357 /***************** Bit definition for USB_COUNT4_TX register ****************/
5358 #define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */
5359  
5360 /***************** Bit definition for USB_COUNT5_TX register ****************/
5361 #define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */
5362  
5363 /***************** Bit definition for USB_COUNT6_TX register ****************/
5364 #define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */
5365  
5366 /***************** Bit definition for USB_COUNT7_TX register ****************/
5367 #define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */
5368  
5369 /*----------------------------------------------------------------------------*/
5370  
5371 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
5372 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */
5373  
5374 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
5375 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */
5376  
5377 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
5378 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */
5379  
5380 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
5381 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */
5382  
5383 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
5384 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */
5385  
5386 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
5387 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */
5388  
5389 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
5390 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */
5391  
5392 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
5393 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */
5394  
5395 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
5396 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */
5397  
5398 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
5399 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */
5400  
5401 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
5402 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */
5403  
5404 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
5405 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */
5406  
5407 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
5408 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */
5409  
5410 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
5411 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */
5412  
5413 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
5414 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */
5415  
5416 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
5417 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */
5418  
5419 /*----------------------------------------------------------------------------*/
5420  
5421 /***************** Bit definition for USB_ADDR0_RX register *****************/
5422 #define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */
5423  
5424 /***************** Bit definition for USB_ADDR1_RX register *****************/
5425 #define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */
5426  
5427 /***************** Bit definition for USB_ADDR2_RX register *****************/
5428 #define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */
5429  
5430 /***************** Bit definition for USB_ADDR3_RX register *****************/
5431 #define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */
5432  
5433 /***************** Bit definition for USB_ADDR4_RX register *****************/
5434 #define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */
5435  
5436 /***************** Bit definition for USB_ADDR5_RX register *****************/
5437 #define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */
5438  
5439 /***************** Bit definition for USB_ADDR6_RX register *****************/
5440 #define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */
5441  
5442 /***************** Bit definition for USB_ADDR7_RX register *****************/
5443 #define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */
5444  
5445 /*----------------------------------------------------------------------------*/
5446  
5447 /***************** Bit definition for USB_COUNT0_RX register ****************/
5448 #define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5449  
5450 #define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5451 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5452 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5453 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5454 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5455 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5456  
5457 #define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5458  
5459 /***************** Bit definition for USB_COUNT1_RX register ****************/
5460 #define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5461  
5462 #define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5463 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5464 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5465 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5466 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5467 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5468  
5469 #define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5470  
5471 /***************** Bit definition for USB_COUNT2_RX register ****************/
5472 #define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5473  
5474 #define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5475 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5476 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5477 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5478 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5479 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5480  
5481 #define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5482  
5483 /***************** Bit definition for USB_COUNT3_RX register ****************/
5484 #define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5485  
5486 #define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5487 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5488 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5489 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5490 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5491 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5492  
5493 #define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5494  
5495 /***************** Bit definition for USB_COUNT4_RX register ****************/
5496 #define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5497  
5498 #define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5499 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5500 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5501 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5502 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5503 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5504  
5505 #define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5506  
5507 /***************** Bit definition for USB_COUNT5_RX register ****************/
5508 #define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5509  
5510 #define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5511 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5512 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5513 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5514 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5515 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5516  
5517 #define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5518  
5519 /***************** Bit definition for USB_COUNT6_RX register ****************/
5520 #define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5521  
5522 #define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5523 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5524 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5525 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5526 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5527 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5528  
5529 #define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5530  
5531 /***************** Bit definition for USB_COUNT7_RX register ****************/
5532 #define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5533  
5534 #define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5535 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5536 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5537 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5538 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5539 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5540  
5541 #define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5542  
5543 /*----------------------------------------------------------------------------*/
5544  
5545 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
5546 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
5547  
5548 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5549 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5550 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5551 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5552 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5553 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5554  
5555 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
5556  
5557 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
5558 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
5559  
5560 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5561 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */
5562 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
5563 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
5564 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
5565 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
5566  
5567 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
5568  
5569 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
5570 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
5571  
5572 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5573 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5574 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5575 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5576 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5577 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5578  
5579 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
5580  
5581 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
5582 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
5583  
5584 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5585 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
5586 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
5587 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
5588 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
5589 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
5590  
5591 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
5592  
5593 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
5594 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
5595  
5596 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5597 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5598 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5599 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5600 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5601 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5602  
5603 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
5604  
5605 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
5606 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
5607  
5608 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5609 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
5610 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
5611 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
5612 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
5613 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
5614  
5615 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
5616  
5617 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
5618 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
5619  
5620 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5621 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5622 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5623 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5624 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5625 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5626  
5627 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
5628  
5629 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
5630 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
5631  
5632 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5633 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
5634 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
5635 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
5636 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
5637 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
5638  
5639 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
5640  
5641 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
5642 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
5643  
5644 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5645 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5646 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5647 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5648 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5649 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5650  
5651 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
5652  
5653 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
5654 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
5655  
5656 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5657 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
5658 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
5659 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
5660 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
5661 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
5662  
5663 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
5664  
5665 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
5666 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
5667  
5668 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5669 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5670 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5671 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5672 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5673 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5674  
5675 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
5676  
5677 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
5678 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
5679  
5680 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5681 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
5682 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
5683 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
5684 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
5685 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
5686  
5687 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
5688  
5689 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
5690 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
5691  
5692 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5693 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5694 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5695 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5696 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5697 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5698  
5699 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
5700  
5701 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
5702 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
5703  
5704 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5705 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
5706 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
5707 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
5708 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
5709 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
5710  
5711 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
5712  
5713 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
5714 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
5715  
5716 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5717 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5718 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5719 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5720 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5721 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5722  
5723 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
5724  
5725 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
5726 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
5727  
5728 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5729 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
5730 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
5731 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
5732 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
5733 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
5734  
5735 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
5736  
5737 /******************************************************************************/
5738 /* */
5739 /* Controller Area Network */
5740 /* */
5741 /******************************************************************************/
5742  
5743 /*!<CAN control and status registers */
5744 /******************* Bit definition for CAN_MCR register ********************/
5745 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
5746 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
5747 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
5748 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
5749 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
5750 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
5751 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
5752 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
5753 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
5754  
5755 /******************* Bit definition for CAN_MSR register ********************/
5756 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
5757 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
5758 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
5759 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
5760 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
5761 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
5762 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
5763 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
5764 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
5765  
5766 /******************* Bit definition for CAN_TSR register ********************/
5767 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
5768 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
5769 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
5770 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
5771 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
5772 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
5773 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
5774 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
5775 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
5776 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
5777 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
5778 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
5779 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
5780 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
5781 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
5782 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
5783  
5784 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
5785 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
5786 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
5787 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
5788  
5789 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
5790 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
5791 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
5792 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
5793  
5794 /******************* Bit definition for CAN_RF0R register *******************/
5795 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
5796 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
5797 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
5798 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
5799  
5800 /******************* Bit definition for CAN_RF1R register *******************/
5801 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
5802 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
5803 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
5804 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
5805  
5806 /******************** Bit definition for CAN_IER register *******************/
5807 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
5808 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
5809 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
5810 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
5811 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
5812 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
5813 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
5814 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
5815 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
5816 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
5817 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
5818 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
5819 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
5820 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
5821  
5822 /******************** Bit definition for CAN_ESR register *******************/
5823 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
5824 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
5825 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
5826  
5827 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
5828 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5829 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5830 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5831  
5832 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
5833 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
5834  
5835 /******************* Bit definition for CAN_BTR register ********************/
5836 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
5837 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
5838 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
5839 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
5840 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
5841 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
5842  
5843 /*!<Mailbox registers */
5844 /****************** Bit definition for CAN_TI0R register ********************/
5845 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
5846 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5847 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5848 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
5849 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5850  
5851 /****************** Bit definition for CAN_TDT0R register *******************/
5852 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5853 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
5854 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5855  
5856 /****************** Bit definition for CAN_TDL0R register *******************/
5857 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5858 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5859 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5860 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5861  
5862 /****************** Bit definition for CAN_TDH0R register *******************/
5863 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5864 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5865 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5866 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5867  
5868 /******************* Bit definition for CAN_TI1R register *******************/
5869 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
5870 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5871 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5872 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
5873 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5874  
5875 /******************* Bit definition for CAN_TDT1R register ******************/
5876 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5877 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
5878 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5879  
5880 /******************* Bit definition for CAN_TDL1R register ******************/
5881 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5882 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5883 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5884 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5885  
5886 /******************* Bit definition for CAN_TDH1R register ******************/
5887 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5888 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5889 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5890 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5891  
5892 /******************* Bit definition for CAN_TI2R register *******************/
5893 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
5894 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5895 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5896 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
5897 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5898  
5899 /******************* Bit definition for CAN_TDT2R register ******************/
5900 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5901 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
5902 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5903  
5904 /******************* Bit definition for CAN_TDL2R register ******************/
5905 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5906 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5907 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5908 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5909  
5910 /******************* Bit definition for CAN_TDH2R register ******************/
5911 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5912 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5913 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5914 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5915  
5916 /******************* Bit definition for CAN_RI0R register *******************/
5917 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5918 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5919 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
5920 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5921  
5922 /******************* Bit definition for CAN_RDT0R register ******************/
5923 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5924 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
5925 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5926  
5927 /******************* Bit definition for CAN_RDL0R register ******************/
5928 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5929 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5930 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5931 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5932  
5933 /******************* Bit definition for CAN_RDH0R register ******************/
5934 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5935 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5936 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5937 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5938  
5939 /******************* Bit definition for CAN_RI1R register *******************/
5940 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5941 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5942 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
5943 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5944  
5945 /******************* Bit definition for CAN_RDT1R register ******************/
5946 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5947 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
5948 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5949  
5950 /******************* Bit definition for CAN_RDL1R register ******************/
5951 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5952 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5953 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5954 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5955  
5956 /******************* Bit definition for CAN_RDH1R register ******************/
5957 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5958 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5959 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5960 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5961  
5962 /*!<CAN filter registers */
5963 /******************* Bit definition for CAN_FMR register ********************/
5964 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
5965  
5966 /******************* Bit definition for CAN_FM1R register *******************/
5967 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
5968 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
5969 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
5970 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
5971 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
5972 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
5973 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
5974 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
5975 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
5976 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
5977 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
5978 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
5979 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
5980 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
5981 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
5982  
5983 /******************* Bit definition for CAN_FS1R register *******************/
5984 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
5985 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
5986 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
5987 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
5988 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
5989 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
5990 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
5991 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
5992 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
5993 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
5994 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
5995 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
5996 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
5997 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
5998 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
5999  
6000 /****************** Bit definition for CAN_FFA1R register *******************/
6001 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
6002 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
6003 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
6004 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
6005 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
6006 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
6007 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
6008 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
6009 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
6010 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
6011 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
6012 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
6013 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
6014 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
6015 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
6016  
6017 /******************* Bit definition for CAN_FA1R register *******************/
6018 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
6019 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
6020 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
6021 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
6022 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
6023 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
6024 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
6025 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
6026 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
6027 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
6028 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
6029 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
6030 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
6031 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
6032 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
6033  
6034 /******************* Bit definition for CAN_F0R1 register *******************/
6035 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6036 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6037 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6038 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6039 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6040 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6041 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6042 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6043 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6044 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6045 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6046 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6047 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6048 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6049 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6050 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6051 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6052 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6053 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6054 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6055 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6056 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6057 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6058 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6059 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6060 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6061 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6062 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6063 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6064 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6065 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6066 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6067  
6068 /******************* Bit definition for CAN_F1R1 register *******************/
6069 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6070 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6071 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6072 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6073 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6074 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6075 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6076 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6077 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6078 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6079 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6080 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6081 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6082 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6083 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6084 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6085 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6086 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6087 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6088 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6089 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6090 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6091 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6092 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6093 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6094 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6095 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6096 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6097 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6098 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6099 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6100 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6101  
6102 /******************* Bit definition for CAN_F2R1 register *******************/
6103 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6104 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6105 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6106 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6107 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6108 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6109 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6110 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6111 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6112 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6113 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6114 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6115 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6116 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6117 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6118 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6119 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6120 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6121 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6122 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6123 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6124 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6125 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6126 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6127 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6128 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6129 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6130 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6131 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6132 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6133 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6134 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6135  
6136 /******************* Bit definition for CAN_F3R1 register *******************/
6137 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6138 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6139 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6140 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6141 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6142 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6143 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6144 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6145 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6146 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6147 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6148 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6149 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6150 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6151 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6152 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6153 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6154 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6155 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6156 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6157 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6158 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6159 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6160 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6161 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6162 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6163 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6164 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6165 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6166 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6167 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6168 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6169  
6170 /******************* Bit definition for CAN_F4R1 register *******************/
6171 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6172 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6173 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6174 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6175 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6176 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6177 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6178 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6179 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6180 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6181 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6182 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6183 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6184 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6185 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6186 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6187 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6188 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6189 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6190 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6191 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6192 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6193 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6194 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6195 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6196 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6197 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6198 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6199 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6200 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6201 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6202 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6203  
6204 /******************* Bit definition for CAN_F5R1 register *******************/
6205 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6206 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6207 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6208 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6209 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6210 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6211 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6212 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6213 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6214 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6215 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6216 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6217 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6218 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6219 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6220 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6221 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6222 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6223 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6224 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6225 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6226 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6227 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6228 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6229 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6230 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6231 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6232 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6233 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6234 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6235 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6236 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6237  
6238 /******************* Bit definition for CAN_F6R1 register *******************/
6239 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6240 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6241 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6242 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6243 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6244 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6245 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6246 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6247 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6248 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6249 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6250 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6251 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6252 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6253 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6254 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6255 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6256 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6257 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6258 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6259 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6260 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6261 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6262 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6263 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6264 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6265 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6266 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6267 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6268 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6269 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6270 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6271  
6272 /******************* Bit definition for CAN_F7R1 register *******************/
6273 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6274 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6275 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6276 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6277 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6278 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6279 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6280 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6281 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6282 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6283 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6284 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6285 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6286 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6287 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6288 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6289 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6290 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6291 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6292 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6293 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6294 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6295 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6296 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6297 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6298 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6299 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6300 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6301 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6302 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6303 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6304 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6305  
6306 /******************* Bit definition for CAN_F8R1 register *******************/
6307 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6308 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6309 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6310 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6311 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6312 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6313 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6314 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6315 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6316 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6317 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6318 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6319 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6320 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6321 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6322 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6323 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6324 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6325 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6326 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6327 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6328 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6329 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6330 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6331 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6332 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6333 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6334 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6335 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6336 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6337 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6338 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6339  
6340 /******************* Bit definition for CAN_F9R1 register *******************/
6341 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6342 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6343 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6344 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6345 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6346 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6347 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6348 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6349 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6350 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6351 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6352 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6353 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6354 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6355 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6356 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6357 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6358 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6359 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6360 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6361 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6362 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6363 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6364 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6365 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6366 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6367 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6368 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6369 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6370 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6371 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6372 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6373  
6374 /******************* Bit definition for CAN_F10R1 register ******************/
6375 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6376 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6377 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6378 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6379 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6380 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6381 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6382 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6383 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6384 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6385 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6386 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6387 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6388 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6389 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6390 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6391 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6392 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6393 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6394 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6395 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6396 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6397 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6398 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6399 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6400 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6401 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6402 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6403 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6404 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6405 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6406 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6407  
6408 /******************* Bit definition for CAN_F11R1 register ******************/
6409 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6410 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6411 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6412 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6413 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6414 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6415 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6416 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6417 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6418 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6419 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6420 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6421 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6422 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6423 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6424 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6425 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6426 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6427 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6428 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6429 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6430 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6431 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6432 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6433 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6434 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6435 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6436 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6437 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6438 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6439 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6440 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6441  
6442 /******************* Bit definition for CAN_F12R1 register ******************/
6443 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6444 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6445 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6446 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6447 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6448 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6449 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6450 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6451 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6452 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6453 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6454 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6455 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6456 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6457 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6458 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6459 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6460 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6461 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6462 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6463 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6464 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6465 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6466 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6467 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6468 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6469 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6470 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6471 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6472 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6473 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6474 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6475  
6476 /******************* Bit definition for CAN_F13R1 register ******************/
6477 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6478 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6479 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6480 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6481 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6482 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6483 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6484 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6485 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6486 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6487 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6488 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6489 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6490 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6491 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6492 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6493 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6494 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6495 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6496 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6497 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6498 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6499 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6500 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6501 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6502 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6503 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6504 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6505 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6506 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6507 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6508 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6509  
6510 /******************* Bit definition for CAN_F0R2 register *******************/
6511 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6512 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6513 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6514 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6515 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6516 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6517 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6518 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6519 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6520 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6521 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6522 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6523 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6524 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6525 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6526 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6527 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6528 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6529 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6530 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6531 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6532 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6533 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6534 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6535 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6536 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6537 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6538 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6539 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6540 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6541 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6542 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6543  
6544 /******************* Bit definition for CAN_F1R2 register *******************/
6545 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6546 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6547 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6548 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6549 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6550 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6551 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6552 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6553 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6554 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6555 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6556 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6557 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6558 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6559 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6560 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6561 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6562 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6563 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6564 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6565 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6566 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6567 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6568 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6569 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6570 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6571 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6572 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6573 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6574 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6575 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6576 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6577  
6578 /******************* Bit definition for CAN_F2R2 register *******************/
6579 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6580 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6581 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6582 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6583 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6584 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6585 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6586 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6587 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6588 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6589 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6590 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6591 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6592 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6593 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6594 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6595 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6596 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6597 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6598 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6599 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6600 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6601 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6602 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6603 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6604 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6605 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6606 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6607 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6608 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6609 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6610 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6611  
6612 /******************* Bit definition for CAN_F3R2 register *******************/
6613 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6614 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6615 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6616 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6617 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6618 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6619 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6620 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6621 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6622 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6623 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6624 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6625 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6626 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6627 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6628 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6629 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6630 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6631 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6632 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6633 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6634 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6635 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6636 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6637 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6638 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6639 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6640 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6641 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6642 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6643 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6644 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6645  
6646 /******************* Bit definition for CAN_F4R2 register *******************/
6647 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6648 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6649 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6650 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6651 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6652 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6653 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6654 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6655 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6656 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6657 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6658 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6659 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6660 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6661 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6662 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6663 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6664 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6665 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6666 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6667 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6668 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6669 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6670 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6671 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6672 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6673 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6674 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6675 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6676 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6677 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6678 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6679  
6680 /******************* Bit definition for CAN_F5R2 register *******************/
6681 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6682 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6683 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6684 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6685 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6686 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6687 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6688 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6689 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6690 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6691 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6692 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6693 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6694 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6695 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6696 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6697 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6698 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6699 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6700 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6701 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6702 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6703 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6704 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6705 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6706 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6707 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6708 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6709 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6710 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6711 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6712 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6713  
6714 /******************* Bit definition for CAN_F6R2 register *******************/
6715 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6716 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6717 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6718 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6719 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6720 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6721 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6722 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6723 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6724 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6725 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6726 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6727 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6728 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6729 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6730 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6731 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6732 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6733 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6734 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6735 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6736 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6737 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6738 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6739 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6740 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6741 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6742 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6743 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6744 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6745 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6746 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6747  
6748 /******************* Bit definition for CAN_F7R2 register *******************/
6749 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6750 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6751 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6752 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6753 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6754 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6755 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6756 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6757 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6758 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6759 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6760 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6761 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6762 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6763 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6764 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6765 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6766 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6767 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6768 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6769 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6770 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6771 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6772 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6773 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6774 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6775 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6776 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6777 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6778 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6779 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6780 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6781  
6782 /******************* Bit definition for CAN_F8R2 register *******************/
6783 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6784 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6785 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6786 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6787 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6788 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6789 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6790 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6791 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6792 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6793 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6794 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6795 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6796 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6797 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6798 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6799 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6800 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6801 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6802 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6803 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6804 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6805 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6806 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6807 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6808 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6809 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6810 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6811 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6812 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6813 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6814 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6815  
6816 /******************* Bit definition for CAN_F9R2 register *******************/
6817 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6818 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6819 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6820 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6821 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6822 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6823 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6824 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6825 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6826 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6827 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6828 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6829 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6830 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6831 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6832 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6833 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6834 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6835 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6836 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6837 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6838 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6839 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6840 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6841 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6842 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6843 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6844 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6845 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6846 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6847 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6848 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6849  
6850 /******************* Bit definition for CAN_F10R2 register ******************/
6851 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6852 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6853 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6854 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6855 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6856 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6857 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6858 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6859 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6860 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6861 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6862 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6863 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6864 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6865 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6866 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6867 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6868 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6869 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6870 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6871 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6872 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6873 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6874 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6875 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6876 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6877 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6878 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6879 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6880 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6881 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6882 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6883  
6884 /******************* Bit definition for CAN_F11R2 register ******************/
6885 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6886 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6887 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6888 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6889 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6890 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6891 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6892 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6893 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6894 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6895 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6896 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6897 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6898 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6899 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6900 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6901 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6902 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6903 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6904 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6905 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6906 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6907 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6908 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6909 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6910 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6911 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6912 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6913 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6914 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6915 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6916 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6917  
6918 /******************* Bit definition for CAN_F12R2 register ******************/
6919 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6920 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6921 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6922 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6923 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6924 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6925 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6926 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6927 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6928 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6929 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6930 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6931 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6932 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6933 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6934 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6935 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6936 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6937 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6938 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6939 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6940 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6941 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6942 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6943 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6944 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6945 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6946 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6947 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6948 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6949 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6950 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6951  
6952 /******************* Bit definition for CAN_F13R2 register ******************/
6953 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6954 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6955 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6956 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6957 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6958 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6959 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6960 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6961 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6962 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6963 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6964 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6965 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6966 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6967 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6968 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6969 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6970 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6971 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6972 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6973 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6974 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6975 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6976 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6977 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6978 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6979 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6980 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6981 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6982 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6983 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6984 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6985  
6986 /******************************************************************************/
6987 /* */
6988 /* Serial Peripheral Interface */
6989 /* */
6990 /******************************************************************************/
6991  
6992 /******************* Bit definition for SPI_CR1 register ********************/
6993 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
6994 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
6995 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
6996  
6997 #define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
6998 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
6999 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
7000 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
7001  
7002 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
7003 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
7004 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
7005 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
7006 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
7007 #define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
7008 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
7009 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
7010 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
7011 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
7012  
7013 /******************* Bit definition for SPI_CR2 register ********************/
7014 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
7015 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
7016 #define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
7017 #define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
7018 #define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
7019 #define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
7020  
7021 /******************** Bit definition for SPI_SR register ********************/
7022 #define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
7023 #define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
7024 #define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
7025 #define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
7026 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
7027 #define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
7028 #define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
7029 #define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
7030  
7031 /******************** Bit definition for SPI_DR register ********************/
7032 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
7033  
7034 /******************* Bit definition for SPI_CRCPR register ******************/
7035 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
7036  
7037 /****************** Bit definition for SPI_RXCRCR register ******************/
7038 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
7039  
7040 /****************** Bit definition for SPI_TXCRCR register ******************/
7041 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
7042  
7043 /****************** Bit definition for SPI_I2SCFGR register *****************/
7044 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
7045  
7046 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
7047 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
7048 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
7049  
7050 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
7051  
7052 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
7053 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
7054 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
7055  
7056 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
7057  
7058 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
7059 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
7060 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
7061  
7062 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
7063 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
7064  
7065 /****************** Bit definition for SPI_I2SPR register *******************/
7066 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
7067 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
7068 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
7069  
7070 /******************************************************************************/
7071 /* */
7072 /* Inter-integrated Circuit Interface */
7073 /* */
7074 /******************************************************************************/
7075  
7076 /******************* Bit definition for I2C_CR1 register ********************/
7077 #define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
7078 #define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
7079 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
7080 #define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
7081 #define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
7082 #define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
7083 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
7084 #define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
7085 #define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
7086 #define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
7087 #define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
7088 #define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
7089 #define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
7090 #define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
7091  
7092 /******************* Bit definition for I2C_CR2 register ********************/
7093 #define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
7094 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
7095 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
7096 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
7097 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
7098 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
7099 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
7100  
7101 #define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
7102 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
7103 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
7104 #define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
7105 #define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
7106  
7107 /******************* Bit definition for I2C_OAR1 register *******************/
7108 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
7109 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
7110  
7111 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
7112 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
7113 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
7114 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
7115 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
7116 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
7117 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
7118 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
7119 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
7120 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
7121  
7122 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
7123  
7124 /******************* Bit definition for I2C_OAR2 register *******************/
7125 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
7126 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
7127  
7128 /******************** Bit definition for I2C_DR register ********************/
7129 #define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
7130  
7131 /******************* Bit definition for I2C_SR1 register ********************/
7132 #define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
7133 #define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
7134 #define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
7135 #define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
7136 #define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
7137 #define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
7138 #define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
7139 #define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
7140 #define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
7141 #define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
7142 #define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
7143 #define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
7144 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
7145 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
7146  
7147 /******************* Bit definition for I2C_SR2 register ********************/
7148 #define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
7149 #define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
7150 #define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
7151 #define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
7152 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
7153 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
7154 #define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
7155 #define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
7156  
7157 /******************* Bit definition for I2C_CCR register ********************/
7158 #define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
7159 #define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
7160 #define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
7161  
7162 /****************** Bit definition for I2C_TRISE register *******************/
7163 #define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
7164  
7165 /******************************************************************************/
7166 /* */
7167 /* Universal Synchronous Asynchronous Receiver Transmitter */
7168 /* */
7169 /******************************************************************************/
7170  
7171 /******************* Bit definition for USART_SR register *******************/
7172 #define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
7173 #define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
7174 #define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
7175 #define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
7176 #define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
7177 #define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
7178 #define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
7179 #define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
7180 #define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
7181 #define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
7182  
7183 /******************* Bit definition for USART_DR register *******************/
7184 #define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
7185  
7186 /****************** Bit definition for USART_BRR register *******************/
7187 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
7188 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
7189  
7190 /****************** Bit definition for USART_CR1 register *******************/
7191 #define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
7192 #define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
7193 #define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
7194 #define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
7195 #define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
7196 #define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
7197 #define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
7198 #define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
7199 #define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
7200 #define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
7201 #define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
7202 #define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
7203 #define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
7204 #define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
7205  
7206 /****************** Bit definition for USART_CR2 register *******************/
7207 #define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
7208 #define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
7209 #define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
7210 #define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
7211 #define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
7212 #define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
7213 #define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
7214  
7215 #define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
7216 #define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
7217 #define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
7218  
7219 #define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
7220  
7221 /****************** Bit definition for USART_CR3 register *******************/
7222 #define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
7223 #define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
7224 #define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
7225 #define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
7226 #define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
7227 #define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
7228 #define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
7229 #define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
7230 #define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
7231 #define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
7232 #define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
7233  
7234 /****************** Bit definition for USART_GTPR register ******************/
7235 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
7236 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
7237 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
7238 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
7239 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
7240 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
7241 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
7242 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
7243 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
7244  
7245 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
7246  
7247 /******************************************************************************/
7248 /* */
7249 /* Debug MCU */
7250 /* */
7251 /******************************************************************************/
7252  
7253 /**************** Bit definition for DBGMCU_IDCODE register *****************/
7254 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */
7255  
7256 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */
7257 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */
7258 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */
7259 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */
7260 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */
7261 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */
7262 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */
7263 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */
7264 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */
7265 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */
7266 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */
7267 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */
7268 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */
7269 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */
7270 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */
7271 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */
7272 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */
7273  
7274 /****************** Bit definition for DBGMCU_CR register *******************/
7275 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */
7276 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */
7277 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */
7278 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */
7279  
7280 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
7281 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
7282 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
7283  
7284 #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */
7285 #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */
7286 #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */
7287 #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */
7288 #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */
7289 #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */
7290 #define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */
7291 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */
7292 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */
7293 #define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */
7294 #define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */
7295 #define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */
7296 #define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */
7297 #define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */
7298  
7299 /******************************************************************************/
7300 /* */
7301 /* FLASH and Option Bytes Registers */
7302 /* */
7303 /******************************************************************************/
7304  
7305 /******************* Bit definition for FLASH_ACR register ******************/
7306 #define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */
7307 #define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */
7308 #define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */
7309 #define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */
7310  
7311 #define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */
7312 #define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */
7313 #define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */
7314  
7315 /****************** Bit definition for FLASH_KEYR register ******************/
7316 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */
7317  
7318 /***************** Bit definition for FLASH_OPTKEYR register ****************/
7319 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */
7320  
7321 /****************** Bit definition for FLASH_SR register *******************/
7322 #define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */
7323 #define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */
7324 #define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */
7325 #define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */
7326  
7327 /******************* Bit definition for FLASH_CR register *******************/
7328 #define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */
7329 #define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */
7330 #define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */
7331 #define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */
7332 #define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */
7333 #define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */
7334 #define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */
7335 #define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */
7336 #define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */
7337 #define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */
7338  
7339 /******************* Bit definition for FLASH_AR register *******************/
7340 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */
7341  
7342 /****************** Bit definition for FLASH_OBR register *******************/
7343 #define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */
7344 #define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */
7345  
7346 #define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */
7347 #define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
7348 #define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
7349 #define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
7350 #define FLASH_OBR_Notused ((uint16_t)0x03E0) /*!<Not used */
7351  
7352 /****************** Bit definition for FLASH_WRPR register ******************/
7353 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */
7354  
7355 /*----------------------------------------------------------------------------*/
7356  
7357 /****************** Bit definition for FLASH_RDP register *******************/
7358 #define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */
7359 #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */
7360  
7361 /****************** Bit definition for FLASH_USER register ******************/
7362 #define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */
7363 #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */
7364  
7365 /****************** Bit definition for FLASH_Data0 register *****************/
7366 #define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */
7367 #define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */
7368  
7369 /****************** Bit definition for FLASH_Data1 register *****************/
7370 #define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */
7371 #define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */
7372  
7373 /****************** Bit definition for FLASH_WRP0 register ******************/
7374 #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
7375 #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
7376  
7377 /****************** Bit definition for FLASH_WRP1 register ******************/
7378 #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
7379 #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
7380  
7381 /****************** Bit definition for FLASH_WRP2 register ******************/
7382 #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
7383 #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
7384  
7385 /****************** Bit definition for FLASH_WRP3 register ******************/
7386 #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
7387 #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
7388  
7389 #ifdef STM32F10X_CL
7390 /******************************************************************************/
7391 /* Ethernet MAC Registers bits definitions */
7392 /******************************************************************************/
7393 /* Bit definition for Ethernet MAC Control Register register */
7394 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
7395 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
7396 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
7397 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
7398 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
7399 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
7400 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
7401 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
7402 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
7403 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
7404 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
7405 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
7406 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
7407 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
7408 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
7409 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
7410 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
7411 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
7412 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
7413 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7414 a transmission attempt during retries after a collision: 0 =< r <2^k */
7415 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
7416 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
7417 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
7418 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
7419 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
7420 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
7421 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
7422  
7423 /* Bit definition for Ethernet MAC Frame Filter Register */
7424 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
7425 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
7426 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
7427 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
7428 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
7429 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
7430 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
7431 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
7432 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
7433 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
7434 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
7435 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
7436 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
7437 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
7438  
7439 /* Bit definition for Ethernet MAC Hash Table High Register */
7440 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
7441  
7442 /* Bit definition for Ethernet MAC Hash Table Low Register */
7443 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
7444  
7445 /* Bit definition for Ethernet MAC MII Address Register */
7446 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
7447 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
7448 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
7449 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
7450 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7451 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7452 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
7453 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
7454  
7455 /* Bit definition for Ethernet MAC MII Data Register */
7456 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
7457  
7458 /* Bit definition for Ethernet MAC Flow Control Register */
7459 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
7460 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
7461 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
7462 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7463 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
7464 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
7465 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
7466 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
7467 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
7468 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
7469 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
7470  
7471 /* Bit definition for Ethernet MAC VLAN Tag Register */
7472 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
7473 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
7474  
7475 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7476 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
7477 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7478 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7479 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7480 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7481 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7482 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7483 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7484 RSVD - Filter1 Command - RSVD - Filter0 Command
7485 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7486 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7487 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7488  
7489 /* Bit definition for Ethernet MAC PMT Control and Status Register */
7490 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
7491 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
7492 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
7493 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
7494 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
7495 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
7496 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
7497  
7498 /* Bit definition for Ethernet MAC Status Register */
7499 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
7500 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
7501 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
7502 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
7503 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
7504  
7505 /* Bit definition for Ethernet MAC Interrupt Mask Register */
7506 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
7507 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
7508  
7509 /* Bit definition for Ethernet MAC Address0 High Register */
7510 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
7511  
7512 /* Bit definition for Ethernet MAC Address0 Low Register */
7513 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
7514  
7515 /* Bit definition for Ethernet MAC Address1 High Register */
7516 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
7517 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
7518 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7519 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7520 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7521 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7522 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7523 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7524 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
7525 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7526  
7527 /* Bit definition for Ethernet MAC Address1 Low Register */
7528 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
7529  
7530 /* Bit definition for Ethernet MAC Address2 High Register */
7531 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
7532 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
7533 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
7534 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7535 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7536 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7537 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7538 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7539 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
7540 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7541  
7542 /* Bit definition for Ethernet MAC Address2 Low Register */
7543 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
7544  
7545 /* Bit definition for Ethernet MAC Address3 High Register */
7546 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
7547 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
7548 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
7549 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7550 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7551 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7552 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7553 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7554 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
7555 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
7556  
7557 /* Bit definition for Ethernet MAC Address3 Low Register */
7558 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
7559  
7560 /******************************************************************************/
7561 /* Ethernet MMC Registers bits definition */
7562 /******************************************************************************/
7563  
7564 /* Bit definition for Ethernet MMC Contol Register */
7565 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
7566 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
7567 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
7568 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
7569  
7570 /* Bit definition for Ethernet MMC Receive Interrupt Register */
7571 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
7572 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
7573 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
7574  
7575 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
7576 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
7577 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
7578 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
7579  
7580 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
7581 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
7582 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
7583 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
7584  
7585 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
7586 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
7587 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
7588 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
7589  
7590 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
7591 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
7592  
7593 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
7594 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
7595  
7596 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
7597 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
7598  
7599 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
7600 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
7601  
7602 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
7603 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
7604  
7605 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
7606 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
7607  
7608 /******************************************************************************/
7609 /* Ethernet PTP Registers bits definition */
7610 /******************************************************************************/
7611  
7612 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
7613 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
7614 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
7615 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
7616 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
7617 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
7618 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
7619  
7620 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
7621 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
7622  
7623 /* Bit definition for Ethernet PTP Time Stamp High Register */
7624 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
7625  
7626 /* Bit definition for Ethernet PTP Time Stamp Low Register */
7627 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
7628 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
7629  
7630 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
7631 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
7632  
7633 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7634 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
7635 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
7636  
7637 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
7638 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
7639  
7640 /* Bit definition for Ethernet PTP Target Time High Register */
7641 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
7642  
7643 /* Bit definition for Ethernet PTP Target Time Low Register */
7644 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
7645  
7646 /******************************************************************************/
7647 /* Ethernet DMA Registers bits definition */
7648 /******************************************************************************/
7649  
7650 /* Bit definition for Ethernet DMA Bus Mode Register */
7651 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
7652 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
7653 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
7654 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
7655 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7656 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7657 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7658 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7659 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7660 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7661 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7662 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7663 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7664 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7665 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7666 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7667 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
7668 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
7669 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
7670 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
7671 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
7672 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
7673 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
7674 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7675 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7676 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7677 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7678 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7679 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7680 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7681 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7682 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7683 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7684 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7685 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7686 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
7687 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
7688 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
7689  
7690 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7691 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
7692  
7693 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
7694 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
7695  
7696 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7697 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
7698  
7699 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7700 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
7701  
7702 /* Bit definition for Ethernet DMA Status Register */
7703 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
7704 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
7705 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
7706 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
7707 /* combination with EBS[2:0] for GetFlagStatus function */
7708 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
7709 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
7710 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
7711 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
7712 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
7713 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
7714 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
7715 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
7716 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
7717 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
7718 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
7719 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
7720 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
7721 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
7722 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
7723 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
7724 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
7725 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
7726 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
7727 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
7728 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
7729 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
7730 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
7731 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
7732 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
7733 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
7734 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
7735 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
7736 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
7737 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
7738 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
7739 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
7740  
7741 /* Bit definition for Ethernet DMA Operation Mode Register */
7742 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
7743 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
7744 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
7745 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
7746 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
7747 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
7748 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7749 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7750 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7751 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7752 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7753 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7754 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7755 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7756 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
7757 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
7758 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
7759 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
7760 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
7761 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
7762 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
7763 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
7764 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
7765 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
7766  
7767 /* Bit definition for Ethernet DMA Interrupt Enable Register */
7768 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
7769 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
7770 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
7771 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
7772 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
7773 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
7774 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
7775 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
7776 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
7777 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
7778 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
7779 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
7780 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
7781 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
7782 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
7783  
7784 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
7785 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
7786 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
7787 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
7788 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
7789  
7790 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
7791 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
7792  
7793 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
7794 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
7795  
7796 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
7797 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
7798  
7799 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
7800 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
7801 #endif /* STM32F10X_CL */
7802  
7803 /**
7804 * @}
7805 */
7806  
7807 /**
7808 * @}
7809 */
7810  
7811 #ifdef USE_STDPERIPH_DRIVER
7812 #include "stm32f10x_conf.h"
7813 #endif
7814  
7815 /** @addtogroup Exported_macro
7816 * @{
7817 */
7818  
7819 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
7820  
7821 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
7822  
7823 #define READ_BIT(REG, BIT) ((REG) & (BIT))
7824  
7825 #define CLEAR_REG(REG) ((REG) = (0x0))
7826  
7827 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
7828  
7829 #define READ_REG(REG) ((REG))
7830  
7831 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
7832  
7833 /**
7834 * @}
7835 */
7836  
7837 #ifdef __cplusplus
7838 }
7839 #endif
7840  
7841 #endif /* __STM32F10x_H */
7842  
7843 /**
7844 * @}
7845 */
7846  
7847 /**
7848 * @}
7849 */
7850  
7851 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/