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/** |
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****************************************************************************** |
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* @file system_stm32f10x.c |
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* @author MCD Application Team |
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* @version V3.1.2 |
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* @date 09/28/2009 |
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
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****************************************************************************** |
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* |
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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* |
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> |
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****************************************************************************** |
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*/ |
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/** @addtogroup CMSIS |
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* @{ |
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*/ |
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/** @addtogroup stm32f10x_system |
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* @{ |
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*/ |
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/** @addtogroup STM32F10x_System_Private_Includes |
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* @{ |
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*/ |
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#include "stm32f10x.h" |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32F10x_System_Private_TypesDefinitions |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32F10x_System_Private_Defines |
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* @{ |
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*/ |
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/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) |
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frequency (after reset the HSI is used as SYSCLK source) |
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IMPORTANT NOTE: |
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============== |
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1. After each device reset the HSI is used as System clock source. |
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2. Please make sure that the selected System clock doesn't exceed your device's |
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maximum frequency. |
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3. If none of the define below is enabled, the HSI is used as System clock |
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source. |
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4. The System clock configuration functions provided within this file assume that: |
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- For Low, Medium and High density devices an external 8MHz crystal is |
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used to drive the System clock. |
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- For Connectivity line devices an external 25MHz crystal is used to drive |
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the System clock. |
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If you are using different crystal you have to adapt those functions accordingly. |
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*/ |
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/* #define SYSCLK_FREQ_HSE HSE_Value */ |
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/* #define SYSCLK_FREQ_24MHz 24000000 */ |
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/* #define SYSCLK_FREQ_36MHz 36000000 */ |
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/* #define SYSCLK_FREQ_48MHz 48000000 */ |
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/* #define SYSCLK_FREQ_56MHz 56000000 */ |
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#define SYSCLK_FREQ_72MHz 72000000 |
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/*!< Uncomment the following line if you need to use external SRAM mounted |
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on STM3210E-EVAL board (STM32 High density devices) as data memory */ |
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#ifdef STM32F10X_HD |
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/* #define DATA_IN_ExtSRAM */ |
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#endif /* STM32F10X_HD */ |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32F10x_System_Private_Macros |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32F10x_System_Private_Variables |
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* @{ |
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*/ |
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/******************************************************************************* |
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* Clock Definitions |
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*******************************************************************************/ |
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#ifdef SYSCLK_FREQ_HSE |
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const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ |
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */ |
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */ |
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const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */ |
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */ |
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#elif defined SYSCLK_FREQ_24MHz |
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const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ |
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */ |
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */ |
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const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */ |
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */ |
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#elif defined SYSCLK_FREQ_36MHz |
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const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ |
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */ |
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */ |
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const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */ |
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */ |
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#elif defined SYSCLK_FREQ_48MHz |
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const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ |
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */ |
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */ |
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const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */ |
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */ |
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#elif defined SYSCLK_FREQ_56MHz |
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const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ |
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */ |
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */ |
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const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */ |
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */ |
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#elif defined SYSCLK_FREQ_72MHz |
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const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ |
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const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */ |
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const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */ |
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const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */ |
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const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */ |
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#else /*!< HSI Selected as System Clock source */ |
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const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */ |
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const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */ |
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const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */ |
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const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */ |
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const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */ |
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#endif |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32F10x_System_Private_FunctionPrototypes |
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* @{ |
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*/ |
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static void SetSysClock(void); |
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#ifdef SYSCLK_FREQ_HSE |
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static void SetSysClockToHSE(void); |
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#elif defined SYSCLK_FREQ_24MHz |
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static void SetSysClockTo24(void); |
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#elif defined SYSCLK_FREQ_36MHz |
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static void SetSysClockTo36(void); |
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#elif defined SYSCLK_FREQ_48MHz |
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static void SetSysClockTo48(void); |
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#elif defined SYSCLK_FREQ_56MHz |
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static void SetSysClockTo56(void); |
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#elif defined SYSCLK_FREQ_72MHz |
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static void SetSysClockTo72(void); |
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#endif |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32F10x_System_Private_Functions |
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* @{ |
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*/ |
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/** |
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* @brief Setup the microcontroller system |
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* Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable. |
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* @note This function should be used only after reset. |
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* @param None |
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* @retval None |
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*/ |
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void SystemInit (void) |
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{ |
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */ |
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/* Set HSION bit */ |
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RCC->CR |= (uint32_t)0x00000001; |
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ |
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#ifndef STM32F10X_CL |
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RCC->CFGR &= (uint32_t)0xF8FF0000; |
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#else |
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RCC->CFGR &= (uint32_t)0xF0FF0000; |
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#endif /* STM32F10X_CL */ |
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/* Reset HSEON, CSSON and PLLON bits */ |
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RCC->CR &= (uint32_t)0xFEF6FFFF; |
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/* Reset HSEBYP bit */ |
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RCC->CR &= (uint32_t)0xFFFBFFFF; |
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ |
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RCC->CFGR &= (uint32_t)0xFF80FFFF; |
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#ifndef STM32F10X_CL |
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/* Disable all interrupts and clear pending bits */ |
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RCC->CIR = 0x009F0000; |
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#else |
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/* Reset PLL2ON and PLL3ON bits */ |
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RCC->CR &= (uint32_t)0xEBFFFFFF; |
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/* Disable all interrupts and clear pending bits */ |
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RCC->CIR = 0x00FF0000; |
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/* Reset CFGR2 register */ |
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RCC->CFGR2 = 0x00000000; |
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#endif /* STM32F10X_CL */ |
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/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ |
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/* Configure the Flash Latency cycles and enable prefetch buffer */ |
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SetSysClock(); |
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} |
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/** |
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. |
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* @param None |
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* @retval None |
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*/ |
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static void SetSysClock(void) |
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{ |
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#ifdef SYSCLK_FREQ_HSE |
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SetSysClockToHSE(); |
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#elif defined SYSCLK_FREQ_24MHz |
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SetSysClockTo24(); |
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#elif defined SYSCLK_FREQ_36MHz |
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SetSysClockTo36(); |
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#elif defined SYSCLK_FREQ_48MHz |
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SetSysClockTo48(); |
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#elif defined SYSCLK_FREQ_56MHz |
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SetSysClockTo56(); |
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#elif defined SYSCLK_FREQ_72MHz |
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SetSysClockTo72(); |
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#endif |
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/* If none of the define above is enabled, the HSI is used as System clock |
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source (default after reset) */ |
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} |
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/** |
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* @brief Setup the external memory controller. Called in startup_stm32f10x.s |
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* before jump to __main |
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* @param None |
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* @retval None |
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*/ |
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#ifdef DATA_IN_ExtSRAM |
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/** |
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* @brief Setup the external memory controller. |
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* Called in startup_stm32f10x_xx.s/.c before jump to main. |
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* This function configures the external SRAM mounted on STM3210E-EVAL |
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* board (STM32 High density devices). This SRAM will be used as program |
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* data memory (including heap and stack). |
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* @param None |
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* @retval None |
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*/ |
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void SystemInit_ExtMemCtl(void) |
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{ |
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/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is |
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required, then adjust the Register Addresses */ |
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/* Enable FSMC clock */ |
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RCC->AHBENR = 0x00000114; |
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/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ |
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RCC->APB2ENR = 0x000001E0; |
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/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ |
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/*---------------- SRAM Address lines configuration -------------------------*/ |
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/*---------------- NOE and NWE configuration --------------------------------*/ |
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/*---------------- NE3 configuration ----------------------------------------*/ |
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/*---------------- NBL0, NBL1 configuration ---------------------------------*/ |
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GPIOD->CRL = 0x44BB44BB; |
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GPIOD->CRH = 0xBBBBBBBB; |
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GPIOE->CRL = 0xB44444BB; |
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GPIOE->CRH = 0xBBBBBBBB; |
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GPIOF->CRL = 0x44BBBBBB; |
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GPIOF->CRH = 0xBBBB4444; |
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GPIOG->CRL = 0x44BBBBBB; |
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GPIOG->CRH = 0x44444B44; |
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/*---------------- FSMC Configuration ---------------------------------------*/ |
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/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ |
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FSMC_Bank1->BTCR[4] = 0x00001011; |
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FSMC_Bank1->BTCR[5] = 0x00000200; |
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} |
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#endif /* DATA_IN_ExtSRAM */ |
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#ifdef SYSCLK_FREQ_HSE |
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/** |
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* @brief Selects HSE as System clock source and configure HCLK, PCLK2 |
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* and PCLK1 prescalers. |
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* @note This function should be used only after reset. |
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* @param None |
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* @retval None |
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*/ |
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static void SetSysClockToHSE(void) |
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{ |
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
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/* Enable HSE */ |
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RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
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/* Wait till HSE is ready and if Time out is reached exit */ |
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do |
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{ |
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HSEStatus = RCC->CR & RCC_CR_HSERDY; |
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StartUpCounter++; |
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} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); |
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if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
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{ |
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HSEStatus = (uint32_t)0x01; |
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} |
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else |
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{ |
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HSEStatus = (uint32_t)0x00; |
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} |
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if (HSEStatus == (uint32_t)0x01) |
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{ |
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/* Enable Prefetch Buffer */ |
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FLASH->ACR |= FLASH_ACR_PRFTBE; |
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/* Flash 0 wait state */ |
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FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
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#ifndef STM32F10X_CL |
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FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; |
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#else |
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if (HSE_Value <= 24000000) |
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{ |
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FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; |
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} |
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else |
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{ |
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FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; |
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} |
|
|
358 |
#endif /* STM32F10X_CL */ |
|
|
359 |
|
|
|
360 |
/* HCLK = SYSCLK */ |
|
|
361 |
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
|
|
362 |
|
|
|
363 |
/* PCLK2 = HCLK */ |
|
|
364 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
|
|
365 |
|
|
|
366 |
/* PCLK1 = HCLK */ |
|
|
367 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
|
|
368 |
|
|
|
369 |
/* Select HSE as system clock source */ |
|
|
370 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
|
|
371 |
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; |
|
|
372 |
|
|
|
373 |
/* Wait till HSE is used as system clock source */ |
|
|
374 |
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) |
|
|
375 |
{ |
|
|
376 |
} |
|
|
377 |
} |
|
|
378 |
else |
|
|
379 |
{ /* If HSE fails to start-up, the application will have wrong clock |
|
|
380 |
configuration. User can add here some code to deal with this error */ |
|
|
381 |
|
|
|
382 |
/* Go to infinite loop */ |
|
|
383 |
while (1) |
|
|
384 |
{ |
|
|
385 |
} |
|
|
386 |
} |
|
|
387 |
} |
|
|
388 |
#elif defined SYSCLK_FREQ_24MHz |
|
|
389 |
/** |
|
|
390 |
* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 |
|
|
391 |
* and PCLK1 prescalers. |
|
|
392 |
* @note This function should be used only after reset. |
|
|
393 |
* @param None |
|
|
394 |
* @retval None |
|
|
395 |
*/ |
|
|
396 |
static void SetSysClockTo24(void) |
|
|
397 |
{ |
|
|
398 |
__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
|
|
399 |
|
|
|
400 |
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
|
|
401 |
/* Enable HSE */ |
|
|
402 |
RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
|
|
403 |
|
|
|
404 |
/* Wait till HSE is ready and if Time out is reached exit */ |
|
|
405 |
do |
|
|
406 |
{ |
|
|
407 |
HSEStatus = RCC->CR & RCC_CR_HSERDY; |
|
|
408 |
StartUpCounter++; |
|
|
409 |
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); |
|
|
410 |
|
|
|
411 |
if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
|
|
412 |
{ |
|
|
413 |
HSEStatus = (uint32_t)0x01; |
|
|
414 |
} |
|
|
415 |
else |
|
|
416 |
{ |
|
|
417 |
HSEStatus = (uint32_t)0x00; |
|
|
418 |
} |
|
|
419 |
|
|
|
420 |
if (HSEStatus == (uint32_t)0x01) |
|
|
421 |
{ |
|
|
422 |
/* Enable Prefetch Buffer */ |
|
|
423 |
FLASH->ACR |= FLASH_ACR_PRFTBE; |
|
|
424 |
|
|
|
425 |
/* Flash 0 wait state */ |
|
|
426 |
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
|
|
427 |
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; |
|
|
428 |
|
|
|
429 |
/* HCLK = SYSCLK */ |
|
|
430 |
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
|
|
431 |
|
|
|
432 |
/* PCLK2 = HCLK */ |
|
|
433 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
|
|
434 |
|
|
|
435 |
/* PCLK1 = HCLK */ |
|
|
436 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
|
|
437 |
|
|
|
438 |
#ifdef STM32F10X_CL |
|
|
439 |
/* Configure PLLs ------------------------------------------------------*/ |
|
|
440 |
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ |
|
|
441 |
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
|
|
442 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
|
|
443 |
RCC_CFGR_PLLMULL6); |
|
|
444 |
|
|
|
445 |
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
|
|
446 |
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ |
|
|
447 |
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
|
|
448 |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
|
|
449 |
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
|
|
450 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); |
|
|
451 |
|
|
|
452 |
/* Enable PLL2 */ |
|
|
453 |
RCC->CR |= RCC_CR_PLL2ON; |
|
|
454 |
/* Wait till PLL2 is ready */ |
|
|
455 |
while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
|
|
456 |
{ |
|
|
457 |
} |
|
|
458 |
#else |
|
|
459 |
/* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ |
|
|
460 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
|
|
461 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); |
|
|
462 |
#endif /* STM32F10X_CL */ |
|
|
463 |
|
|
|
464 |
/* Enable PLL */ |
|
|
465 |
RCC->CR |= RCC_CR_PLLON; |
|
|
466 |
|
|
|
467 |
/* Wait till PLL is ready */ |
|
|
468 |
while((RCC->CR & RCC_CR_PLLRDY) == 0) |
|
|
469 |
{ |
|
|
470 |
} |
|
|
471 |
|
|
|
472 |
/* Select PLL as system clock source */ |
|
|
473 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
|
|
474 |
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
|
|
475 |
|
|
|
476 |
/* Wait till PLL is used as system clock source */ |
|
|
477 |
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
|
|
478 |
{ |
|
|
479 |
} |
|
|
480 |
} |
|
|
481 |
else |
|
|
482 |
{ /* If HSE fails to start-up, the application will have wrong clock |
|
|
483 |
configuration. User can add here some code to deal with this error */ |
|
|
484 |
|
|
|
485 |
/* Go to infinite loop */ |
|
|
486 |
while (1) |
|
|
487 |
{ |
|
|
488 |
} |
|
|
489 |
} |
|
|
490 |
} |
|
|
491 |
#elif defined SYSCLK_FREQ_36MHz |
|
|
492 |
/** |
|
|
493 |
* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 |
|
|
494 |
* and PCLK1 prescalers. |
|
|
495 |
* @note This function should be used only after reset. |
|
|
496 |
* @param None |
|
|
497 |
* @retval None |
|
|
498 |
*/ |
|
|
499 |
static void SetSysClockTo36(void) |
|
|
500 |
{ |
|
|
501 |
__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
|
|
502 |
|
|
|
503 |
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
|
|
504 |
/* Enable HSE */ |
|
|
505 |
RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
|
|
506 |
|
|
|
507 |
/* Wait till HSE is ready and if Time out is reached exit */ |
|
|
508 |
do |
|
|
509 |
{ |
|
|
510 |
HSEStatus = RCC->CR & RCC_CR_HSERDY; |
|
|
511 |
StartUpCounter++; |
|
|
512 |
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); |
|
|
513 |
|
|
|
514 |
if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
|
|
515 |
{ |
|
|
516 |
HSEStatus = (uint32_t)0x01; |
|
|
517 |
} |
|
|
518 |
else |
|
|
519 |
{ |
|
|
520 |
HSEStatus = (uint32_t)0x00; |
|
|
521 |
} |
|
|
522 |
|
|
|
523 |
if (HSEStatus == (uint32_t)0x01) |
|
|
524 |
{ |
|
|
525 |
/* Enable Prefetch Buffer */ |
|
|
526 |
FLASH->ACR |= FLASH_ACR_PRFTBE; |
|
|
527 |
|
|
|
528 |
/* Flash 1 wait state */ |
|
|
529 |
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
|
|
530 |
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; |
|
|
531 |
|
|
|
532 |
/* HCLK = SYSCLK */ |
|
|
533 |
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
|
|
534 |
|
|
|
535 |
/* PCLK2 = HCLK */ |
|
|
536 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
|
|
537 |
|
|
|
538 |
/* PCLK1 = HCLK */ |
|
|
539 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
|
|
540 |
|
|
|
541 |
#ifdef STM32F10X_CL |
|
|
542 |
/* Configure PLLs ------------------------------------------------------*/ |
|
|
543 |
|
|
|
544 |
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ |
|
|
545 |
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
|
|
546 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
|
|
547 |
RCC_CFGR_PLLMULL9); |
|
|
548 |
|
|
|
549 |
/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
|
|
550 |
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ |
|
|
551 |
|
|
|
552 |
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
|
|
553 |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
|
|
554 |
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
|
|
555 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); |
|
|
556 |
|
|
|
557 |
/* Enable PLL2 */ |
|
|
558 |
RCC->CR |= RCC_CR_PLL2ON; |
|
|
559 |
/* Wait till PLL2 is ready */ |
|
|
560 |
while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
|
|
561 |
{ |
|
|
562 |
} |
|
|
563 |
|
|
|
564 |
#else |
|
|
565 |
/* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ |
|
|
566 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
|
|
567 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); |
|
|
568 |
#endif /* STM32F10X_CL */ |
|
|
569 |
|
|
|
570 |
/* Enable PLL */ |
|
|
571 |
RCC->CR |= RCC_CR_PLLON; |
|
|
572 |
|
|
|
573 |
/* Wait till PLL is ready */ |
|
|
574 |
while((RCC->CR & RCC_CR_PLLRDY) == 0) |
|
|
575 |
{ |
|
|
576 |
} |
|
|
577 |
|
|
|
578 |
/* Select PLL as system clock source */ |
|
|
579 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
|
|
580 |
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
|
|
581 |
|
|
|
582 |
/* Wait till PLL is used as system clock source */ |
|
|
583 |
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
|
|
584 |
{ |
|
|
585 |
} |
|
|
586 |
} |
|
|
587 |
else |
|
|
588 |
{ /* If HSE fails to start-up, the application will have wrong clock |
|
|
589 |
configuration. User can add here some code to deal with this error */ |
|
|
590 |
|
|
|
591 |
/* Go to infinite loop */ |
|
|
592 |
while (1) |
|
|
593 |
{ |
|
|
594 |
} |
|
|
595 |
} |
|
|
596 |
} |
|
|
597 |
#elif defined SYSCLK_FREQ_48MHz |
|
|
598 |
/** |
|
|
599 |
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 |
|
|
600 |
* and PCLK1 prescalers. |
|
|
601 |
* @note This function should be used only after reset. |
|
|
602 |
* @param None |
|
|
603 |
* @retval None |
|
|
604 |
*/ |
|
|
605 |
static void SetSysClockTo48(void) |
|
|
606 |
{ |
|
|
607 |
__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
|
|
608 |
|
|
|
609 |
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
|
|
610 |
/* Enable HSE */ |
|
|
611 |
RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
|
|
612 |
|
|
|
613 |
/* Wait till HSE is ready and if Time out is reached exit */ |
|
|
614 |
do |
|
|
615 |
{ |
|
|
616 |
HSEStatus = RCC->CR & RCC_CR_HSERDY; |
|
|
617 |
StartUpCounter++; |
|
|
618 |
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); |
|
|
619 |
|
|
|
620 |
if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
|
|
621 |
{ |
|
|
622 |
HSEStatus = (uint32_t)0x01; |
|
|
623 |
} |
|
|
624 |
else |
|
|
625 |
{ |
|
|
626 |
HSEStatus = (uint32_t)0x00; |
|
|
627 |
} |
|
|
628 |
|
|
|
629 |
if (HSEStatus == (uint32_t)0x01) |
|
|
630 |
{ |
|
|
631 |
/* Enable Prefetch Buffer */ |
|
|
632 |
FLASH->ACR |= FLASH_ACR_PRFTBE; |
|
|
633 |
|
|
|
634 |
/* Flash 1 wait state */ |
|
|
635 |
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
|
|
636 |
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; |
|
|
637 |
|
|
|
638 |
/* HCLK = SYSCLK */ |
|
|
639 |
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
|
|
640 |
|
|
|
641 |
/* PCLK2 = HCLK */ |
|
|
642 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
|
|
643 |
|
|
|
644 |
/* PCLK1 = HCLK/2 */ |
|
|
645 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; |
|
|
646 |
|
|
|
647 |
#ifdef STM32F10X_CL |
|
|
648 |
/* Configure PLLs ------------------------------------------------------*/ |
|
|
649 |
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
|
|
650 |
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ |
|
|
651 |
|
|
|
652 |
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
|
|
653 |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
|
|
654 |
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
|
|
655 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); |
|
|
656 |
|
|
|
657 |
/* Enable PLL2 */ |
|
|
658 |
RCC->CR |= RCC_CR_PLL2ON; |
|
|
659 |
/* Wait till PLL2 is ready */ |
|
|
660 |
while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
|
|
661 |
{ |
|
|
662 |
} |
|
|
663 |
|
|
|
664 |
|
|
|
665 |
/* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ |
|
|
666 |
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
|
|
667 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
|
|
668 |
RCC_CFGR_PLLMULL6); |
|
|
669 |
#else |
|
|
670 |
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ |
|
|
671 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
|
|
672 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); |
|
|
673 |
#endif /* STM32F10X_CL */ |
|
|
674 |
|
|
|
675 |
/* Enable PLL */ |
|
|
676 |
RCC->CR |= RCC_CR_PLLON; |
|
|
677 |
|
|
|
678 |
/* Wait till PLL is ready */ |
|
|
679 |
while((RCC->CR & RCC_CR_PLLRDY) == 0) |
|
|
680 |
{ |
|
|
681 |
} |
|
|
682 |
|
|
|
683 |
/* Select PLL as system clock source */ |
|
|
684 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
|
|
685 |
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
|
|
686 |
|
|
|
687 |
/* Wait till PLL is used as system clock source */ |
|
|
688 |
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
|
|
689 |
{ |
|
|
690 |
} |
|
|
691 |
} |
|
|
692 |
else |
|
|
693 |
{ /* If HSE fails to start-up, the application will have wrong clock |
|
|
694 |
configuration. User can add here some code to deal with this error */ |
|
|
695 |
|
|
|
696 |
/* Go to infinite loop */ |
|
|
697 |
while (1) |
|
|
698 |
{ |
|
|
699 |
} |
|
|
700 |
} |
|
|
701 |
} |
|
|
702 |
|
|
|
703 |
#elif defined SYSCLK_FREQ_56MHz |
|
|
704 |
/** |
|
|
705 |
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 |
|
|
706 |
* and PCLK1 prescalers. |
|
|
707 |
* @note This function should be used only after reset. |
|
|
708 |
* @param None |
|
|
709 |
* @retval None |
|
|
710 |
*/ |
|
|
711 |
static void SetSysClockTo56(void) |
|
|
712 |
{ |
|
|
713 |
__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
|
|
714 |
|
|
|
715 |
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
|
|
716 |
/* Enable HSE */ |
|
|
717 |
RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
|
|
718 |
|
|
|
719 |
/* Wait till HSE is ready and if Time out is reached exit */ |
|
|
720 |
do |
|
|
721 |
{ |
|
|
722 |
HSEStatus = RCC->CR & RCC_CR_HSERDY; |
|
|
723 |
StartUpCounter++; |
|
|
724 |
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); |
|
|
725 |
|
|
|
726 |
if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
|
|
727 |
{ |
|
|
728 |
HSEStatus = (uint32_t)0x01; |
|
|
729 |
} |
|
|
730 |
else |
|
|
731 |
{ |
|
|
732 |
HSEStatus = (uint32_t)0x00; |
|
|
733 |
} |
|
|
734 |
|
|
|
735 |
if (HSEStatus == (uint32_t)0x01) |
|
|
736 |
{ |
|
|
737 |
/* Enable Prefetch Buffer */ |
|
|
738 |
FLASH->ACR |= FLASH_ACR_PRFTBE; |
|
|
739 |
|
|
|
740 |
/* Flash 2 wait state */ |
|
|
741 |
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
|
|
742 |
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; |
|
|
743 |
|
|
|
744 |
/* HCLK = SYSCLK */ |
|
|
745 |
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
|
|
746 |
|
|
|
747 |
/* PCLK2 = HCLK */ |
|
|
748 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
|
|
749 |
|
|
|
750 |
/* PCLK1 = HCLK/2 */ |
|
|
751 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; |
|
|
752 |
|
|
|
753 |
#ifdef STM32F10X_CL |
|
|
754 |
/* Configure PLLs ------------------------------------------------------*/ |
|
|
755 |
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
|
|
756 |
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ |
|
|
757 |
|
|
|
758 |
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
|
|
759 |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
|
|
760 |
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
|
|
761 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); |
|
|
762 |
|
|
|
763 |
/* Enable PLL2 */ |
|
|
764 |
RCC->CR |= RCC_CR_PLL2ON; |
|
|
765 |
/* Wait till PLL2 is ready */ |
|
|
766 |
while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
|
|
767 |
{ |
|
|
768 |
} |
|
|
769 |
|
|
|
770 |
|
|
|
771 |
/* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ |
|
|
772 |
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
|
|
773 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
|
|
774 |
RCC_CFGR_PLLMULL7); |
|
|
775 |
#else |
|
|
776 |
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ |
|
|
777 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
|
|
778 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); |
|
|
779 |
|
|
|
780 |
#endif /* STM32F10X_CL */ |
|
|
781 |
|
|
|
782 |
/* Enable PLL */ |
|
|
783 |
RCC->CR |= RCC_CR_PLLON; |
|
|
784 |
|
|
|
785 |
/* Wait till PLL is ready */ |
|
|
786 |
while((RCC->CR & RCC_CR_PLLRDY) == 0) |
|
|
787 |
{ |
|
|
788 |
} |
|
|
789 |
|
|
|
790 |
/* Select PLL as system clock source */ |
|
|
791 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
|
|
792 |
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
|
|
793 |
|
|
|
794 |
/* Wait till PLL is used as system clock source */ |
|
|
795 |
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
|
|
796 |
{ |
|
|
797 |
} |
|
|
798 |
} |
|
|
799 |
else |
|
|
800 |
{ /* If HSE fails to start-up, the application will have wrong clock |
|
|
801 |
configuration. User can add here some code to deal with this error */ |
|
|
802 |
|
|
|
803 |
/* Go to infinite loop */ |
|
|
804 |
while (1) |
|
|
805 |
{ |
|
|
806 |
} |
|
|
807 |
} |
|
|
808 |
} |
|
|
809 |
|
|
|
810 |
#elif defined SYSCLK_FREQ_72MHz |
|
|
811 |
/** |
|
|
812 |
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 |
|
|
813 |
* and PCLK1 prescalers. |
|
|
814 |
* @note This function should be used only after reset. |
|
|
815 |
* @param None |
|
|
816 |
* @retval None |
|
|
817 |
*/ |
|
|
818 |
static void SetSysClockTo72(void) |
|
|
819 |
{ |
|
|
820 |
__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
|
|
821 |
|
|
|
822 |
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ |
|
|
823 |
/* Enable HSE */ |
|
|
824 |
RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
|
|
825 |
|
|
|
826 |
/* Wait till HSE is ready and if Time out is reached exit */ |
|
|
827 |
do |
|
|
828 |
{ |
|
|
829 |
HSEStatus = RCC->CR & RCC_CR_HSERDY; |
|
|
830 |
StartUpCounter++; |
|
|
831 |
} while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); |
|
|
832 |
|
|
|
833 |
if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
|
|
834 |
{ |
|
|
835 |
HSEStatus = (uint32_t)0x01; |
|
|
836 |
} |
|
|
837 |
else |
|
|
838 |
{ |
|
|
839 |
HSEStatus = (uint32_t)0x00; |
|
|
840 |
} |
|
|
841 |
|
|
|
842 |
if (HSEStatus == (uint32_t)0x01) |
|
|
843 |
{ |
|
|
844 |
/* Enable Prefetch Buffer */ |
|
|
845 |
FLASH->ACR |= FLASH_ACR_PRFTBE; |
|
|
846 |
|
|
|
847 |
/* Flash 2 wait state */ |
|
|
848 |
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
|
|
849 |
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; |
|
|
850 |
|
|
|
851 |
|
|
|
852 |
/* HCLK = SYSCLK */ |
|
|
853 |
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
|
|
854 |
|
|
|
855 |
/* PCLK2 = HCLK */ |
|
|
856 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
|
|
857 |
|
|
|
858 |
/* PCLK1 = HCLK/2 */ |
|
|
859 |
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; |
|
|
860 |
|
|
|
861 |
#ifdef STM32F10X_CL |
|
|
862 |
/* Configure PLLs ------------------------------------------------------*/ |
|
|
863 |
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ |
|
|
864 |
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ |
|
|
865 |
|
|
|
866 |
RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
|
|
867 |
RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
|
|
868 |
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
|
|
869 |
RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); |
|
|
870 |
|
|
|
871 |
/* Enable PLL2 */ |
|
|
872 |
RCC->CR |= RCC_CR_PLL2ON; |
|
|
873 |
/* Wait till PLL2 is ready */ |
|
|
874 |
while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
|
|
875 |
{ |
|
|
876 |
} |
|
|
877 |
|
|
|
878 |
|
|
|
879 |
/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ |
|
|
880 |
RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
|
|
881 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
|
|
882 |
RCC_CFGR_PLLMULL9); |
|
|
883 |
#else |
|
|
884 |
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ |
|
|
885 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | |
|
|
886 |
RCC_CFGR_PLLMULL)); |
|
|
887 |
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); |
|
|
888 |
#endif /* STM32F10X_CL */ |
|
|
889 |
|
|
|
890 |
/* Enable PLL */ |
|
|
891 |
RCC->CR |= RCC_CR_PLLON; |
|
|
892 |
|
|
|
893 |
/* Wait till PLL is ready */ |
|
|
894 |
while((RCC->CR & RCC_CR_PLLRDY) == 0) |
|
|
895 |
{ |
|
|
896 |
} |
|
|
897 |
|
|
|
898 |
/* Select PLL as system clock source */ |
|
|
899 |
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
|
|
900 |
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
|
|
901 |
|
|
|
902 |
/* Wait till PLL is used as system clock source */ |
|
|
903 |
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
|
|
904 |
{ |
|
|
905 |
} |
|
|
906 |
} |
|
|
907 |
else |
|
|
908 |
{ /* If HSE fails to start-up, the application will have wrong clock |
|
|
909 |
configuration. User can add here some code to deal with this error */ |
|
|
910 |
|
|
|
911 |
/* Go to infinite loop */ |
|
|
912 |
while (1) |
|
|
913 |
{ |
|
|
914 |
} |
|
|
915 |
} |
|
|
916 |
} |
|
|
917 |
#endif |
|
|
918 |
|
|
|
919 |
/** |
|
|
920 |
* @} |
|
|
921 |
*/ |
|
|
922 |
|
|
|
923 |
/** |
|
|
924 |
* @} |
|
|
925 |
*/ |
|
|
926 |
|
|
|
927 |
/** |
|
|
928 |
* @} |
|
|
929 |
*/ |
|
|
930 |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ |