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/** |
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****************************************************************************** |
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* @file stm32f10x_fsmc.h |
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* @author MCD Application Team |
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* @version V3.1.0 |
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* @date 06/19/2009 |
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* @brief This file contains all the functions prototypes for the FSMC firmware |
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* library. |
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****************************************************************************** |
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* @copy |
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* |
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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* |
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F10x_FSMC_H |
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#define __STM32F10x_FSMC_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f10x.h" |
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/** @addtogroup STM32F10x_StdPeriph_Driver |
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* @{ |
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*/ |
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/** @addtogroup FSMC |
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* @{ |
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*/ |
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/** @defgroup FSMC_Exported_Types |
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* @{ |
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*/ |
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/** |
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* @brief Timing parameters For NOR/SRAM Banks |
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*/ |
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typedef struct |
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{ |
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uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
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the duration of the address setup time. |
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This parameter can be a value between 0 and 0xF. |
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@note: It is not used with synchronous NOR Flash memories. */ |
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uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
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the duration of the address hold time. |
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This parameter can be a value between 0 and 0xF. |
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@note: It is not used with synchronous NOR Flash memories.*/ |
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uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
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the duration of the data setup time. |
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This parameter can be a value between 0 and 0xFF. |
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@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ |
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uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
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the duration of the bus turnaround. |
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This parameter can be a value between 0 and 0xF. |
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@note: It is only used for multiplexed NOR Flash memories. */ |
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uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. |
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This parameter can be a value between 1 and 0xF. |
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@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ |
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uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue |
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to the memory before getting the first data. |
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The value of this parameter depends on the memory type as shown below: |
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- It must be set to 0 in case of a CRAM |
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- It is dont care in asynchronous NOR, SRAM or ROM accesses |
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- It may assume a value between 0 and 0xF in NOR Flash memories |
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with synchronous burst mode enable */ |
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uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. |
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This parameter can be a value of @ref FSMC_Access_Mode */ |
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}FSMC_NORSRAMTimingInitTypeDef; |
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/** |
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* @brief FSMC NOR/SRAM Init structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. |
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This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
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uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are |
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multiplexed on the databus or not. |
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This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
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uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to |
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the corresponding memory bank. |
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This parameter can be a value of @ref FSMC_Memory_Type */ |
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uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. |
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This parameter can be a value of @ref FSMC_Data_Width */ |
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uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
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valid only with synchronous burst Flash memories. |
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This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
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uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
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the Flash memory in burst mode. |
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This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
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uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
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memory, valid only when accessing Flash memories in burst mode. |
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This parameter can be a value of @ref FSMC_Wrap_Mode */ |
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uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
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clock cycle before the wait state or during the wait state, |
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valid only when accessing memories in burst mode. |
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This parameter can be a value of @ref FSMC_Wait_Timing */ |
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uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. |
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This parameter can be a value of @ref FSMC_Write_Operation */ |
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uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait |
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signal, valid for Flash memory access in burst mode. |
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This parameter can be a value of @ref FSMC_Wait_Signal */ |
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uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. |
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This parameter can be a value of @ref FSMC_Extended_Mode */ |
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uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. |
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This parameter can be a value of @ref FSMC_Write_Burst */ |
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FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ |
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FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ |
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}FSMC_NORSRAMInitTypeDef; |
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/** |
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* @brief Timing parameters For FSMC NAND and PCCARD Banks |
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*/ |
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typedef struct |
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{ |
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uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
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the command assertion for NAND-Flash read or write access |
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to common/Attribute or I/O memory space (depending on |
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the memory space timing to be configured). |
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This parameter can be a value between 0 and 0xFF.*/ |
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uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
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command for NAND-Flash read or write access to |
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common/Attribute or I/O memory space (depending on the |
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memory space timing to be configured). |
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This parameter can be a number between 0x00 and 0xFF */ |
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uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
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(and data for write access) after the command deassertion |
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for NAND-Flash read or write access to common/Attribute |
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or I/O memory space (depending on the memory space timing |
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to be configured). |
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This parameter can be a number between 0x00 and 0xFF */ |
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uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
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databus is kept in HiZ after the start of a NAND-Flash |
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write access to common/Attribute or I/O memory space (depending |
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on the memory space timing to be configured). |
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This parameter can be a number between 0x00 and 0xFF */ |
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}FSMC_NAND_PCCARDTimingInitTypeDef; |
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/** |
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* @brief FSMC NAND Init structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. |
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This parameter can be a value of @ref FSMC_NAND_Bank */ |
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uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. |
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This parameter can be any value of @ref FSMC_Wait_feature */ |
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uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. |
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This parameter can be any value of @ref FSMC_Data_Width */ |
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uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. |
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This parameter can be any value of @ref FSMC_ECC */ |
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uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. |
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This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
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uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
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delay between CLE low and RE low. |
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This parameter can be a value between 0 and 0xFF. */ |
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uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
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delay between ALE low and RE low. |
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This parameter can be a number between 0x0 and 0xFF */ |
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ |
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ |
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}FSMC_NANDInitTypeDef; |
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/** |
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* @brief FSMC PCCARD Init structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. |
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This parameter can be any value of @ref FSMC_Wait_feature */ |
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uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
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delay between CLE low and RE low. |
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This parameter can be a value between 0 and 0xFF. */ |
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uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
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delay between ALE low and RE low. |
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This parameter can be a number between 0x0 and 0xFF */ |
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ |
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ |
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ |
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}FSMC_PCCARDInitTypeDef; |
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/** |
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* @} |
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*/ |
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/** @defgroup FSMC_Exported_Constants |
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* @{ |
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*/ |
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/** @defgroup FSMC_NORSRAM_Bank |
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* @{ |
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*/ |
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#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) |
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#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) |
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#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) |
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#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) |
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/** |
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* @} |
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*/ |
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/** @defgroup FSMC_NAND_Bank |
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* @{ |
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*/ |
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#define FSMC_Bank2_NAND ((uint32_t)0x00000010) |
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#define FSMC_Bank3_NAND ((uint32_t)0x00000100) |
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/** |
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* @} |
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*/ |
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/** @defgroup FSMC_PCCARD_Bank |
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* @{ |
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*/ |
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#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) |
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/** |
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* @} |
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*/ |
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#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ |
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((BANK) == FSMC_Bank1_NORSRAM2) || \ |
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((BANK) == FSMC_Bank1_NORSRAM3) || \ |
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((BANK) == FSMC_Bank1_NORSRAM4)) |
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#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ |
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((BANK) == FSMC_Bank3_NAND)) |
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#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ |
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((BANK) == FSMC_Bank3_NAND) || \ |
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((BANK) == FSMC_Bank4_PCCARD)) |
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#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ |
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((BANK) == FSMC_Bank3_NAND) || \ |
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((BANK) == FSMC_Bank4_PCCARD)) |
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/** @defgroup NOR_SRAM_Controller |
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* @{ |
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*/ |
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/** @defgroup FSMC_Data_Address_Bus_Multiplexing |
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* @{ |
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*/ |
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#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) |
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#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) |
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#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ |
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((MUX) == FSMC_DataAddressMux_Enable)) |
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/** |
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* @} |
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*/ |
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/** @defgroup FSMC_Memory_Type |
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* @{ |
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*/ |
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#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) |
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#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) |
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#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) |
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#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ |
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((MEMORY) == FSMC_MemoryType_PSRAM)|| \ |
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((MEMORY) == FSMC_MemoryType_NOR)) |
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/** |
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* @} |
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*/ |
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/** @defgroup FSMC_Data_Width |
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* @{ |
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*/ |
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#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) |
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#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) |
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#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ |
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((WIDTH) == FSMC_MemoryDataWidth_16b)) |
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/** |
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* @} |
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*/ |
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/** @defgroup FSMC_Burst_Access_Mode |
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* @{ |
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*/ |
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#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) |
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#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) |
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#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ |
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((STATE) == FSMC_BurstAccessMode_Enable)) |
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/** |
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* @} |
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*/ |
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/** @defgroup FSMC_Wait_Signal_Polarity |
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* @{ |
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*/ |
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#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) |
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#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) |
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#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ |
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((POLARITY) == FSMC_WaitSignalPolarity_High)) |
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|
350 |
|
|
|
351 |
/** |
|
|
352 |
* @} |
|
|
353 |
*/ |
|
|
354 |
|
|
|
355 |
/** @defgroup FSMC_Wrap_Mode |
|
|
356 |
* @{ |
|
|
357 |
*/ |
|
|
358 |
|
|
|
359 |
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) |
|
|
360 |
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) |
|
|
361 |
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ |
|
|
362 |
((MODE) == FSMC_WrapMode_Enable)) |
|
|
363 |
|
|
|
364 |
/** |
|
|
365 |
* @} |
|
|
366 |
*/ |
|
|
367 |
|
|
|
368 |
/** @defgroup FSMC_Wait_Timing |
|
|
369 |
* @{ |
|
|
370 |
*/ |
|
|
371 |
|
|
|
372 |
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) |
|
|
373 |
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) |
|
|
374 |
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ |
|
|
375 |
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) |
|
|
376 |
|
|
|
377 |
/** |
|
|
378 |
* @} |
|
|
379 |
*/ |
|
|
380 |
|
|
|
381 |
/** @defgroup FSMC_Write_Operation |
|
|
382 |
* @{ |
|
|
383 |
*/ |
|
|
384 |
|
|
|
385 |
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) |
|
|
386 |
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) |
|
|
387 |
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ |
|
|
388 |
((OPERATION) == FSMC_WriteOperation_Enable)) |
|
|
389 |
|
|
|
390 |
/** |
|
|
391 |
* @} |
|
|
392 |
*/ |
|
|
393 |
|
|
|
394 |
/** @defgroup FSMC_Wait_Signal |
|
|
395 |
* @{ |
|
|
396 |
*/ |
|
|
397 |
|
|
|
398 |
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) |
|
|
399 |
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) |
|
|
400 |
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ |
|
|
401 |
((SIGNAL) == FSMC_WaitSignal_Enable)) |
|
|
402 |
/** |
|
|
403 |
* @} |
|
|
404 |
*/ |
|
|
405 |
|
|
|
406 |
/** @defgroup FSMC_Extended_Mode |
|
|
407 |
* @{ |
|
|
408 |
*/ |
|
|
409 |
|
|
|
410 |
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) |
|
|
411 |
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) |
|
|
412 |
|
|
|
413 |
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ |
|
|
414 |
((MODE) == FSMC_ExtendedMode_Enable)) |
|
|
415 |
|
|
|
416 |
/** |
|
|
417 |
* @} |
|
|
418 |
*/ |
|
|
419 |
|
|
|
420 |
/** @defgroup FSMC_Write_Burst |
|
|
421 |
* @{ |
|
|
422 |
*/ |
|
|
423 |
|
|
|
424 |
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) |
|
|
425 |
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) |
|
|
426 |
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ |
|
|
427 |
((BURST) == FSMC_WriteBurst_Enable)) |
|
|
428 |
/** |
|
|
429 |
* @} |
|
|
430 |
*/ |
|
|
431 |
|
|
|
432 |
/** @defgroup FSMC_Address_Setup_Time |
|
|
433 |
* @{ |
|
|
434 |
*/ |
|
|
435 |
|
|
|
436 |
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) |
|
|
437 |
|
|
|
438 |
/** |
|
|
439 |
* @} |
|
|
440 |
*/ |
|
|
441 |
|
|
|
442 |
/** @defgroup FSMC_Address_Hold_Time |
|
|
443 |
* @{ |
|
|
444 |
*/ |
|
|
445 |
|
|
|
446 |
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) |
|
|
447 |
|
|
|
448 |
/** |
|
|
449 |
* @} |
|
|
450 |
*/ |
|
|
451 |
|
|
|
452 |
/** @defgroup FSMC_Data_Setup_Time |
|
|
453 |
* @{ |
|
|
454 |
*/ |
|
|
455 |
|
|
|
456 |
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) |
|
|
457 |
|
|
|
458 |
/** |
|
|
459 |
* @} |
|
|
460 |
*/ |
|
|
461 |
|
|
|
462 |
/** @defgroup FSMC_Bus_Turn_around_Duration |
|
|
463 |
* @{ |
|
|
464 |
*/ |
|
|
465 |
|
|
|
466 |
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) |
|
|
467 |
|
|
|
468 |
/** |
|
|
469 |
* @} |
|
|
470 |
*/ |
|
|
471 |
|
|
|
472 |
/** @defgroup FSMC_CLK_Division |
|
|
473 |
* @{ |
|
|
474 |
*/ |
|
|
475 |
|
|
|
476 |
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) |
|
|
477 |
|
|
|
478 |
/** |
|
|
479 |
* @} |
|
|
480 |
*/ |
|
|
481 |
|
|
|
482 |
/** @defgroup FSMC_Data_Latency |
|
|
483 |
* @{ |
|
|
484 |
*/ |
|
|
485 |
|
|
|
486 |
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) |
|
|
487 |
|
|
|
488 |
/** |
|
|
489 |
* @} |
|
|
490 |
*/ |
|
|
491 |
|
|
|
492 |
/** @defgroup FSMC_Access_Mode |
|
|
493 |
* @{ |
|
|
494 |
*/ |
|
|
495 |
|
|
|
496 |
#define FSMC_AccessMode_A ((uint32_t)0x00000000) |
|
|
497 |
#define FSMC_AccessMode_B ((uint32_t)0x10000000) |
|
|
498 |
#define FSMC_AccessMode_C ((uint32_t)0x20000000) |
|
|
499 |
#define FSMC_AccessMode_D ((uint32_t)0x30000000) |
|
|
500 |
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ |
|
|
501 |
((MODE) == FSMC_AccessMode_B) || \ |
|
|
502 |
((MODE) == FSMC_AccessMode_C) || \ |
|
|
503 |
((MODE) == FSMC_AccessMode_D)) |
|
|
504 |
|
|
|
505 |
/** |
|
|
506 |
* @} |
|
|
507 |
*/ |
|
|
508 |
|
|
|
509 |
/** |
|
|
510 |
* @} |
|
|
511 |
*/ |
|
|
512 |
|
|
|
513 |
/** @defgroup NAND_PCCARD_Controller |
|
|
514 |
* @{ |
|
|
515 |
*/ |
|
|
516 |
|
|
|
517 |
/** @defgroup FSMC_Wait_feature |
|
|
518 |
* @{ |
|
|
519 |
*/ |
|
|
520 |
|
|
|
521 |
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) |
|
|
522 |
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) |
|
|
523 |
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ |
|
|
524 |
((FEATURE) == FSMC_Waitfeature_Enable)) |
|
|
525 |
|
|
|
526 |
/** |
|
|
527 |
* @} |
|
|
528 |
*/ |
|
|
529 |
|
|
|
530 |
|
|
|
531 |
/** @defgroup FSMC_ECC |
|
|
532 |
* @{ |
|
|
533 |
*/ |
|
|
534 |
|
|
|
535 |
#define FSMC_ECC_Disable ((uint32_t)0x00000000) |
|
|
536 |
#define FSMC_ECC_Enable ((uint32_t)0x00000040) |
|
|
537 |
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ |
|
|
538 |
((STATE) == FSMC_ECC_Enable)) |
|
|
539 |
|
|
|
540 |
/** |
|
|
541 |
* @} |
|
|
542 |
*/ |
|
|
543 |
|
|
|
544 |
/** @defgroup FSMC_ECC_Page_Size |
|
|
545 |
* @{ |
|
|
546 |
*/ |
|
|
547 |
|
|
|
548 |
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) |
|
|
549 |
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) |
|
|
550 |
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) |
|
|
551 |
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) |
|
|
552 |
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) |
|
|
553 |
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) |
|
|
554 |
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ |
|
|
555 |
((SIZE) == FSMC_ECCPageSize_512Bytes) || \ |
|
|
556 |
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ |
|
|
557 |
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ |
|
|
558 |
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ |
|
|
559 |
((SIZE) == FSMC_ECCPageSize_8192Bytes)) |
|
|
560 |
|
|
|
561 |
/** |
|
|
562 |
* @} |
|
|
563 |
*/ |
|
|
564 |
|
|
|
565 |
/** @defgroup FSMC_TCLR_Setup_Time |
|
|
566 |
* @{ |
|
|
567 |
*/ |
|
|
568 |
|
|
|
569 |
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) |
|
|
570 |
|
|
|
571 |
/** |
|
|
572 |
* @} |
|
|
573 |
*/ |
|
|
574 |
|
|
|
575 |
/** @defgroup FSMC_TAR_Setup_Time |
|
|
576 |
* @{ |
|
|
577 |
*/ |
|
|
578 |
|
|
|
579 |
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) |
|
|
580 |
|
|
|
581 |
/** |
|
|
582 |
* @} |
|
|
583 |
*/ |
|
|
584 |
|
|
|
585 |
/** @defgroup FSMC_Setup_Time |
|
|
586 |
* @{ |
|
|
587 |
*/ |
|
|
588 |
|
|
|
589 |
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) |
|
|
590 |
|
|
|
591 |
/** |
|
|
592 |
* @} |
|
|
593 |
*/ |
|
|
594 |
|
|
|
595 |
/** @defgroup FSMC_Wait_Setup_Time |
|
|
596 |
* @{ |
|
|
597 |
*/ |
|
|
598 |
|
|
|
599 |
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) |
|
|
600 |
|
|
|
601 |
/** |
|
|
602 |
* @} |
|
|
603 |
*/ |
|
|
604 |
|
|
|
605 |
/** @defgroup FSMC_Hold_Setup_Time |
|
|
606 |
* @{ |
|
|
607 |
*/ |
|
|
608 |
|
|
|
609 |
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) |
|
|
610 |
|
|
|
611 |
/** |
|
|
612 |
* @} |
|
|
613 |
*/ |
|
|
614 |
|
|
|
615 |
/** @defgroup FSMC_HiZ_Setup_Time |
|
|
616 |
* @{ |
|
|
617 |
*/ |
|
|
618 |
|
|
|
619 |
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) |
|
|
620 |
|
|
|
621 |
/** |
|
|
622 |
* @} |
|
|
623 |
*/ |
|
|
624 |
|
|
|
625 |
/** @defgroup FSMC_Interrupt_sources |
|
|
626 |
* @{ |
|
|
627 |
*/ |
|
|
628 |
|
|
|
629 |
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) |
|
|
630 |
#define FSMC_IT_Level ((uint32_t)0x00000010) |
|
|
631 |
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) |
|
|
632 |
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) |
|
|
633 |
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ |
|
|
634 |
((IT) == FSMC_IT_Level) || \ |
|
|
635 |
((IT) == FSMC_IT_FallingEdge)) |
|
|
636 |
/** |
|
|
637 |
* @} |
|
|
638 |
*/ |
|
|
639 |
|
|
|
640 |
/** @defgroup FSMC_Flags |
|
|
641 |
* @{ |
|
|
642 |
*/ |
|
|
643 |
|
|
|
644 |
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) |
|
|
645 |
#define FSMC_FLAG_Level ((uint32_t)0x00000002) |
|
|
646 |
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) |
|
|
647 |
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) |
|
|
648 |
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ |
|
|
649 |
((FLAG) == FSMC_FLAG_Level) || \ |
|
|
650 |
((FLAG) == FSMC_FLAG_FallingEdge) || \ |
|
|
651 |
((FLAG) == FSMC_FLAG_FEMPT)) |
|
|
652 |
|
|
|
653 |
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) |
|
|
654 |
|
|
|
655 |
/** |
|
|
656 |
* @} |
|
|
657 |
*/ |
|
|
658 |
|
|
|
659 |
/** |
|
|
660 |
* @} |
|
|
661 |
*/ |
|
|
662 |
|
|
|
663 |
/** |
|
|
664 |
* @} |
|
|
665 |
*/ |
|
|
666 |
|
|
|
667 |
/** @defgroup FSMC_Exported_Macros |
|
|
668 |
* @{ |
|
|
669 |
*/ |
|
|
670 |
|
|
|
671 |
/** |
|
|
672 |
* @} |
|
|
673 |
*/ |
|
|
674 |
|
|
|
675 |
/** @defgroup FSMC_Exported_Functions |
|
|
676 |
* @{ |
|
|
677 |
*/ |
|
|
678 |
|
|
|
679 |
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); |
|
|
680 |
void FSMC_NANDDeInit(uint32_t FSMC_Bank); |
|
|
681 |
void FSMC_PCCARDDeInit(void); |
|
|
682 |
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); |
|
|
683 |
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); |
|
|
684 |
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); |
|
|
685 |
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); |
|
|
686 |
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); |
|
|
687 |
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); |
|
|
688 |
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); |
|
|
689 |
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); |
|
|
690 |
void FSMC_PCCARDCmd(FunctionalState NewState); |
|
|
691 |
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); |
|
|
692 |
uint32_t FSMC_GetECC(uint32_t FSMC_Bank); |
|
|
693 |
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); |
|
|
694 |
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); |
|
|
695 |
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); |
|
|
696 |
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); |
|
|
697 |
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); |
|
|
698 |
|
|
|
699 |
#ifdef __cplusplus |
|
|
700 |
} |
|
|
701 |
#endif |
|
|
702 |
|
|
|
703 |
#endif /*__STM32F10x_FSMC_H */ |
|
|
704 |
/** |
|
|
705 |
* @} |
|
|
706 |
*/ |
|
|
707 |
|
|
|
708 |
/** |
|
|
709 |
* @} |
|
|
710 |
*/ |
|
|
711 |
|
|
|
712 |
/** |
|
|
713 |
* @} |
|
|
714 |
*/ |
|
|
715 |
|
|
|
716 |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ |