Rev Author Line No. Line
3328 povik 1 /**
2 ******************************************************************************
3 * @file stm32f10x_sdio.h
4 * @author MCD Application Team
5 * @version V3.1.0
6 * @date 06/19/2009
7 * @brief This file contains all the functions prototypes for the SDIO firmware
8 * library.
9 ******************************************************************************
10 * @copy
11 *
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 *
19 * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
20 */
21  
22 /* Define to prevent recursive inclusion -------------------------------------*/
23 #ifndef __STM32F10x_SDIO_H
24 #define __STM32F10x_SDIO_H
25  
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29  
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32f10x.h"
32  
33 /** @addtogroup STM32F10x_StdPeriph_Driver
34 * @{
35 */
36  
37 /** @addtogroup SDIO
38 * @{
39 */
40  
41 /** @defgroup SDIO_Exported_Types
42 * @{
43 */
44  
45 typedef struct
46 {
47 uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
48 This parameter can be a value of @ref SDIO_Clock_Edge */
49  
50 uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
51 enabled or disabled.
52 This parameter can be a value of @ref SDIO_Clock_Bypass */
53  
54 uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
55 disabled when the bus is idle.
56 This parameter can be a value of @ref SDIO_Clock_Power_Save */
57  
58 uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
59 This parameter can be a value of @ref SDIO_Bus_Wide */
60  
61 uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
62 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
63  
64 uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
65 This parameter can be a value between 0x00 and 0xFF. */
66  
67 } SDIO_InitTypeDef;
68  
69 typedef struct
70 {
71 uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
72 to a card as part of a command message. If a command
73 contains an argument, it must be loaded into this register
74 before writing the command to the command register */
75  
76 uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
77  
78 uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
79 This parameter can be a value of @ref SDIO_Response_Type */
80  
81 uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
82 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
83  
84 uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
85 is enabled or disabled.
86 This parameter can be a value of @ref SDIO_CPSM_State */
87 } SDIO_CmdInitTypeDef;
88  
89 typedef struct
90 {
91 uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
92  
93 uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
94  
95 uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
96 This parameter can be a value of @ref SDIO_Data_Block_Size */
97  
98 uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
99 is a read or write.
100 This parameter can be a value of @ref SDIO_Transfer_Direction */
101  
102 uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
103 This parameter can be a value of @ref SDIO_Transfer_Type */
104  
105 uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
106 is enabled or disabled.
107 This parameter can be a value of @ref SDIO_DPSM_State */
108 } SDIO_DataInitTypeDef;
109  
110 /**
111 * @}
112 */
113  
114 /** @defgroup SDIO_Exported_Constants
115 * @{
116 */
117  
118 /** @defgroup SDIO_Clock_Edge
119 * @{
120 */
121  
122 #define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
123 #define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
124 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
125 ((EDGE) == SDIO_ClockEdge_Falling))
126 /**
127 * @}
128 */
129  
130 /** @defgroup SDIO_Clock_Bypass
131 * @{
132 */
133  
134 #define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
135 #define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
136 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
137 ((BYPASS) == SDIO_ClockBypass_Enable))
138 /**
139 * @}
140 */
141  
142 /** @defgroup SDIO_Clock_Power_Save
143 * @{
144 */
145  
146 #define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
147 #define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
148 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
149 ((SAVE) == SDIO_ClockPowerSave_Enable))
150 /**
151 * @}
152 */
153  
154 /** @defgroup SDIO_Bus_Wide
155 * @{
156 */
157  
158 #define SDIO_BusWide_1b ((uint32_t)0x00000000)
159 #define SDIO_BusWide_4b ((uint32_t)0x00000800)
160 #define SDIO_BusWide_8b ((uint32_t)0x00001000)
161 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
162 ((WIDE) == SDIO_BusWide_8b))
163  
164 /**
165 * @}
166 */
167  
168 /** @defgroup SDIO_Hardware_Flow_Control
169 * @{
170 */
171  
172 #define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
173 #define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
174 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
175 ((CONTROL) == SDIO_HardwareFlowControl_Enable))
176 /**
177 * @}
178 */
179  
180 /** @defgroup SDIO_Power_State
181 * @{
182 */
183  
184 #define SDIO_PowerState_OFF ((uint32_t)0x00000000)
185 #define SDIO_PowerState_ON ((uint32_t)0x00000003)
186 #define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
187 /**
188 * @}
189 */
190  
191  
192 /** @defgroup SDIO_Interrupt_soucres
193 * @{
194 */
195  
196 #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
197 #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
198 #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
199 #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
200 #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
201 #define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
202 #define SDIO_IT_CMDREND ((uint32_t)0x00000040)
203 #define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
204 #define SDIO_IT_DATAEND ((uint32_t)0x00000100)
205 #define SDIO_IT_STBITERR ((uint32_t)0x00000200)
206 #define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
207 #define SDIO_IT_CMDACT ((uint32_t)0x00000800)
208 #define SDIO_IT_TXACT ((uint32_t)0x00001000)
209 #define SDIO_IT_RXACT ((uint32_t)0x00002000)
210 #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
211 #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
212 #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
213 #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
214 #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
215 #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
216 #define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
217 #define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
218 #define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
219 #define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
220 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
221 /**
222 * @}
223 */
224  
225 /** @defgroup SDIO_Command_Index
226 * @{
227 */
228  
229 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
230 /**
231 * @}
232 */
233  
234 /** @defgroup SDIO_Response_Type
235 * @{
236 */
237  
238 #define SDIO_Response_No ((uint32_t)0x00000000)
239 #define SDIO_Response_Short ((uint32_t)0x00000040)
240 #define SDIO_Response_Long ((uint32_t)0x000000C0)
241 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
242 ((RESPONSE) == SDIO_Response_Short) || \
243 ((RESPONSE) == SDIO_Response_Long))
244 /**
245 * @}
246 */
247  
248 /** @defgroup SDIO_Wait_Interrupt_State
249 * @{
250 */
251  
252 #define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
253 #define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
254 #define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
255 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
256 ((WAIT) == SDIO_Wait_Pend))
257 /**
258 * @}
259 */
260  
261 /** @defgroup SDIO_CPSM_State
262 * @{
263 */
264  
265 #define SDIO_CPSM_Disable ((uint32_t)0x00000000)
266 #define SDIO_CPSM_Enable ((uint32_t)0x00000400)
267 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
268 /**
269 * @}
270 */
271  
272 /** @defgroup SDIO_Response_Registers
273 * @{
274 */
275  
276 #define SDIO_RESP1 ((uint32_t)0x00000000)
277 #define SDIO_RESP2 ((uint32_t)0x00000004)
278 #define SDIO_RESP3 ((uint32_t)0x00000008)
279 #define SDIO_RESP4 ((uint32_t)0x0000000C)
280 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
281 ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
282 /**
283 * @}
284 */
285  
286 /** @defgroup SDIO_Data_Length
287 * @{
288 */
289  
290 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
291 /**
292 * @}
293 */
294  
295 /** @defgroup SDIO_Data_Block_Size
296 * @{
297 */
298  
299 #define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
300 #define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
301 #define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
302 #define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
303 #define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
304 #define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
305 #define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
306 #define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
307 #define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
308 #define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
309 #define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
310 #define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
311 #define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
312 #define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
313 #define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
314 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
315 ((SIZE) == SDIO_DataBlockSize_2b) || \
316 ((SIZE) == SDIO_DataBlockSize_4b) || \
317 ((SIZE) == SDIO_DataBlockSize_8b) || \
318 ((SIZE) == SDIO_DataBlockSize_16b) || \
319 ((SIZE) == SDIO_DataBlockSize_32b) || \
320 ((SIZE) == SDIO_DataBlockSize_64b) || \
321 ((SIZE) == SDIO_DataBlockSize_128b) || \
322 ((SIZE) == SDIO_DataBlockSize_256b) || \
323 ((SIZE) == SDIO_DataBlockSize_512b) || \
324 ((SIZE) == SDIO_DataBlockSize_1024b) || \
325 ((SIZE) == SDIO_DataBlockSize_2048b) || \
326 ((SIZE) == SDIO_DataBlockSize_4096b) || \
327 ((SIZE) == SDIO_DataBlockSize_8192b) || \
328 ((SIZE) == SDIO_DataBlockSize_16384b))
329 /**
330 * @}
331 */
332  
333 /** @defgroup SDIO_Transfer_Direction
334 * @{
335 */
336  
337 #define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
338 #define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
339 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
340 ((DIR) == SDIO_TransferDir_ToSDIO))
341 /**
342 * @}
343 */
344  
345 /** @defgroup SDIO_Transfer_Type
346 * @{
347 */
348  
349 #define SDIO_TransferMode_Block ((uint32_t)0x00000000)
350 #define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
351 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
352 ((MODE) == SDIO_TransferMode_Block))
353 /**
354 * @}
355 */
356  
357 /** @defgroup SDIO_DPSM_State
358 * @{
359 */
360  
361 #define SDIO_DPSM_Disable ((uint32_t)0x00000000)
362 #define SDIO_DPSM_Enable ((uint32_t)0x00000001)
363 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
364 /**
365 * @}
366 */
367  
368 /** @defgroup SDIO_Flags
369 * @{
370 */
371  
372 #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
373 #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
374 #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
375 #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
376 #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
377 #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
378 #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
379 #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
380 #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
381 #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
382 #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
383 #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
384 #define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
385 #define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
386 #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
387 #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
388 #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
389 #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
390 #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
391 #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
392 #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
393 #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
394 #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
395 #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
396 #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
397 ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
398 ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
399 ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
400 ((FLAG) == SDIO_FLAG_TXUNDERR) || \
401 ((FLAG) == SDIO_FLAG_RXOVERR) || \
402 ((FLAG) == SDIO_FLAG_CMDREND) || \
403 ((FLAG) == SDIO_FLAG_CMDSENT) || \
404 ((FLAG) == SDIO_FLAG_DATAEND) || \
405 ((FLAG) == SDIO_FLAG_STBITERR) || \
406 ((FLAG) == SDIO_FLAG_DBCKEND) || \
407 ((FLAG) == SDIO_FLAG_CMDACT) || \
408 ((FLAG) == SDIO_FLAG_TXACT) || \
409 ((FLAG) == SDIO_FLAG_RXACT) || \
410 ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
411 ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
412 ((FLAG) == SDIO_FLAG_TXFIFOF) || \
413 ((FLAG) == SDIO_FLAG_RXFIFOF) || \
414 ((FLAG) == SDIO_FLAG_TXFIFOE) || \
415 ((FLAG) == SDIO_FLAG_RXFIFOE) || \
416 ((FLAG) == SDIO_FLAG_TXDAVL) || \
417 ((FLAG) == SDIO_FLAG_RXDAVL) || \
418 ((FLAG) == SDIO_FLAG_SDIOIT) || \
419 ((FLAG) == SDIO_FLAG_CEATAEND))
420  
421 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
422  
423 #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
424 ((IT) == SDIO_IT_DCRCFAIL) || \
425 ((IT) == SDIO_IT_CTIMEOUT) || \
426 ((IT) == SDIO_IT_DTIMEOUT) || \
427 ((IT) == SDIO_IT_TXUNDERR) || \
428 ((IT) == SDIO_IT_RXOVERR) || \
429 ((IT) == SDIO_IT_CMDREND) || \
430 ((IT) == SDIO_IT_CMDSENT) || \
431 ((IT) == SDIO_IT_DATAEND) || \
432 ((IT) == SDIO_IT_STBITERR) || \
433 ((IT) == SDIO_IT_DBCKEND) || \
434 ((IT) == SDIO_IT_CMDACT) || \
435 ((IT) == SDIO_IT_TXACT) || \
436 ((IT) == SDIO_IT_RXACT) || \
437 ((IT) == SDIO_IT_TXFIFOHE) || \
438 ((IT) == SDIO_IT_RXFIFOHF) || \
439 ((IT) == SDIO_IT_TXFIFOF) || \
440 ((IT) == SDIO_IT_RXFIFOF) || \
441 ((IT) == SDIO_IT_TXFIFOE) || \
442 ((IT) == SDIO_IT_RXFIFOE) || \
443 ((IT) == SDIO_IT_TXDAVL) || \
444 ((IT) == SDIO_IT_RXDAVL) || \
445 ((IT) == SDIO_IT_SDIOIT) || \
446 ((IT) == SDIO_IT_CEATAEND))
447  
448 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
449  
450 /**
451 * @}
452 */
453  
454 /** @defgroup SDIO_Read_Wait_Mode
455 * @{
456 */
457  
458 #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
459 #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
460 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
461 ((MODE) == SDIO_ReadWaitMode_DATA2))
462 /**
463 * @}
464 */
465  
466 /**
467 * @}
468 */
469  
470 /** @defgroup SDIO_Exported_Macros
471 * @{
472 */
473  
474 /**
475 * @}
476 */
477  
478 /** @defgroup SDIO_Exported_Functions
479 * @{
480 */
481  
482 void SDIO_DeInit(void);
483 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
484 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
485 void SDIO_ClockCmd(FunctionalState NewState);
486 void SDIO_SetPowerState(uint32_t SDIO_PowerState);
487 uint32_t SDIO_GetPowerState(void);
488 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
489 void SDIO_DMACmd(FunctionalState NewState);
490 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
491 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
492 uint8_t SDIO_GetCommandResponse(void);
493 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
494 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
495 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
496 uint32_t SDIO_GetDataCounter(void);
497 uint32_t SDIO_ReadData(void);
498 void SDIO_WriteData(uint32_t Data);
499 uint32_t SDIO_GetFIFOCount(void);
500 void SDIO_StartSDIOReadWait(FunctionalState NewState);
501 void SDIO_StopSDIOReadWait(FunctionalState NewState);
502 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
503 void SDIO_SetSDIOOperation(FunctionalState NewState);
504 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
505 void SDIO_CommandCompletionCmd(FunctionalState NewState);
506 void SDIO_CEATAITCmd(FunctionalState NewState);
507 void SDIO_SendCEATACmd(FunctionalState NewState);
508 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
509 void SDIO_ClearFlag(uint32_t SDIO_FLAG);
510 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
511 void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
512  
513 #ifdef __cplusplus
514 }
515 #endif
516  
517 #endif /* __STM32F10x_SDIO_H */
518 /**
519 * @}
520 */
521  
522 /**
523 * @}
524 */
525  
526 /**
527 * @}
528 */
529  
530 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/