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/** |
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****************************************************************************** |
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* @file stm32f10x_tim.h |
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* @author MCD Application Team |
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* @version V3.1.0 |
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* @date 06/19/2009 |
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* @brief This file contains all the functions prototypes for the TIM firmware |
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* library. |
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****************************************************************************** |
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* @copy |
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* |
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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* |
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F10x_TIM_H |
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#define __STM32F10x_TIM_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f10x.h" |
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/** @addtogroup STM32F10x_StdPeriph_Driver |
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* @{ |
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*/ |
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/** @addtogroup TIM |
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* @{ |
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*/ |
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/** @defgroup TIM_Exported_Types |
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* @{ |
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*/ |
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/** |
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* @brief TIM Time Base Init structure definition |
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* @note This sturcture is used with all TIMx except for TIM6 and TIM7. |
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*/ |
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typedef struct |
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{ |
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uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
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This parameter can be a number between 0x0000 and 0xFFFF */ |
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uint16_t TIM_CounterMode; /*!< Specifies the counter mode. |
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This parameter can be a value of @ref TIM_Counter_Mode */ |
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uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active |
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Auto-Reload Register at the next update event. |
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This parameter must be a number between 0x0000 and 0xFFFF. */ |
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uint16_t TIM_ClockDivision; /*!< Specifies the clock division. |
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This parameter can be a value of @ref TIM_Clock_Division_CKD */ |
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uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
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reaches zero, an update event is generated and counting restarts |
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from the RCR value (N). |
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This means in PWM mode that (N+1) corresponds to: |
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- the number of PWM periods in edge-aligned mode |
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- the number of half PWM period in center-aligned mode |
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This parameter must be a number between 0x00 and 0xFF. |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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} TIM_TimeBaseInitTypeDef; |
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/** |
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* @brief TIM Output Compare Init structure definition |
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*/ |
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typedef struct |
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{ |
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uint16_t TIM_OCMode; /*!< Specifies the TIM mode. |
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This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
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uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. |
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This parameter can be a value of @ref TIM_Output_Compare_state */ |
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uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. |
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This parameter can be a value of @ref TIM_Output_Compare_N_state |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
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This parameter can be a number between 0x0000 and 0xFFFF */ |
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uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. |
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This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
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uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. |
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This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
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This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
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@note This parameter is valid only for TIM1 and TIM8. */ |
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} TIM_OCInitTypeDef; |
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/** |
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* @brief TIM Input Capture Init structure definition |
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*/ |
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typedef struct |
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{ |
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uint16_t TIM_Channel; /*!< Specifies the TIM channel. |
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This parameter can be a value of @ref TIM_Channel */ |
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uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. |
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
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uint16_t TIM_ICSelection; /*!< Specifies the input. |
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This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
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uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
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This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
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uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. |
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This parameter can be a number between 0x0 and 0xF */ |
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} TIM_ICInitTypeDef; |
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/** |
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* @brief BDTR structure definition |
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* @note This sturcture is used only with TIM1 and TIM8. |
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*/ |
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typedef struct |
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{ |
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uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. |
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This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ |
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uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. |
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This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ |
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uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. |
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This parameter can be a value of @ref Lock_level */ |
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uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the |
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switching-on of the outputs. |
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This parameter can be a number between 0x00 and 0xFF */ |
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uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. |
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This parameter can be a value of @ref Break_Input_enable_disable */ |
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uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. |
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This parameter can be a value of @ref Break_Polarity */ |
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uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. |
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This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
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} TIM_BDTRInitTypeDef; |
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/** @defgroup TIM_Exported_constants |
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* @{ |
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*/ |
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#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM6) || \ |
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((PERIPH) == TIM7) || \ |
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((PERIPH) == TIM8)) |
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#define IS_TIM_18_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
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((PERIPH) == TIM8)) |
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#define IS_TIM_123458_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ |
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM8)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Output_Compare_and_PWM_modes |
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* @{ |
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*/ |
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#define TIM_OCMode_Timing ((uint16_t)0x0000) |
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#define TIM_OCMode_Active ((uint16_t)0x0010) |
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#define TIM_OCMode_Inactive ((uint16_t)0x0020) |
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#define TIM_OCMode_Toggle ((uint16_t)0x0030) |
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#define TIM_OCMode_PWM1 ((uint16_t)0x0060) |
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#define TIM_OCMode_PWM2 ((uint16_t)0x0070) |
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#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ |
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((MODE) == TIM_OCMode_Active) || \ |
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((MODE) == TIM_OCMode_Inactive) || \ |
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((MODE) == TIM_OCMode_Toggle)|| \ |
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((MODE) == TIM_OCMode_PWM1) || \ |
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((MODE) == TIM_OCMode_PWM2)) |
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#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ |
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((MODE) == TIM_OCMode_Active) || \ |
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((MODE) == TIM_OCMode_Inactive) || \ |
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((MODE) == TIM_OCMode_Toggle)|| \ |
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((MODE) == TIM_OCMode_PWM1) || \ |
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((MODE) == TIM_OCMode_PWM2) || \ |
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((MODE) == TIM_ForcedAction_Active) || \ |
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((MODE) == TIM_ForcedAction_InActive)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_One_Pulse_Mode |
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* @{ |
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*/ |
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#define TIM_OPMode_Single ((uint16_t)0x0008) |
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#define TIM_OPMode_Repetitive ((uint16_t)0x0000) |
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#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ |
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((MODE) == TIM_OPMode_Repetitive)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Channel |
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* @{ |
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*/ |
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#define TIM_Channel_1 ((uint16_t)0x0000) |
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#define TIM_Channel_2 ((uint16_t)0x0004) |
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#define TIM_Channel_3 ((uint16_t)0x0008) |
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#define TIM_Channel_4 ((uint16_t)0x000C) |
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#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ |
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((CHANNEL) == TIM_Channel_2) || \ |
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((CHANNEL) == TIM_Channel_3) || \ |
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((CHANNEL) == TIM_Channel_4)) |
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#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ |
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((CHANNEL) == TIM_Channel_2)) |
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#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ |
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((CHANNEL) == TIM_Channel_2) || \ |
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((CHANNEL) == TIM_Channel_3)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Clock_Division_CKD |
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* @{ |
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*/ |
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#define TIM_CKD_DIV1 ((uint16_t)0x0000) |
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#define TIM_CKD_DIV2 ((uint16_t)0x0100) |
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#define TIM_CKD_DIV4 ((uint16_t)0x0200) |
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#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ |
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((DIV) == TIM_CKD_DIV2) || \ |
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((DIV) == TIM_CKD_DIV4)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Counter_Mode |
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* @{ |
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*/ |
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#define TIM_CounterMode_Up ((uint16_t)0x0000) |
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#define TIM_CounterMode_Down ((uint16_t)0x0010) |
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#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) |
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#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) |
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#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) |
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#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ |
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((MODE) == TIM_CounterMode_Down) || \ |
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((MODE) == TIM_CounterMode_CenterAligned1) || \ |
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((MODE) == TIM_CounterMode_CenterAligned2) || \ |
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((MODE) == TIM_CounterMode_CenterAligned3)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Output_Compare_Polarity |
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* @{ |
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*/ |
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#define TIM_OCPolarity_High ((uint16_t)0x0000) |
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#define TIM_OCPolarity_Low ((uint16_t)0x0002) |
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#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ |
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((POLARITY) == TIM_OCPolarity_Low)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Output_Compare_N_Polarity |
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* @{ |
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*/ |
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#define TIM_OCNPolarity_High ((uint16_t)0x0000) |
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#define TIM_OCNPolarity_Low ((uint16_t)0x0008) |
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#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ |
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((POLARITY) == TIM_OCNPolarity_Low)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Output_Compare_state |
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* @{ |
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*/ |
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#define TIM_OutputState_Disable ((uint16_t)0x0000) |
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#define TIM_OutputState_Enable ((uint16_t)0x0001) |
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#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ |
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((STATE) == TIM_OutputState_Enable)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Output_Compare_N_state |
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* @{ |
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*/ |
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#define TIM_OutputNState_Disable ((uint16_t)0x0000) |
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#define TIM_OutputNState_Enable ((uint16_t)0x0004) |
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#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ |
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((STATE) == TIM_OutputNState_Enable)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Capture_Compare_state |
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* @{ |
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*/ |
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#define TIM_CCx_Enable ((uint16_t)0x0001) |
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#define TIM_CCx_Disable ((uint16_t)0x0000) |
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#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ |
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((CCX) == TIM_CCx_Disable)) |
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/** |
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* @} |
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*/ |
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/** @defgroup TIM_Capture_Compare_N_state |
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* @{ |
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*/ |
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#define TIM_CCxN_Enable ((uint16_t)0x0004) |
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#define TIM_CCxN_Disable ((uint16_t)0x0000) |
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#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ |
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((CCXN) == TIM_CCxN_Disable)) |
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/** |
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* @} |
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*/ |
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/** @defgroup Break_Input_enable_disable |
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* @{ |
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*/ |
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#define TIM_Break_Enable ((uint16_t)0x1000) |
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#define TIM_Break_Disable ((uint16_t)0x0000) |
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361 |
#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ |
|
|
362 |
((STATE) == TIM_Break_Disable)) |
|
|
363 |
/** |
|
|
364 |
* @} |
|
|
365 |
*/ |
|
|
366 |
|
|
|
367 |
/** @defgroup Break_Polarity |
|
|
368 |
* @{ |
|
|
369 |
*/ |
|
|
370 |
|
|
|
371 |
#define TIM_BreakPolarity_Low ((uint16_t)0x0000) |
|
|
372 |
#define TIM_BreakPolarity_High ((uint16_t)0x2000) |
|
|
373 |
#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ |
|
|
374 |
((POLARITY) == TIM_BreakPolarity_High)) |
|
|
375 |
/** |
|
|
376 |
* @} |
|
|
377 |
*/ |
|
|
378 |
|
|
|
379 |
/** @defgroup TIM_AOE_Bit_Set_Reset |
|
|
380 |
* @{ |
|
|
381 |
*/ |
|
|
382 |
|
|
|
383 |
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) |
|
|
384 |
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) |
|
|
385 |
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ |
|
|
386 |
((STATE) == TIM_AutomaticOutput_Disable)) |
|
|
387 |
/** |
|
|
388 |
* @} |
|
|
389 |
*/ |
|
|
390 |
|
|
|
391 |
/** @defgroup Lock_level |
|
|
392 |
* @{ |
|
|
393 |
*/ |
|
|
394 |
|
|
|
395 |
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) |
|
|
396 |
#define TIM_LOCKLevel_1 ((uint16_t)0x0100) |
|
|
397 |
#define TIM_LOCKLevel_2 ((uint16_t)0x0200) |
|
|
398 |
#define TIM_LOCKLevel_3 ((uint16_t)0x0300) |
|
|
399 |
#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ |
|
|
400 |
((LEVEL) == TIM_LOCKLevel_1) || \ |
|
|
401 |
((LEVEL) == TIM_LOCKLevel_2) || \ |
|
|
402 |
((LEVEL) == TIM_LOCKLevel_3)) |
|
|
403 |
/** |
|
|
404 |
* @} |
|
|
405 |
*/ |
|
|
406 |
|
|
|
407 |
/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state |
|
|
408 |
* @{ |
|
|
409 |
*/ |
|
|
410 |
|
|
|
411 |
#define TIM_OSSIState_Enable ((uint16_t)0x0400) |
|
|
412 |
#define TIM_OSSIState_Disable ((uint16_t)0x0000) |
|
|
413 |
#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ |
|
|
414 |
((STATE) == TIM_OSSIState_Disable)) |
|
|
415 |
/** |
|
|
416 |
* @} |
|
|
417 |
*/ |
|
|
418 |
|
|
|
419 |
/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state |
|
|
420 |
* @{ |
|
|
421 |
*/ |
|
|
422 |
|
|
|
423 |
#define TIM_OSSRState_Enable ((uint16_t)0x0800) |
|
|
424 |
#define TIM_OSSRState_Disable ((uint16_t)0x0000) |
|
|
425 |
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ |
|
|
426 |
((STATE) == TIM_OSSRState_Disable)) |
|
|
427 |
/** |
|
|
428 |
* @} |
|
|
429 |
*/ |
|
|
430 |
|
|
|
431 |
/** @defgroup TIM_Output_Compare_Idle_State |
|
|
432 |
* @{ |
|
|
433 |
*/ |
|
|
434 |
|
|
|
435 |
#define TIM_OCIdleState_Set ((uint16_t)0x0100) |
|
|
436 |
#define TIM_OCIdleState_Reset ((uint16_t)0x0000) |
|
|
437 |
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ |
|
|
438 |
((STATE) == TIM_OCIdleState_Reset)) |
|
|
439 |
/** |
|
|
440 |
* @} |
|
|
441 |
*/ |
|
|
442 |
|
|
|
443 |
/** @defgroup TIM_Output_Compare_N_Idle_State |
|
|
444 |
* @{ |
|
|
445 |
*/ |
|
|
446 |
|
|
|
447 |
#define TIM_OCNIdleState_Set ((uint16_t)0x0200) |
|
|
448 |
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) |
|
|
449 |
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ |
|
|
450 |
((STATE) == TIM_OCNIdleState_Reset)) |
|
|
451 |
/** |
|
|
452 |
* @} |
|
|
453 |
*/ |
|
|
454 |
|
|
|
455 |
/** @defgroup TIM_Input_Capture_Polarity |
|
|
456 |
* @{ |
|
|
457 |
*/ |
|
|
458 |
|
|
|
459 |
#define TIM_ICPolarity_Rising ((uint16_t)0x0000) |
|
|
460 |
#define TIM_ICPolarity_Falling ((uint16_t)0x0002) |
|
|
461 |
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ |
|
|
462 |
((POLARITY) == TIM_ICPolarity_Falling)) |
|
|
463 |
/** |
|
|
464 |
* @} |
|
|
465 |
*/ |
|
|
466 |
|
|
|
467 |
/** @defgroup TIM_Input_Capture_Selection |
|
|
468 |
* @{ |
|
|
469 |
*/ |
|
|
470 |
|
|
|
471 |
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
|
|
472 |
connected to IC1, IC2, IC3 or IC4, respectively */ |
|
|
473 |
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
|
|
474 |
connected to IC2, IC1, IC4 or IC3, respectively. */ |
|
|
475 |
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ |
|
|
476 |
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ |
|
|
477 |
((SELECTION) == TIM_ICSelection_IndirectTI) || \ |
|
|
478 |
((SELECTION) == TIM_ICSelection_TRC)) |
|
|
479 |
/** |
|
|
480 |
* @} |
|
|
481 |
*/ |
|
|
482 |
|
|
|
483 |
/** @defgroup TIM_Input_Capture_Prescaler |
|
|
484 |
* @{ |
|
|
485 |
*/ |
|
|
486 |
|
|
|
487 |
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ |
|
|
488 |
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ |
|
|
489 |
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ |
|
|
490 |
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ |
|
|
491 |
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ |
|
|
492 |
((PRESCALER) == TIM_ICPSC_DIV2) || \ |
|
|
493 |
((PRESCALER) == TIM_ICPSC_DIV4) || \ |
|
|
494 |
((PRESCALER) == TIM_ICPSC_DIV8)) |
|
|
495 |
/** |
|
|
496 |
* @} |
|
|
497 |
*/ |
|
|
498 |
|
|
|
499 |
/** @defgroup TIM_interrupt_sources |
|
|
500 |
* @{ |
|
|
501 |
*/ |
|
|
502 |
|
|
|
503 |
#define TIM_IT_Update ((uint16_t)0x0001) |
|
|
504 |
#define TIM_IT_CC1 ((uint16_t)0x0002) |
|
|
505 |
#define TIM_IT_CC2 ((uint16_t)0x0004) |
|
|
506 |
#define TIM_IT_CC3 ((uint16_t)0x0008) |
|
|
507 |
#define TIM_IT_CC4 ((uint16_t)0x0010) |
|
|
508 |
#define TIM_IT_COM ((uint16_t)0x0020) |
|
|
509 |
#define TIM_IT_Trigger ((uint16_t)0x0040) |
|
|
510 |
#define TIM_IT_Break ((uint16_t)0x0080) |
|
|
511 |
#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) |
|
|
512 |
|
|
|
513 |
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ |
|
|
514 |
((IT) == TIM_IT_CC1) || \ |
|
|
515 |
((IT) == TIM_IT_CC2) || \ |
|
|
516 |
((IT) == TIM_IT_CC3) || \ |
|
|
517 |
((IT) == TIM_IT_CC4) || \ |
|
|
518 |
((IT) == TIM_IT_COM) || \ |
|
|
519 |
((IT) == TIM_IT_Trigger) || \ |
|
|
520 |
((IT) == TIM_IT_Break)) |
|
|
521 |
/** |
|
|
522 |
* @} |
|
|
523 |
*/ |
|
|
524 |
|
|
|
525 |
/** @defgroup TIM_DMA_Base_address |
|
|
526 |
* @{ |
|
|
527 |
*/ |
|
|
528 |
|
|
|
529 |
#define TIM_DMABase_CR1 ((uint16_t)0x0000) |
|
|
530 |
#define TIM_DMABase_CR2 ((uint16_t)0x0001) |
|
|
531 |
#define TIM_DMABase_SMCR ((uint16_t)0x0002) |
|
|
532 |
#define TIM_DMABase_DIER ((uint16_t)0x0003) |
|
|
533 |
#define TIM_DMABase_SR ((uint16_t)0x0004) |
|
|
534 |
#define TIM_DMABase_EGR ((uint16_t)0x0005) |
|
|
535 |
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) |
|
|
536 |
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) |
|
|
537 |
#define TIM_DMABase_CCER ((uint16_t)0x0008) |
|
|
538 |
#define TIM_DMABase_CNT ((uint16_t)0x0009) |
|
|
539 |
#define TIM_DMABase_PSC ((uint16_t)0x000A) |
|
|
540 |
#define TIM_DMABase_ARR ((uint16_t)0x000B) |
|
|
541 |
#define TIM_DMABase_RCR ((uint16_t)0x000C) |
|
|
542 |
#define TIM_DMABase_CCR1 ((uint16_t)0x000D) |
|
|
543 |
#define TIM_DMABase_CCR2 ((uint16_t)0x000E) |
|
|
544 |
#define TIM_DMABase_CCR3 ((uint16_t)0x000F) |
|
|
545 |
#define TIM_DMABase_CCR4 ((uint16_t)0x0010) |
|
|
546 |
#define TIM_DMABase_BDTR ((uint16_t)0x0011) |
|
|
547 |
#define TIM_DMABase_DCR ((uint16_t)0x0012) |
|
|
548 |
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ |
|
|
549 |
((BASE) == TIM_DMABase_CR2) || \ |
|
|
550 |
((BASE) == TIM_DMABase_SMCR) || \ |
|
|
551 |
((BASE) == TIM_DMABase_DIER) || \ |
|
|
552 |
((BASE) == TIM_DMABase_SR) || \ |
|
|
553 |
((BASE) == TIM_DMABase_EGR) || \ |
|
|
554 |
((BASE) == TIM_DMABase_CCMR1) || \ |
|
|
555 |
((BASE) == TIM_DMABase_CCMR2) || \ |
|
|
556 |
((BASE) == TIM_DMABase_CCER) || \ |
|
|
557 |
((BASE) == TIM_DMABase_CNT) || \ |
|
|
558 |
((BASE) == TIM_DMABase_PSC) || \ |
|
|
559 |
((BASE) == TIM_DMABase_ARR) || \ |
|
|
560 |
((BASE) == TIM_DMABase_RCR) || \ |
|
|
561 |
((BASE) == TIM_DMABase_CCR1) || \ |
|
|
562 |
((BASE) == TIM_DMABase_CCR2) || \ |
|
|
563 |
((BASE) == TIM_DMABase_CCR3) || \ |
|
|
564 |
((BASE) == TIM_DMABase_CCR4) || \ |
|
|
565 |
((BASE) == TIM_DMABase_BDTR) || \ |
|
|
566 |
((BASE) == TIM_DMABase_DCR)) |
|
|
567 |
/** |
|
|
568 |
* @} |
|
|
569 |
*/ |
|
|
570 |
|
|
|
571 |
/** @defgroup TIM_DMA_Burst_Length |
|
|
572 |
* @{ |
|
|
573 |
*/ |
|
|
574 |
|
|
|
575 |
#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) |
|
|
576 |
#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) |
|
|
577 |
#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) |
|
|
578 |
#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) |
|
|
579 |
#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) |
|
|
580 |
#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) |
|
|
581 |
#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) |
|
|
582 |
#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) |
|
|
583 |
#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) |
|
|
584 |
#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) |
|
|
585 |
#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) |
|
|
586 |
#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) |
|
|
587 |
#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) |
|
|
588 |
#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) |
|
|
589 |
#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) |
|
|
590 |
#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) |
|
|
591 |
#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) |
|
|
592 |
#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) |
|
|
593 |
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ |
|
|
594 |
((LENGTH) == TIM_DMABurstLength_2Bytes) || \ |
|
|
595 |
((LENGTH) == TIM_DMABurstLength_3Bytes) || \ |
|
|
596 |
((LENGTH) == TIM_DMABurstLength_4Bytes) || \ |
|
|
597 |
((LENGTH) == TIM_DMABurstLength_5Bytes) || \ |
|
|
598 |
((LENGTH) == TIM_DMABurstLength_6Bytes) || \ |
|
|
599 |
((LENGTH) == TIM_DMABurstLength_7Bytes) || \ |
|
|
600 |
((LENGTH) == TIM_DMABurstLength_8Bytes) || \ |
|
|
601 |
((LENGTH) == TIM_DMABurstLength_9Bytes) || \ |
|
|
602 |
((LENGTH) == TIM_DMABurstLength_10Bytes) || \ |
|
|
603 |
((LENGTH) == TIM_DMABurstLength_11Bytes) || \ |
|
|
604 |
((LENGTH) == TIM_DMABurstLength_12Bytes) || \ |
|
|
605 |
((LENGTH) == TIM_DMABurstLength_13Bytes) || \ |
|
|
606 |
((LENGTH) == TIM_DMABurstLength_14Bytes) || \ |
|
|
607 |
((LENGTH) == TIM_DMABurstLength_15Bytes) || \ |
|
|
608 |
((LENGTH) == TIM_DMABurstLength_16Bytes) || \ |
|
|
609 |
((LENGTH) == TIM_DMABurstLength_17Bytes) || \ |
|
|
610 |
((LENGTH) == TIM_DMABurstLength_18Bytes)) |
|
|
611 |
/** |
|
|
612 |
* @} |
|
|
613 |
*/ |
|
|
614 |
|
|
|
615 |
/** @defgroup TIM_DMA_sources |
|
|
616 |
* @{ |
|
|
617 |
*/ |
|
|
618 |
|
|
|
619 |
#define TIM_DMA_Update ((uint16_t)0x0100) |
|
|
620 |
#define TIM_DMA_CC1 ((uint16_t)0x0200) |
|
|
621 |
#define TIM_DMA_CC2 ((uint16_t)0x0400) |
|
|
622 |
#define TIM_DMA_CC3 ((uint16_t)0x0800) |
|
|
623 |
#define TIM_DMA_CC4 ((uint16_t)0x1000) |
|
|
624 |
#define TIM_DMA_COM ((uint16_t)0x2000) |
|
|
625 |
#define TIM_DMA_Trigger ((uint16_t)0x4000) |
|
|
626 |
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) |
|
|
627 |
|
|
|
628 |
/** |
|
|
629 |
* @} |
|
|
630 |
*/ |
|
|
631 |
|
|
|
632 |
/** @defgroup TIM_External_Trigger_Prescaler |
|
|
633 |
* @{ |
|
|
634 |
*/ |
|
|
635 |
|
|
|
636 |
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) |
|
|
637 |
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) |
|
|
638 |
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) |
|
|
639 |
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) |
|
|
640 |
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ |
|
|
641 |
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ |
|
|
642 |
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ |
|
|
643 |
((PRESCALER) == TIM_ExtTRGPSC_DIV8)) |
|
|
644 |
/** |
|
|
645 |
* @} |
|
|
646 |
*/ |
|
|
647 |
|
|
|
648 |
/** @defgroup TIM_Internal_Trigger_Selection |
|
|
649 |
* @{ |
|
|
650 |
*/ |
|
|
651 |
|
|
|
652 |
#define TIM_TS_ITR0 ((uint16_t)0x0000) |
|
|
653 |
#define TIM_TS_ITR1 ((uint16_t)0x0010) |
|
|
654 |
#define TIM_TS_ITR2 ((uint16_t)0x0020) |
|
|
655 |
#define TIM_TS_ITR3 ((uint16_t)0x0030) |
|
|
656 |
#define TIM_TS_TI1F_ED ((uint16_t)0x0040) |
|
|
657 |
#define TIM_TS_TI1FP1 ((uint16_t)0x0050) |
|
|
658 |
#define TIM_TS_TI2FP2 ((uint16_t)0x0060) |
|
|
659 |
#define TIM_TS_ETRF ((uint16_t)0x0070) |
|
|
660 |
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
|
|
661 |
((SELECTION) == TIM_TS_ITR1) || \ |
|
|
662 |
((SELECTION) == TIM_TS_ITR2) || \ |
|
|
663 |
((SELECTION) == TIM_TS_ITR3) || \ |
|
|
664 |
((SELECTION) == TIM_TS_TI1F_ED) || \ |
|
|
665 |
((SELECTION) == TIM_TS_TI1FP1) || \ |
|
|
666 |
((SELECTION) == TIM_TS_TI2FP2) || \ |
|
|
667 |
((SELECTION) == TIM_TS_ETRF)) |
|
|
668 |
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ |
|
|
669 |
((SELECTION) == TIM_TS_ITR1) || \ |
|
|
670 |
((SELECTION) == TIM_TS_ITR2) || \ |
|
|
671 |
((SELECTION) == TIM_TS_ITR3)) |
|
|
672 |
/** |
|
|
673 |
* @} |
|
|
674 |
*/ |
|
|
675 |
|
|
|
676 |
/** @defgroup TIM_TIx_External_Clock_Source |
|
|
677 |
* @{ |
|
|
678 |
*/ |
|
|
679 |
|
|
|
680 |
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) |
|
|
681 |
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) |
|
|
682 |
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) |
|
|
683 |
#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ |
|
|
684 |
((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ |
|
|
685 |
((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) |
|
|
686 |
/** |
|
|
687 |
* @} |
|
|
688 |
*/ |
|
|
689 |
|
|
|
690 |
/** @defgroup TIM_External_Trigger_Polarity |
|
|
691 |
* @{ |
|
|
692 |
*/ |
|
|
693 |
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) |
|
|
694 |
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) |
|
|
695 |
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ |
|
|
696 |
((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) |
|
|
697 |
/** |
|
|
698 |
* @} |
|
|
699 |
*/ |
|
|
700 |
|
|
|
701 |
/** @defgroup TIM_Prescaler_Reload_Mode |
|
|
702 |
* @{ |
|
|
703 |
*/ |
|
|
704 |
|
|
|
705 |
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) |
|
|
706 |
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) |
|
|
707 |
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ |
|
|
708 |
((RELOAD) == TIM_PSCReloadMode_Immediate)) |
|
|
709 |
/** |
|
|
710 |
* @} |
|
|
711 |
*/ |
|
|
712 |
|
|
|
713 |
/** @defgroup TIM_Forced_Action |
|
|
714 |
* @{ |
|
|
715 |
*/ |
|
|
716 |
|
|
|
717 |
#define TIM_ForcedAction_Active ((uint16_t)0x0050) |
|
|
718 |
#define TIM_ForcedAction_InActive ((uint16_t)0x0040) |
|
|
719 |
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ |
|
|
720 |
((ACTION) == TIM_ForcedAction_InActive)) |
|
|
721 |
/** |
|
|
722 |
* @} |
|
|
723 |
*/ |
|
|
724 |
|
|
|
725 |
/** @defgroup TIM_Encoder_Mode |
|
|
726 |
* @{ |
|
|
727 |
*/ |
|
|
728 |
|
|
|
729 |
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) |
|
|
730 |
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) |
|
|
731 |
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) |
|
|
732 |
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ |
|
|
733 |
((MODE) == TIM_EncoderMode_TI2) || \ |
|
|
734 |
((MODE) == TIM_EncoderMode_TI12)) |
|
|
735 |
/** |
|
|
736 |
* @} |
|
|
737 |
*/ |
|
|
738 |
|
|
|
739 |
|
|
|
740 |
/** @defgroup TIM_Event_Source |
|
|
741 |
* @{ |
|
|
742 |
*/ |
|
|
743 |
|
|
|
744 |
#define TIM_EventSource_Update ((uint16_t)0x0001) |
|
|
745 |
#define TIM_EventSource_CC1 ((uint16_t)0x0002) |
|
|
746 |
#define TIM_EventSource_CC2 ((uint16_t)0x0004) |
|
|
747 |
#define TIM_EventSource_CC3 ((uint16_t)0x0008) |
|
|
748 |
#define TIM_EventSource_CC4 ((uint16_t)0x0010) |
|
|
749 |
#define TIM_EventSource_COM ((uint16_t)0x0020) |
|
|
750 |
#define TIM_EventSource_Trigger ((uint16_t)0x0040) |
|
|
751 |
#define TIM_EventSource_Break ((uint16_t)0x0080) |
|
|
752 |
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) |
|
|
753 |
|
|
|
754 |
/** |
|
|
755 |
* @} |
|
|
756 |
*/ |
|
|
757 |
|
|
|
758 |
/** @defgroup TIM_Update_Source |
|
|
759 |
* @{ |
|
|
760 |
*/ |
|
|
761 |
|
|
|
762 |
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow |
|
|
763 |
or the setting of UG bit, or an update generation |
|
|
764 |
through the slave mode controller. */ |
|
|
765 |
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ |
|
|
766 |
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ |
|
|
767 |
((SOURCE) == TIM_UpdateSource_Regular)) |
|
|
768 |
/** |
|
|
769 |
* @} |
|
|
770 |
*/ |
|
|
771 |
|
|
|
772 |
/** @defgroup TIM_Ouput_Compare_Preload_State |
|
|
773 |
* @{ |
|
|
774 |
*/ |
|
|
775 |
|
|
|
776 |
#define TIM_OCPreload_Enable ((uint16_t)0x0008) |
|
|
777 |
#define TIM_OCPreload_Disable ((uint16_t)0x0000) |
|
|
778 |
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ |
|
|
779 |
((STATE) == TIM_OCPreload_Disable)) |
|
|
780 |
/** |
|
|
781 |
* @} |
|
|
782 |
*/ |
|
|
783 |
|
|
|
784 |
/** @defgroup TIM_Ouput_Compare_Fast_State |
|
|
785 |
* @{ |
|
|
786 |
*/ |
|
|
787 |
|
|
|
788 |
#define TIM_OCFast_Enable ((uint16_t)0x0004) |
|
|
789 |
#define TIM_OCFast_Disable ((uint16_t)0x0000) |
|
|
790 |
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ |
|
|
791 |
((STATE) == TIM_OCFast_Disable)) |
|
|
792 |
|
|
|
793 |
/** |
|
|
794 |
* @} |
|
|
795 |
*/ |
|
|
796 |
|
|
|
797 |
/** @defgroup TIM_Ouput_Compare_Clear_State |
|
|
798 |
* @{ |
|
|
799 |
*/ |
|
|
800 |
|
|
|
801 |
#define TIM_OCClear_Enable ((uint16_t)0x0080) |
|
|
802 |
#define TIM_OCClear_Disable ((uint16_t)0x0000) |
|
|
803 |
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ |
|
|
804 |
((STATE) == TIM_OCClear_Disable)) |
|
|
805 |
/** |
|
|
806 |
* @} |
|
|
807 |
*/ |
|
|
808 |
|
|
|
809 |
/** @defgroup TIM_Trigger_Output_Source |
|
|
810 |
* @{ |
|
|
811 |
*/ |
|
|
812 |
|
|
|
813 |
#define TIM_TRGOSource_Reset ((uint16_t)0x0000) |
|
|
814 |
#define TIM_TRGOSource_Enable ((uint16_t)0x0010) |
|
|
815 |
#define TIM_TRGOSource_Update ((uint16_t)0x0020) |
|
|
816 |
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) |
|
|
817 |
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) |
|
|
818 |
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) |
|
|
819 |
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) |
|
|
820 |
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) |
|
|
821 |
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ |
|
|
822 |
((SOURCE) == TIM_TRGOSource_Enable) || \ |
|
|
823 |
((SOURCE) == TIM_TRGOSource_Update) || \ |
|
|
824 |
((SOURCE) == TIM_TRGOSource_OC1) || \ |
|
|
825 |
((SOURCE) == TIM_TRGOSource_OC1Ref) || \ |
|
|
826 |
((SOURCE) == TIM_TRGOSource_OC2Ref) || \ |
|
|
827 |
((SOURCE) == TIM_TRGOSource_OC3Ref) || \ |
|
|
828 |
((SOURCE) == TIM_TRGOSource_OC4Ref)) |
|
|
829 |
/** |
|
|
830 |
* @} |
|
|
831 |
*/ |
|
|
832 |
|
|
|
833 |
/** @defgroup TIM_Slave_Mode |
|
|
834 |
* @{ |
|
|
835 |
*/ |
|
|
836 |
|
|
|
837 |
#define TIM_SlaveMode_Reset ((uint16_t)0x0004) |
|
|
838 |
#define TIM_SlaveMode_Gated ((uint16_t)0x0005) |
|
|
839 |
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) |
|
|
840 |
#define TIM_SlaveMode_External1 ((uint16_t)0x0007) |
|
|
841 |
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ |
|
|
842 |
((MODE) == TIM_SlaveMode_Gated) || \ |
|
|
843 |
((MODE) == TIM_SlaveMode_Trigger) || \ |
|
|
844 |
((MODE) == TIM_SlaveMode_External1)) |
|
|
845 |
/** |
|
|
846 |
* @} |
|
|
847 |
*/ |
|
|
848 |
|
|
|
849 |
/** @defgroup TIM_Master_Slave_Mode |
|
|
850 |
* @{ |
|
|
851 |
*/ |
|
|
852 |
|
|
|
853 |
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) |
|
|
854 |
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) |
|
|
855 |
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ |
|
|
856 |
((STATE) == TIM_MasterSlaveMode_Disable)) |
|
|
857 |
/** |
|
|
858 |
* @} |
|
|
859 |
*/ |
|
|
860 |
|
|
|
861 |
/** @defgroup TIM_Flags |
|
|
862 |
* @{ |
|
|
863 |
*/ |
|
|
864 |
|
|
|
865 |
#define TIM_FLAG_Update ((uint16_t)0x0001) |
|
|
866 |
#define TIM_FLAG_CC1 ((uint16_t)0x0002) |
|
|
867 |
#define TIM_FLAG_CC2 ((uint16_t)0x0004) |
|
|
868 |
#define TIM_FLAG_CC3 ((uint16_t)0x0008) |
|
|
869 |
#define TIM_FLAG_CC4 ((uint16_t)0x0010) |
|
|
870 |
#define TIM_FLAG_COM ((uint16_t)0x0020) |
|
|
871 |
#define TIM_FLAG_Trigger ((uint16_t)0x0040) |
|
|
872 |
#define TIM_FLAG_Break ((uint16_t)0x0080) |
|
|
873 |
#define TIM_FLAG_CC1OF ((uint16_t)0x0200) |
|
|
874 |
#define TIM_FLAG_CC2OF ((uint16_t)0x0400) |
|
|
875 |
#define TIM_FLAG_CC3OF ((uint16_t)0x0800) |
|
|
876 |
#define TIM_FLAG_CC4OF ((uint16_t)0x1000) |
|
|
877 |
#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ |
|
|
878 |
((FLAG) == TIM_FLAG_CC1) || \ |
|
|
879 |
((FLAG) == TIM_FLAG_CC2) || \ |
|
|
880 |
((FLAG) == TIM_FLAG_CC3) || \ |
|
|
881 |
((FLAG) == TIM_FLAG_CC4) || \ |
|
|
882 |
((FLAG) == TIM_FLAG_COM) || \ |
|
|
883 |
((FLAG) == TIM_FLAG_Trigger) || \ |
|
|
884 |
((FLAG) == TIM_FLAG_Break) || \ |
|
|
885 |
((FLAG) == TIM_FLAG_CC1OF) || \ |
|
|
886 |
((FLAG) == TIM_FLAG_CC2OF) || \ |
|
|
887 |
((FLAG) == TIM_FLAG_CC3OF) || \ |
|
|
888 |
((FLAG) == TIM_FLAG_CC4OF)) |
|
|
889 |
|
|
|
890 |
|
|
|
891 |
#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) |
|
|
892 |
/** |
|
|
893 |
* @} |
|
|
894 |
*/ |
|
|
895 |
|
|
|
896 |
/** @defgroup TIM_Input_Capture_Filer_Value |
|
|
897 |
* @{ |
|
|
898 |
*/ |
|
|
899 |
|
|
|
900 |
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
|
|
901 |
/** |
|
|
902 |
* @} |
|
|
903 |
*/ |
|
|
904 |
|
|
|
905 |
/** @defgroup TIM_External_Trigger_Filter |
|
|
906 |
* @{ |
|
|
907 |
*/ |
|
|
908 |
|
|
|
909 |
#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) |
|
|
910 |
/** |
|
|
911 |
* @} |
|
|
912 |
*/ |
|
|
913 |
|
|
|
914 |
/** |
|
|
915 |
* @} |
|
|
916 |
*/ |
|
|
917 |
|
|
|
918 |
/** @defgroup TIM_Exported_Macros |
|
|
919 |
* @{ |
|
|
920 |
*/ |
|
|
921 |
|
|
|
922 |
/** |
|
|
923 |
* @} |
|
|
924 |
*/ |
|
|
925 |
|
|
|
926 |
/** @defgroup TIM_Exported_Functions |
|
|
927 |
* @{ |
|
|
928 |
*/ |
|
|
929 |
|
|
|
930 |
void TIM_DeInit(TIM_TypeDef* TIMx); |
|
|
931 |
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); |
|
|
932 |
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
|
|
933 |
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
|
|
934 |
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
|
|
935 |
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); |
|
|
936 |
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); |
|
|
937 |
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); |
|
|
938 |
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); |
|
|
939 |
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); |
|
|
940 |
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); |
|
|
941 |
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); |
|
|
942 |
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); |
|
|
943 |
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); |
|
|
944 |
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); |
|
|
945 |
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); |
|
|
946 |
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); |
|
|
947 |
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); |
|
|
948 |
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); |
|
|
949 |
void TIM_InternalClockConfig(TIM_TypeDef* TIMx); |
|
|
950 |
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); |
|
|
951 |
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, |
|
|
952 |
uint16_t TIM_ICPolarity, uint16_t ICFilter); |
|
|
953 |
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
|
|
954 |
uint16_t ExtTRGFilter); |
|
|
955 |
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, |
|
|
956 |
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); |
|
|
957 |
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
|
|
958 |
uint16_t ExtTRGFilter); |
|
|
959 |
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); |
|
|
960 |
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); |
|
|
961 |
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); |
|
|
962 |
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, |
|
|
963 |
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); |
|
|
964 |
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
|
|
965 |
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
|
|
966 |
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
|
|
967 |
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); |
|
|
968 |
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); |
|
|
969 |
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); |
|
|
970 |
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); |
|
|
971 |
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); |
|
|
972 |
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
|
|
973 |
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
|
|
974 |
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
|
|
975 |
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); |
|
|
976 |
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
|
|
977 |
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
|
|
978 |
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
|
|
979 |
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); |
|
|
980 |
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
|
|
981 |
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
|
|
982 |
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
|
|
983 |
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); |
|
|
984 |
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
|
|
985 |
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
|
|
986 |
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
|
|
987 |
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
|
|
988 |
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
|
|
989 |
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); |
|
|
990 |
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); |
|
|
991 |
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); |
|
|
992 |
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); |
|
|
993 |
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); |
|
|
994 |
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); |
|
|
995 |
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); |
|
|
996 |
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); |
|
|
997 |
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); |
|
|
998 |
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); |
|
|
999 |
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); |
|
|
1000 |
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); |
|
|
1001 |
void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); |
|
|
1002 |
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); |
|
|
1003 |
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); |
|
|
1004 |
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); |
|
|
1005 |
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); |
|
|
1006 |
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); |
|
|
1007 |
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
|
|
1008 |
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
|
|
1009 |
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
|
|
1010 |
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); |
|
|
1011 |
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); |
|
|
1012 |
uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); |
|
|
1013 |
uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); |
|
|
1014 |
uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); |
|
|
1015 |
uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); |
|
|
1016 |
uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); |
|
|
1017 |
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); |
|
|
1018 |
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); |
|
|
1019 |
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); |
|
|
1020 |
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); |
|
|
1021 |
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); |
|
|
1022 |
|
|
|
1023 |
#ifdef __cplusplus |
|
|
1024 |
} |
|
|
1025 |
#endif |
|
|
1026 |
|
|
|
1027 |
#endif /*__STM32F10x_TIM_H */ |
|
|
1028 |
/** |
|
|
1029 |
* @} |
|
|
1030 |
*/ |
|
|
1031 |
|
|
|
1032 |
/** |
|
|
1033 |
* @} |
|
|
1034 |
*/ |
|
|
1035 |
|
|
|
1036 |
/** |
|
|
1037 |
* @} |
|
|
1038 |
*/ |
|
|
1039 |
|
|
|
1040 |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ |