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povik |
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/** |
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****************************************************************************** |
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* @file stm32f10x_can.c |
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* @author MCD Application Team |
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* @version V3.1.0 |
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* @date 06/19/2009 |
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* @brief This file provides all the CAN firmware functions. |
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****************************************************************************** |
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* @copy |
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* |
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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* |
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> |
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*/ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f10x_can.h" |
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#include "stm32f10x_rcc.h" |
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/** @addtogroup STM32F10x_StdPeriph_Driver |
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* @{ |
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*/ |
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/** @defgroup CAN |
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* @brief CAN driver modules |
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* @{ |
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*/ |
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/** @defgroup CAN_Private_TypesDefinitions |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup CAN_Private_Defines |
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* @{ |
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*/ |
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/* CAN Master Control Register bits */ |
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#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */ |
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#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */ |
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#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */ |
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#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */ |
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#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */ |
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#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */ |
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#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */ |
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#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */ |
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#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */ |
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#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ |
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/* CAN Master Status Register bits */ |
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#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */ |
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#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */ |
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#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */ |
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/* CAN Transmit Status Register bits */ |
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#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */ |
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#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */ |
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#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */ |
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#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */ |
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#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */ |
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#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */ |
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#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */ |
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#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */ |
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#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */ |
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#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */ |
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#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */ |
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#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */ |
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/* CAN Receive FIFO 0 Register bits */ |
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#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */ |
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#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */ |
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#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */ |
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/* CAN Receive FIFO 1 Register bits */ |
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#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */ |
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#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */ |
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#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */ |
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/* CAN Error Status Register bits */ |
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#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */ |
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#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */ |
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#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */ |
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/* CAN Mailbox Transmit Request */ |
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#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ |
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/* CAN Filter Master Register bits */ |
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#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ |
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/* Time out for INAK bit */ |
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#define INAK_TimeOut ((uint32_t)0x0000FFFF) |
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/* Time out for SLAK bit */ |
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#define SLAK_TimeOut ((uint32_t)0x0000FFFF) |
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/** |
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* @} |
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*/ |
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/** @defgroup CAN_Private_Macros |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup CAN_Private_Variables |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup CAN_Private_FunctionPrototypes |
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* @{ |
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*/ |
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static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); |
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/** |
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* @} |
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*/ |
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/** @defgroup CAN_Private_Functions |
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* @{ |
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*/ |
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/** |
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* @brief Deinitializes the CAN peripheral registers to their default reset values. |
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* @param CANx: where x can be 1 or 2 to select the CAN peripheral. |
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* @retval None. |
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*/ |
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void CAN_DeInit(CAN_TypeDef* CANx) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_CAN_ALL_PERIPH(CANx)); |
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if (CANx == CAN1) |
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{ |
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/* Enable CAN1 reset state */ |
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); |
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/* Release CAN1 from reset state */ |
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); |
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} |
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else |
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{ |
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/* Enable CAN2 reset state */ |
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); |
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/* Release CAN2 from reset state */ |
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); |
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} |
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} |
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/** |
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* @brief Initializes the CAN peripheral according to the specified |
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* parameters in the CAN_InitStruct. |
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* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
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* @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that |
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* contains the configuration information for the CAN peripheral. |
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* @retval Constant indicates initialization succeed which will be |
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* CANINITFAILED or CANINITOK. |
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*/ |
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uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) |
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{ |
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uint8_t InitStatus = CANINITFAILED; |
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uint32_t wait_ack = 0x00000000; |
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/* Check the parameters */ |
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assert_param(IS_CAN_ALL_PERIPH(CANx)); |
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assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); |
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assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); |
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assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); |
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assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); |
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assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); |
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assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); |
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assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); |
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assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); |
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assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); |
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assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); |
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assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); |
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/* exit from sleep mode */ |
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CANx->MCR &= ~MCR_SLEEP; |
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/* Request initialisation */ |
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CANx->MCR |= MCR_INRQ ; |
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/* Wait the acknowledge */ |
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while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut)) |
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{ |
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wait_ack++; |
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} |
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/* ...and check acknowledged */ |
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if ((CANx->MSR & MSR_INAK) != MSR_INAK) |
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{ |
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InitStatus = CANINITFAILED; |
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} |
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else |
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{ |
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/* Set the time triggered communication mode */ |
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if (CAN_InitStruct->CAN_TTCM == ENABLE) |
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{ |
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CANx->MCR |= MCR_TTCM; |
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} |
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else |
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{ |
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CANx->MCR &= ~MCR_TTCM; |
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} |
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/* Set the automatic bus-off management */ |
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if (CAN_InitStruct->CAN_ABOM == ENABLE) |
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{ |
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CANx->MCR |= MCR_ABOM; |
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} |
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else |
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{ |
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CANx->MCR &= ~MCR_ABOM; |
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} |
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/* Set the automatic wake-up mode */ |
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if (CAN_InitStruct->CAN_AWUM == ENABLE) |
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{ |
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CANx->MCR |= MCR_AWUM; |
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} |
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else |
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{ |
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CANx->MCR &= ~MCR_AWUM; |
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} |
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/* Set the no automatic retransmission */ |
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if (CAN_InitStruct->CAN_NART == ENABLE) |
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{ |
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CANx->MCR |= MCR_NART; |
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} |
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else |
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{ |
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CANx->MCR &= ~MCR_NART; |
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} |
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/* Set the receive FIFO locked mode */ |
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if (CAN_InitStruct->CAN_RFLM == ENABLE) |
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{ |
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CANx->MCR |= MCR_RFLM; |
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} |
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else |
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{ |
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CANx->MCR &= ~MCR_RFLM; |
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} |
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/* Set the transmit FIFO priority */ |
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if (CAN_InitStruct->CAN_TXFP == ENABLE) |
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{ |
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CANx->MCR |= MCR_TXFP; |
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} |
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else |
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{ |
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CANx->MCR &= ~MCR_TXFP; |
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} |
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/* Set the bit timing register */ |
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CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | |
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((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | |
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((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); |
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/* Request leave initialisation */ |
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CANx->MCR &= ~MCR_INRQ; |
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/* Wait the acknowledge */ |
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wait_ack = 0x00; |
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while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut)) |
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{ |
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wait_ack++; |
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} |
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/* ...and check acknowledged */ |
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if ((CANx->MSR & MSR_INAK) == MSR_INAK) |
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{ |
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InitStatus = CANINITFAILED; |
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} |
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else |
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{ |
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InitStatus = CANINITOK ; |
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} |
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} |
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/* At this step, return the status of initialization */ |
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return InitStatus; |
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} |
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/** |
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* @brief Initializes the CAN peripheral according to the specified |
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* parameters in the CAN_FilterInitStruct. |
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* @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef |
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* structure that contains the configuration information. |
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* @retval None. |
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*/ |
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void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) |
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{ |
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uint32_t filter_number_bit_pos = 0; |
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/* Check the parameters */ |
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assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); |
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assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); |
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assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); |
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assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); |
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assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); |
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filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; |
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/* Initialisation mode for the filter */ |
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CAN1->FMR |= FMR_FINIT; |
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/* Filter Deactivation */ |
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CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; |
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/* Filter Scale */ |
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if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) |
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{ |
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/* 16-bit scale for the filter */ |
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CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; |
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/* First 16-bit identifier and First 16-bit mask */ |
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/* Or First 16-bit identifier and Second 16-bit identifier */ |
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CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = |
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((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | |
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(0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); |
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/* Second 16-bit identifier and Second 16-bit mask */ |
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/* Or Third 16-bit identifier and Fourth 16-bit identifier */ |
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CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = |
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((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | |
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(0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); |
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} |
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if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) |
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{ |
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/* 32-bit scale for the filter */ |
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CAN1->FS1R |= filter_number_bit_pos; |
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/* 32-bit identifier or First 32-bit identifier */ |
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CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = |
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((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | |
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(0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); |
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/* 32-bit mask or Second 32-bit identifier */ |
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CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = |
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((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | |
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(0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); |
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} |
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358 |
|
|
|
359 |
/* Filter Mode */ |
|
|
360 |
if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) |
|
|
361 |
{ |
|
|
362 |
/*Id/Mask mode for the filter*/ |
|
|
363 |
CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; |
|
|
364 |
} |
|
|
365 |
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ |
|
|
366 |
{ |
|
|
367 |
/*Identifier list mode for the filter*/ |
|
|
368 |
CAN1->FM1R |= (uint32_t)filter_number_bit_pos; |
|
|
369 |
} |
|
|
370 |
|
|
|
371 |
/* Filter FIFO assignment */ |
|
|
372 |
if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) |
|
|
373 |
{ |
|
|
374 |
/* FIFO 0 assignation for the filter */ |
|
|
375 |
CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; |
|
|
376 |
} |
|
|
377 |
|
|
|
378 |
if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) |
|
|
379 |
{ |
|
|
380 |
/* FIFO 1 assignation for the filter */ |
|
|
381 |
CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; |
|
|
382 |
} |
|
|
383 |
|
|
|
384 |
/* Filter activation */ |
|
|
385 |
if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) |
|
|
386 |
{ |
|
|
387 |
CAN1->FA1R |= filter_number_bit_pos; |
|
|
388 |
} |
|
|
389 |
|
|
|
390 |
/* Leave the initialisation mode for the filter */ |
|
|
391 |
CAN1->FMR &= ~FMR_FINIT; |
|
|
392 |
} |
|
|
393 |
|
|
|
394 |
/** |
|
|
395 |
* @brief Fills each CAN_InitStruct member with its default value. |
|
|
396 |
* @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which |
|
|
397 |
* will be initialized. |
|
|
398 |
* @retval None. |
|
|
399 |
*/ |
|
|
400 |
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) |
|
|
401 |
{ |
|
|
402 |
/* Reset CAN init structure parameters values */ |
|
|
403 |
/* Initialize the time triggered communication mode */ |
|
|
404 |
CAN_InitStruct->CAN_TTCM = DISABLE; |
|
|
405 |
/* Initialize the automatic bus-off management */ |
|
|
406 |
CAN_InitStruct->CAN_ABOM = DISABLE; |
|
|
407 |
/* Initialize the automatic wake-up mode */ |
|
|
408 |
CAN_InitStruct->CAN_AWUM = DISABLE; |
|
|
409 |
/* Initialize the no automatic retransmission */ |
|
|
410 |
CAN_InitStruct->CAN_NART = DISABLE; |
|
|
411 |
/* Initialize the receive FIFO locked mode */ |
|
|
412 |
CAN_InitStruct->CAN_RFLM = DISABLE; |
|
|
413 |
/* Initialize the transmit FIFO priority */ |
|
|
414 |
CAN_InitStruct->CAN_TXFP = DISABLE; |
|
|
415 |
/* Initialize the CAN_Mode member */ |
|
|
416 |
CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; |
|
|
417 |
/* Initialize the CAN_SJW member */ |
|
|
418 |
CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; |
|
|
419 |
/* Initialize the CAN_BS1 member */ |
|
|
420 |
CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; |
|
|
421 |
/* Initialize the CAN_BS2 member */ |
|
|
422 |
CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; |
|
|
423 |
/* Initialize the CAN_Prescaler member */ |
|
|
424 |
CAN_InitStruct->CAN_Prescaler = 1; |
|
|
425 |
} |
|
|
426 |
|
|
|
427 |
/** |
|
|
428 |
* @brief Select the start bank filter for slave CAN. |
|
|
429 |
* @note This function applies only to STM32 Connectivity line devices. |
|
|
430 |
* @param CAN_BankNumber: Select the start slave bank filter from 1..27. |
|
|
431 |
* @retval None. |
|
|
432 |
*/ |
|
|
433 |
void CAN_SlaveStartBank(uint8_t CAN_BankNumber) |
|
|
434 |
{ |
|
|
435 |
/* Check the parameters */ |
|
|
436 |
assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); |
|
|
437 |
/* enter Initialisation mode for the filter */ |
|
|
438 |
CAN1->FMR |= FMR_FINIT; |
|
|
439 |
/* Select the start slave bank */ |
|
|
440 |
CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; |
|
|
441 |
CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; |
|
|
442 |
/* Leave Initialisation mode for the filter */ |
|
|
443 |
CAN1->FMR &= ~FMR_FINIT; |
|
|
444 |
} |
|
|
445 |
|
|
|
446 |
/** |
|
|
447 |
* @brief Enables or disables the specified CAN interrupts. |
|
|
448 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
449 |
* @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. |
|
|
450 |
* This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0, |
|
|
451 |
* CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1, |
|
|
452 |
* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, |
|
|
453 |
* CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or |
|
|
454 |
* CAN_IT_SLK. |
|
|
455 |
* @param NewState: new state of the CAN interrupts. |
|
|
456 |
* This parameter can be: ENABLE or DISABLE. |
|
|
457 |
* @retval None. |
|
|
458 |
*/ |
|
|
459 |
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) |
|
|
460 |
{ |
|
|
461 |
/* Check the parameters */ |
|
|
462 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
463 |
assert_param(IS_CAN_ITConfig(CAN_IT)); |
|
|
464 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
465 |
|
|
|
466 |
if (NewState != DISABLE) |
|
|
467 |
{ |
|
|
468 |
/* Enable the selected CAN interrupt */ |
|
|
469 |
CANx->IER |= CAN_IT; |
|
|
470 |
} |
|
|
471 |
else |
|
|
472 |
{ |
|
|
473 |
/* Disable the selected CAN interrupt */ |
|
|
474 |
CANx->IER &= ~CAN_IT; |
|
|
475 |
} |
|
|
476 |
} |
|
|
477 |
|
|
|
478 |
/** |
|
|
479 |
* @brief Initiates the transmission of a message. |
|
|
480 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
481 |
* @param TxMessage: pointer to a structure which contains CAN Id, CAN |
|
|
482 |
* DLC and CAN datas. |
|
|
483 |
* @retval The number of the mailbox that is used for transmission |
|
|
484 |
* or CAN_NO_MB if there is no empty mailbox. |
|
|
485 |
*/ |
|
|
486 |
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) |
|
|
487 |
{ |
|
|
488 |
uint8_t transmit_mailbox = 0; |
|
|
489 |
/* Check the parameters */ |
|
|
490 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
491 |
assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); |
|
|
492 |
assert_param(IS_CAN_RTR(TxMessage->RTR)); |
|
|
493 |
assert_param(IS_CAN_DLC(TxMessage->DLC)); |
|
|
494 |
|
|
|
495 |
/* Select one empty transmit mailbox */ |
|
|
496 |
if ((CANx->TSR&TSR_TME0) == TSR_TME0) |
|
|
497 |
{ |
|
|
498 |
transmit_mailbox = 0; |
|
|
499 |
} |
|
|
500 |
else if ((CANx->TSR&TSR_TME1) == TSR_TME1) |
|
|
501 |
{ |
|
|
502 |
transmit_mailbox = 1; |
|
|
503 |
} |
|
|
504 |
else if ((CANx->TSR&TSR_TME2) == TSR_TME2) |
|
|
505 |
{ |
|
|
506 |
transmit_mailbox = 2; |
|
|
507 |
} |
|
|
508 |
else |
|
|
509 |
{ |
|
|
510 |
transmit_mailbox = CAN_NO_MB; |
|
|
511 |
} |
|
|
512 |
|
|
|
513 |
if (transmit_mailbox != CAN_NO_MB) |
|
|
514 |
{ |
|
|
515 |
/* Set up the Id */ |
|
|
516 |
CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; |
|
|
517 |
if (TxMessage->IDE == CAN_ID_STD) |
|
|
518 |
{ |
|
|
519 |
assert_param(IS_CAN_STDID(TxMessage->StdId)); |
|
|
520 |
CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); |
|
|
521 |
} |
|
|
522 |
else |
|
|
523 |
{ |
|
|
524 |
assert_param(IS_CAN_EXTID(TxMessage->ExtId)); |
|
|
525 |
CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | |
|
|
526 |
TxMessage->RTR); |
|
|
527 |
} |
|
|
528 |
|
|
|
529 |
|
|
|
530 |
/* Set up the DLC */ |
|
|
531 |
TxMessage->DLC &= (uint8_t)0x0000000F; |
|
|
532 |
CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; |
|
|
533 |
CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; |
|
|
534 |
|
|
|
535 |
/* Set up the data field */ |
|
|
536 |
CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | |
|
|
537 |
((uint32_t)TxMessage->Data[2] << 16) | |
|
|
538 |
((uint32_t)TxMessage->Data[1] << 8) | |
|
|
539 |
((uint32_t)TxMessage->Data[0])); |
|
|
540 |
CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | |
|
|
541 |
((uint32_t)TxMessage->Data[6] << 16) | |
|
|
542 |
((uint32_t)TxMessage->Data[5] << 8) | |
|
|
543 |
((uint32_t)TxMessage->Data[4])); |
|
|
544 |
/* Request transmission */ |
|
|
545 |
CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; |
|
|
546 |
} |
|
|
547 |
return transmit_mailbox; |
|
|
548 |
} |
|
|
549 |
|
|
|
550 |
/** |
|
|
551 |
* @brief Checks the transmission of a message. |
|
|
552 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
553 |
* @param TransmitMailbox: the number of the mailbox that is used for transmission. |
|
|
554 |
* @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case. |
|
|
555 |
*/ |
|
|
556 |
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) |
|
|
557 |
{ |
|
|
558 |
/* RQCP, TXOK and TME bits */ |
|
|
559 |
uint8_t state = 0; |
|
|
560 |
/* Check the parameters */ |
|
|
561 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
562 |
assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); |
|
|
563 |
switch (TransmitMailbox) |
|
|
564 |
{ |
|
|
565 |
case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2); |
|
|
566 |
state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0); |
|
|
567 |
state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26); |
|
|
568 |
break; |
|
|
569 |
case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6); |
|
|
570 |
state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8); |
|
|
571 |
state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27); |
|
|
572 |
break; |
|
|
573 |
case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14); |
|
|
574 |
state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16); |
|
|
575 |
state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28); |
|
|
576 |
break; |
|
|
577 |
default: |
|
|
578 |
state = CANTXFAILED; |
|
|
579 |
break; |
|
|
580 |
} |
|
|
581 |
switch (state) |
|
|
582 |
{ |
|
|
583 |
/* transmit pending */ |
|
|
584 |
case (0x0): state = CANTXPENDING; |
|
|
585 |
break; |
|
|
586 |
/* transmit failed */ |
|
|
587 |
case (0x5): state = CANTXFAILED; |
|
|
588 |
break; |
|
|
589 |
/* transmit succedeed */ |
|
|
590 |
case (0x7): state = CANTXOK; |
|
|
591 |
break; |
|
|
592 |
default: |
|
|
593 |
state = CANTXFAILED; |
|
|
594 |
break; |
|
|
595 |
} |
|
|
596 |
return state; |
|
|
597 |
} |
|
|
598 |
|
|
|
599 |
/** |
|
|
600 |
* @brief Cancels a transmit request. |
|
|
601 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
602 |
* @param Mailbox: Mailbox number. |
|
|
603 |
* @retval None. |
|
|
604 |
*/ |
|
|
605 |
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) |
|
|
606 |
{ |
|
|
607 |
/* Check the parameters */ |
|
|
608 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
609 |
assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); |
|
|
610 |
/* abort transmission */ |
|
|
611 |
switch (Mailbox) |
|
|
612 |
{ |
|
|
613 |
case (0): CANx->TSR |= TSR_ABRQ0; |
|
|
614 |
break; |
|
|
615 |
case (1): CANx->TSR |= TSR_ABRQ1; |
|
|
616 |
break; |
|
|
617 |
case (2): CANx->TSR |= TSR_ABRQ2; |
|
|
618 |
break; |
|
|
619 |
default: |
|
|
620 |
break; |
|
|
621 |
} |
|
|
622 |
} |
|
|
623 |
|
|
|
624 |
/** |
|
|
625 |
* @brief Releases a FIFO. |
|
|
626 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
627 |
* @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. |
|
|
628 |
* @retval None. |
|
|
629 |
*/ |
|
|
630 |
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) |
|
|
631 |
{ |
|
|
632 |
/* Check the parameters */ |
|
|
633 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
634 |
assert_param(IS_CAN_FIFO(FIFONumber)); |
|
|
635 |
/* Release FIFO0 */ |
|
|
636 |
if (FIFONumber == CAN_FIFO0) |
|
|
637 |
{ |
|
|
638 |
CANx->RF0R = RF0R_RFOM0; |
|
|
639 |
} |
|
|
640 |
/* Release FIFO1 */ |
|
|
641 |
else /* FIFONumber == CAN_FIFO1 */ |
|
|
642 |
{ |
|
|
643 |
CANx->RF1R = RF1R_RFOM1; |
|
|
644 |
} |
|
|
645 |
} |
|
|
646 |
|
|
|
647 |
/** |
|
|
648 |
* @brief Returns the number of pending messages. |
|
|
649 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
650 |
* @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. |
|
|
651 |
* @retval NbMessage which is the number of pending message. |
|
|
652 |
*/ |
|
|
653 |
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) |
|
|
654 |
{ |
|
|
655 |
uint8_t message_pending=0; |
|
|
656 |
/* Check the parameters */ |
|
|
657 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
658 |
assert_param(IS_CAN_FIFO(FIFONumber)); |
|
|
659 |
if (FIFONumber == CAN_FIFO0) |
|
|
660 |
{ |
|
|
661 |
message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); |
|
|
662 |
} |
|
|
663 |
else if (FIFONumber == CAN_FIFO1) |
|
|
664 |
{ |
|
|
665 |
message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); |
|
|
666 |
} |
|
|
667 |
else |
|
|
668 |
{ |
|
|
669 |
message_pending = 0; |
|
|
670 |
} |
|
|
671 |
return message_pending; |
|
|
672 |
} |
|
|
673 |
|
|
|
674 |
/** |
|
|
675 |
* @brief Receives a message. |
|
|
676 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
677 |
* @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. |
|
|
678 |
* @param RxMessage: pointer to a structure receive message which |
|
|
679 |
* contains CAN Id, CAN DLC, CAN datas and FMI number. |
|
|
680 |
* @retval None. |
|
|
681 |
*/ |
|
|
682 |
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) |
|
|
683 |
{ |
|
|
684 |
/* Check the parameters */ |
|
|
685 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
686 |
assert_param(IS_CAN_FIFO(FIFONumber)); |
|
|
687 |
/* Get the Id */ |
|
|
688 |
RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; |
|
|
689 |
if (RxMessage->IDE == CAN_ID_STD) |
|
|
690 |
{ |
|
|
691 |
RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); |
|
|
692 |
} |
|
|
693 |
else |
|
|
694 |
{ |
|
|
695 |
RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); |
|
|
696 |
} |
|
|
697 |
|
|
|
698 |
RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; |
|
|
699 |
/* Get the DLC */ |
|
|
700 |
RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; |
|
|
701 |
/* Get the FMI */ |
|
|
702 |
RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); |
|
|
703 |
/* Get the data field */ |
|
|
704 |
RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; |
|
|
705 |
RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); |
|
|
706 |
RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); |
|
|
707 |
RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); |
|
|
708 |
RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; |
|
|
709 |
RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); |
|
|
710 |
RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); |
|
|
711 |
RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); |
|
|
712 |
/* Release the FIFO */ |
|
|
713 |
CAN_FIFORelease(CANx, FIFONumber); |
|
|
714 |
} |
|
|
715 |
|
|
|
716 |
/** |
|
|
717 |
* @brief Enables or disables the DBG Freeze for CAN. |
|
|
718 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
719 |
* @param NewState: new state of the CAN peripheral. |
|
|
720 |
* This parameter can be: ENABLE or DISABLE. |
|
|
721 |
* @retval None. |
|
|
722 |
*/ |
|
|
723 |
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) |
|
|
724 |
{ |
|
|
725 |
/* Check the parameters */ |
|
|
726 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
727 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
728 |
|
|
|
729 |
if (NewState != DISABLE) |
|
|
730 |
{ |
|
|
731 |
/* Enable Debug Freeze */ |
|
|
732 |
CANx->MCR |= MCR_DBF; |
|
|
733 |
} |
|
|
734 |
else |
|
|
735 |
{ |
|
|
736 |
/* Disable Debug Freeze */ |
|
|
737 |
CANx->MCR &= ~MCR_DBF; |
|
|
738 |
} |
|
|
739 |
} |
|
|
740 |
|
|
|
741 |
/** |
|
|
742 |
* @brief Enters the low power mode. |
|
|
743 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
744 |
* @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. |
|
|
745 |
*/ |
|
|
746 |
uint8_t CAN_Sleep(CAN_TypeDef* CANx) |
|
|
747 |
{ |
|
|
748 |
uint8_t sleepstatus = CANSLEEPFAILED; |
|
|
749 |
|
|
|
750 |
/* Check the parameters */ |
|
|
751 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
752 |
|
|
|
753 |
/* Request Sleep mode */ |
|
|
754 |
CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP); |
|
|
755 |
|
|
|
756 |
/* Sleep mode status */ |
|
|
757 |
if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) |
|
|
758 |
{ |
|
|
759 |
/* Sleep mode not entered */ |
|
|
760 |
sleepstatus = CANSLEEPOK; |
|
|
761 |
} |
|
|
762 |
/* At this step, sleep mode status */ |
|
|
763 |
return (uint8_t)sleepstatus; |
|
|
764 |
} |
|
|
765 |
|
|
|
766 |
/** |
|
|
767 |
* @brief Wakes the CAN up. |
|
|
768 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
769 |
* @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. |
|
|
770 |
*/ |
|
|
771 |
uint8_t CAN_WakeUp(CAN_TypeDef* CANx) |
|
|
772 |
{ |
|
|
773 |
uint32_t wait_slak = SLAK_TimeOut ; |
|
|
774 |
uint8_t wakeupstatus = CANWAKEUPFAILED; |
|
|
775 |
|
|
|
776 |
/* Check the parameters */ |
|
|
777 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
778 |
|
|
|
779 |
/* Wake up request */ |
|
|
780 |
CANx->MCR &= ~MCR_SLEEP; |
|
|
781 |
|
|
|
782 |
/* Sleep mode status */ |
|
|
783 |
while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) |
|
|
784 |
{ |
|
|
785 |
wait_slak--; |
|
|
786 |
} |
|
|
787 |
if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) |
|
|
788 |
{ |
|
|
789 |
/* Sleep mode exited */ |
|
|
790 |
wakeupstatus = CANWAKEUPOK; |
|
|
791 |
} |
|
|
792 |
/* At this step, sleep mode status */ |
|
|
793 |
return (uint8_t)wakeupstatus; |
|
|
794 |
} |
|
|
795 |
|
|
|
796 |
/** |
|
|
797 |
* @brief Checks whether the specified CAN flag is set or not. |
|
|
798 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
799 |
* @param CAN_FLAG: specifies the flag to check. |
|
|
800 |
* This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF. |
|
|
801 |
* @retval The new state of CAN_FLAG (SET or RESET). |
|
|
802 |
*/ |
|
|
803 |
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) |
|
|
804 |
{ |
|
|
805 |
FlagStatus bitstatus = RESET; |
|
|
806 |
/* Check the parameters */ |
|
|
807 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
808 |
assert_param(IS_CAN_FLAG(CAN_FLAG)); |
|
|
809 |
/* Check the status of the specified CAN flag */ |
|
|
810 |
if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET) |
|
|
811 |
{ |
|
|
812 |
/* CAN_FLAG is set */ |
|
|
813 |
bitstatus = SET; |
|
|
814 |
} |
|
|
815 |
else |
|
|
816 |
{ |
|
|
817 |
/* CAN_FLAG is reset */ |
|
|
818 |
bitstatus = RESET; |
|
|
819 |
} |
|
|
820 |
/* Return the CAN_FLAG status */ |
|
|
821 |
return bitstatus; |
|
|
822 |
} |
|
|
823 |
|
|
|
824 |
/** |
|
|
825 |
* @brief Clears the CAN's pending flags. |
|
|
826 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
827 |
* @param CAN_FLAG: specifies the flag to clear. |
|
|
828 |
* @retval None. |
|
|
829 |
*/ |
|
|
830 |
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) |
|
|
831 |
{ |
|
|
832 |
/* Check the parameters */ |
|
|
833 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
834 |
assert_param(IS_CAN_FLAG(CAN_FLAG)); |
|
|
835 |
/* Clear the selected CAN flags */ |
|
|
836 |
CANx->ESR &= ~CAN_FLAG; |
|
|
837 |
} |
|
|
838 |
|
|
|
839 |
/** |
|
|
840 |
* @brief Checks whether the specified CAN interrupt has occurred or not. |
|
|
841 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
842 |
* @param CAN_IT: specifies the CAN interrupt source to check. |
|
|
843 |
* This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2, |
|
|
844 |
* CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1, |
|
|
845 |
* CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, |
|
|
846 |
* CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK. |
|
|
847 |
* @retval The new state of CAN_IT (SET or RESET). |
|
|
848 |
*/ |
|
|
849 |
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) |
|
|
850 |
{ |
|
|
851 |
ITStatus pendingbitstatus = RESET; |
|
|
852 |
/* Check the parameters */ |
|
|
853 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
854 |
assert_param(IS_CAN_ITStatus(CAN_IT)); |
|
|
855 |
switch (CAN_IT) |
|
|
856 |
{ |
|
|
857 |
case CAN_IT_RQCP0: |
|
|
858 |
pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0); |
|
|
859 |
break; |
|
|
860 |
case CAN_IT_RQCP1: |
|
|
861 |
pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1); |
|
|
862 |
break; |
|
|
863 |
case CAN_IT_RQCP2: |
|
|
864 |
pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2); |
|
|
865 |
break; |
|
|
866 |
case CAN_IT_FF0: |
|
|
867 |
pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0); |
|
|
868 |
break; |
|
|
869 |
case CAN_IT_FOV0: |
|
|
870 |
pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0); |
|
|
871 |
break; |
|
|
872 |
case CAN_IT_FF1: |
|
|
873 |
pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1); |
|
|
874 |
break; |
|
|
875 |
case CAN_IT_FOV1: |
|
|
876 |
pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1); |
|
|
877 |
break; |
|
|
878 |
case CAN_IT_EWG: |
|
|
879 |
pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF); |
|
|
880 |
break; |
|
|
881 |
case CAN_IT_EPV: |
|
|
882 |
pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF); |
|
|
883 |
break; |
|
|
884 |
case CAN_IT_BOF: |
|
|
885 |
pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF); |
|
|
886 |
break; |
|
|
887 |
case CAN_IT_SLK: |
|
|
888 |
pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI); |
|
|
889 |
break; |
|
|
890 |
case CAN_IT_WKU: |
|
|
891 |
pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI); |
|
|
892 |
break; |
|
|
893 |
default : |
|
|
894 |
pendingbitstatus = RESET; |
|
|
895 |
break; |
|
|
896 |
} |
|
|
897 |
/* Return the CAN_IT status */ |
|
|
898 |
return pendingbitstatus; |
|
|
899 |
} |
|
|
900 |
|
|
|
901 |
/** |
|
|
902 |
* @brief Clears the CANs interrupt pending bits. |
|
|
903 |
* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. |
|
|
904 |
* @param CAN_IT: specifies the interrupt pending bit to clear. |
|
|
905 |
* @retval None. |
|
|
906 |
*/ |
|
|
907 |
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) |
|
|
908 |
{ |
|
|
909 |
/* Check the parameters */ |
|
|
910 |
assert_param(IS_CAN_ALL_PERIPH(CANx)); |
|
|
911 |
assert_param(IS_CAN_ITStatus(CAN_IT)); |
|
|
912 |
switch (CAN_IT) |
|
|
913 |
{ |
|
|
914 |
case CAN_IT_RQCP0: |
|
|
915 |
CANx->TSR = TSR_RQCP0; /* rc_w1*/ |
|
|
916 |
break; |
|
|
917 |
case CAN_IT_RQCP1: |
|
|
918 |
CANx->TSR = TSR_RQCP1; /* rc_w1*/ |
|
|
919 |
break; |
|
|
920 |
case CAN_IT_RQCP2: |
|
|
921 |
CANx->TSR = TSR_RQCP2; /* rc_w1*/ |
|
|
922 |
break; |
|
|
923 |
case CAN_IT_FF0: |
|
|
924 |
CANx->RF0R = RF0R_FULL0; /* rc_w1*/ |
|
|
925 |
break; |
|
|
926 |
case CAN_IT_FOV0: |
|
|
927 |
CANx->RF0R = RF0R_FOVR0; /* rc_w1*/ |
|
|
928 |
break; |
|
|
929 |
case CAN_IT_FF1: |
|
|
930 |
CANx->RF1R = RF1R_FULL1; /* rc_w1*/ |
|
|
931 |
break; |
|
|
932 |
case CAN_IT_FOV1: |
|
|
933 |
CANx->RF1R = RF1R_FOVR1; /* rc_w1*/ |
|
|
934 |
break; |
|
|
935 |
case CAN_IT_EWG: |
|
|
936 |
CANx->ESR &= ~ ESR_EWGF; /* rw */ |
|
|
937 |
break; |
|
|
938 |
case CAN_IT_EPV: |
|
|
939 |
CANx->ESR &= ~ ESR_EPVF; /* rw */ |
|
|
940 |
break; |
|
|
941 |
case CAN_IT_BOF: |
|
|
942 |
CANx->ESR &= ~ ESR_BOFF; /* rw */ |
|
|
943 |
break; |
|
|
944 |
case CAN_IT_WKU: |
|
|
945 |
CANx->MSR = MSR_WKUI; /* rc_w1*/ |
|
|
946 |
break; |
|
|
947 |
case CAN_IT_SLK: |
|
|
948 |
CANx->MSR = MSR_SLAKI; /* rc_w1*/ |
|
|
949 |
break; |
|
|
950 |
default : |
|
|
951 |
break; |
|
|
952 |
} |
|
|
953 |
} |
|
|
954 |
|
|
|
955 |
/** |
|
|
956 |
* @brief Checks whether the CAN interrupt has occurred or not. |
|
|
957 |
* @param CAN_Reg: specifies the CAN interrupt register to check. |
|
|
958 |
* @param It_Bit: specifies the interrupt source bit to check. |
|
|
959 |
* @retval The new state of the CAN Interrupt (SET or RESET). |
|
|
960 |
*/ |
|
|
961 |
static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) |
|
|
962 |
{ |
|
|
963 |
ITStatus pendingbitstatus = RESET; |
|
|
964 |
|
|
|
965 |
if ((CAN_Reg & It_Bit) != (uint32_t)RESET) |
|
|
966 |
{ |
|
|
967 |
/* CAN_IT is set */ |
|
|
968 |
pendingbitstatus = SET; |
|
|
969 |
} |
|
|
970 |
else |
|
|
971 |
{ |
|
|
972 |
/* CAN_IT is reset */ |
|
|
973 |
pendingbitstatus = RESET; |
|
|
974 |
} |
|
|
975 |
return pendingbitstatus; |
|
|
976 |
} |
|
|
977 |
|
|
|
978 |
/** |
|
|
979 |
* @} |
|
|
980 |
*/ |
|
|
981 |
|
|
|
982 |
/** |
|
|
983 |
* @} |
|
|
984 |
*/ |
|
|
985 |
|
|
|
986 |
/** |
|
|
987 |
* @} |
|
|
988 |
*/ |
|
|
989 |
|
|
|
990 |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ |