Rev Author Line No. Line
3328 povik 1 /**
2 ******************************************************************************
3 * @file stm32f10x_dma.c
4 * @author MCD Application Team
5 * @version V3.1.0
6 * @date 06/19/2009
7 * @brief This file provides all the DMA firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
19 */
20  
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_dma.h"
23 #include "stm32f10x_rcc.h"
24  
25 /** @addtogroup STM32F10x_StdPeriph_Driver
26 * @{
27 */
28  
29 /** @defgroup DMA
30 * @brief DMA driver modules
31 * @{
32 */
33  
34 /** @defgroup DMA_Private_TypesDefinitions
35 * @{
36 */
37 /**
38 * @}
39 */
40  
41 /** @defgroup DMA_Private_Defines
42 * @{
43 */
44  
45 /* DMA ENABLE mask */
46 #define CCR_ENABLE_Set ((uint32_t)0x00000001)
47 #define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)
48  
49 /* DMA1 Channelx interrupt pending bit masks */
50 #define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)
51 #define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)
52 #define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)
53 #define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)
54 #define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)
55 #define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)
56 #define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)
57  
58 /* DMA2 Channelx interrupt pending bit masks */
59 #define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F)
60 #define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0)
61 #define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00)
62 #define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000)
63 #define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000)
64  
65 /* DMA2 FLAG mask */
66 #define FLAG_Mask ((uint32_t)0x10000000)
67  
68 /* DMA registers Masks */
69 #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
70  
71 /**
72 * @}
73 */
74  
75 /** @defgroup DMA_Private_Macros
76 * @{
77 */
78  
79 /**
80 * @}
81 */
82  
83 /** @defgroup DMA_Private_Variables
84 * @{
85 */
86  
87 /**
88 * @}
89 */
90  
91 /** @defgroup DMA_Private_FunctionPrototypes
92 * @{
93 */
94  
95 /**
96 * @}
97 */
98  
99 /** @defgroup DMA_Private_Functions
100 * @{
101 */
102  
103 /**
104 * @brief Deinitializes the DMAy Channelx registers to their default reset
105 * values.
106 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
107 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
108 * @retval None
109 */
110 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
111 {
112 /* Check the parameters */
113 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
114 /* Disable the selected DMAy Channelx */
115 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
116 /* Reset DMAy Channelx control register */
117 DMAy_Channelx->CCR = 0;
118  
119 /* Reset DMAy Channelx remaining bytes register */
120 DMAy_Channelx->CNDTR = 0;
121  
122 /* Reset DMAy Channelx peripheral address register */
123 DMAy_Channelx->CPAR = 0;
124  
125 /* Reset DMAy Channelx memory address register */
126 DMAy_Channelx->CMAR = 0;
127  
128 if (DMAy_Channelx == DMA1_Channel1)
129 {
130 /* Reset interrupt pending bits for DMA1 Channel1 */
131 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
132 }
133 else if (DMAy_Channelx == DMA1_Channel2)
134 {
135 /* Reset interrupt pending bits for DMA1 Channel2 */
136 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
137 }
138 else if (DMAy_Channelx == DMA1_Channel3)
139 {
140 /* Reset interrupt pending bits for DMA1 Channel3 */
141 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
142 }
143 else if (DMAy_Channelx == DMA1_Channel4)
144 {
145 /* Reset interrupt pending bits for DMA1 Channel4 */
146 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
147 }
148 else if (DMAy_Channelx == DMA1_Channel5)
149 {
150 /* Reset interrupt pending bits for DMA1 Channel5 */
151 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
152 }
153 else if (DMAy_Channelx == DMA1_Channel6)
154 {
155 /* Reset interrupt pending bits for DMA1 Channel6 */
156 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
157 }
158 else if (DMAy_Channelx == DMA1_Channel7)
159 {
160 /* Reset interrupt pending bits for DMA1 Channel7 */
161 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
162 }
163 else if (DMAy_Channelx == DMA2_Channel1)
164 {
165 /* Reset interrupt pending bits for DMA2 Channel1 */
166 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
167 }
168 else if (DMAy_Channelx == DMA2_Channel2)
169 {
170 /* Reset interrupt pending bits for DMA2 Channel2 */
171 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
172 }
173 else if (DMAy_Channelx == DMA2_Channel3)
174 {
175 /* Reset interrupt pending bits for DMA2 Channel3 */
176 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
177 }
178 else if (DMAy_Channelx == DMA2_Channel4)
179 {
180 /* Reset interrupt pending bits for DMA2 Channel4 */
181 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
182 }
183 else
184 {
185 if (DMAy_Channelx == DMA2_Channel5)
186 {
187 /* Reset interrupt pending bits for DMA2 Channel5 */
188 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
189 }
190 }
191 }
192  
193 /**
194 * @brief Initializes the DMAy Channelx according to the specified
195 * parameters in the DMA_InitStruct.
196 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
197 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
198 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
199 * contains the configuration information for the specified DMA Channel.
200 * @retval None
201 */
202 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
203 {
204 uint32_t tmpreg = 0;
205  
206 /* Check the parameters */
207 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
208 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
209 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
210 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
211 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
212 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
213 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
214 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
215 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
216 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
217  
218 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
219 /* Get the DMAy_Channelx CCR value */
220 tmpreg = DMAy_Channelx->CCR;
221 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
222 tmpreg &= CCR_CLEAR_Mask;
223 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
224 /* Set DIR bit according to DMA_DIR value */
225 /* Set CIRC bit according to DMA_Mode value */
226 /* Set PINC bit according to DMA_PeripheralInc value */
227 /* Set MINC bit according to DMA_MemoryInc value */
228 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
229 /* Set MSIZE bits according to DMA_MemoryDataSize value */
230 /* Set PL bits according to DMA_Priority value */
231 /* Set the MEM2MEM bit according to DMA_M2M value */
232 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
233 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
234 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
235 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
236  
237 /* Write to DMAy Channelx CCR */
238 DMAy_Channelx->CCR = tmpreg;
239  
240 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
241 /* Write to DMAy Channelx CNDTR */
242 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
243  
244 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
245 /* Write to DMAy Channelx CPAR */
246 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
247  
248 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
249 /* Write to DMAy Channelx CMAR */
250 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
251 }
252  
253 /**
254 * @brief Fills each DMA_InitStruct member with its default value.
255 * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
256 * be initialized.
257 * @retval None
258 */
259 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
260 {
261 /*-------------- Reset DMA init structure parameters values ------------------*/
262 /* Initialize the DMA_PeripheralBaseAddr member */
263 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
264 /* Initialize the DMA_MemoryBaseAddr member */
265 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
266 /* Initialize the DMA_DIR member */
267 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
268 /* Initialize the DMA_BufferSize member */
269 DMA_InitStruct->DMA_BufferSize = 0;
270 /* Initialize the DMA_PeripheralInc member */
271 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
272 /* Initialize the DMA_MemoryInc member */
273 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
274 /* Initialize the DMA_PeripheralDataSize member */
275 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
276 /* Initialize the DMA_MemoryDataSize member */
277 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
278 /* Initialize the DMA_Mode member */
279 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
280 /* Initialize the DMA_Priority member */
281 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
282 /* Initialize the DMA_M2M member */
283 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
284 }
285  
286 /**
287 * @brief Enables or disables the specified DMAy Channelx.
288 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
289 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
290 * @param NewState: new state of the DMAy Channelx.
291 * This parameter can be: ENABLE or DISABLE.
292 * @retval None
293 */
294 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
295 {
296 /* Check the parameters */
297 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
298 assert_param(IS_FUNCTIONAL_STATE(NewState));
299  
300 if (NewState != DISABLE)
301 {
302 /* Enable the selected DMAy Channelx */
303 DMAy_Channelx->CCR |= CCR_ENABLE_Set;
304 }
305 else
306 {
307 /* Disable the selected DMAy Channelx */
308 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
309 }
310 }
311  
312 /**
313 * @brief Enables or disables the specified DMAy Channelx interrupts.
314 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
315 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
316 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
317 * or disabled.
318 * This parameter can be any combination of the following values:
319 * @arg DMA_IT_TC: Transfer complete interrupt mask
320 * @arg DMA_IT_HT: Half transfer interrupt mask
321 * @arg DMA_IT_TE: Transfer error interrupt mask
322 * @param NewState: new state of the specified DMA interrupts.
323 * This parameter can be: ENABLE or DISABLE.
324 * @retval None
325 */
326 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
327 {
328 /* Check the parameters */
329 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
330 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
331 assert_param(IS_FUNCTIONAL_STATE(NewState));
332 if (NewState != DISABLE)
333 {
334 /* Enable the selected DMA interrupts */
335 DMAy_Channelx->CCR |= DMA_IT;
336 }
337 else
338 {
339 /* Disable the selected DMA interrupts */
340 DMAy_Channelx->CCR &= ~DMA_IT;
341 }
342 }
343  
344 /**
345 * @brief Returns the number of remaining data units in the current
346 * DMAy Channelx transfer.
347 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
348 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
349 * @retval The number of remaining data units in the current DMAy Channelx
350 * transfer.
351 */
352 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
353 {
354 /* Check the parameters */
355 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
356 /* Return the number of remaining data units for DMAy Channelx */
357 return ((uint16_t)(DMAy_Channelx->CNDTR));
358 }
359  
360 /**
361 * @brief Checks whether the specified DMAy Channelx flag is set or not.
362 * @param DMA_FLAG: specifies the flag to check.
363 * This parameter can be one of the following values:
364 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
365 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
366 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
367 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
368 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
369 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
370 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
371 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
372 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
373 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
374 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
375 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
376 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
377 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
378 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
379 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
380 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
381 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
382 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
383 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
384 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
385 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
386 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
387 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
388 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
389 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
390 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
391 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
392 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
393 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
394 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
395 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
396 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
397 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
398 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
399 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
400 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
401 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
402 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
403 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
404 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
405 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
406 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
407 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
408 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
409 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
410 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
411 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
412 * @retval The new state of DMA_FLAG (SET or RESET).
413 */
414 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
415 {
416 FlagStatus bitstatus = RESET;
417 uint32_t tmpreg = 0;
418 /* Check the parameters */
419 assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
420  
421 /* Calculate the used DMA */
422 if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
423 {
424 /* Get DMA2 ISR register value */
425 tmpreg = DMA2->ISR ;
426 }
427 else
428 {
429 /* Get DMA1 ISR register value */
430 tmpreg = DMA1->ISR ;
431 }
432  
433 /* Check the status of the specified DMA flag */
434 if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
435 {
436 /* DMA_FLAG is set */
437 bitstatus = SET;
438 }
439 else
440 {
441 /* DMA_FLAG is reset */
442 bitstatus = RESET;
443 }
444  
445 /* Return the DMA_FLAG status */
446 return bitstatus;
447 }
448  
449 /**
450 * @brief Clears the DMAy Channelx's pending flags.
451 * @param DMA_FLAG: specifies the flag to clear.
452 * This parameter can be any combination (for the same DMA) of the following values:
453 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
454 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
455 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
456 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
457 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
458 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
459 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
460 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
461 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
462 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
463 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
464 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
465 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
466 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
467 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
468 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
469 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
470 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
471 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
472 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
473 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
474 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
475 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
476 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
477 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
478 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
479 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
480 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
481 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
482 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
483 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
484 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
485 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
486 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
487 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
488 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
489 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
490 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
491 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
492 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
493 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
494 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
495 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
496 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
497 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
498 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
499 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
500 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
501 * @retval None
502 */
503 void DMA_ClearFlag(uint32_t DMA_FLAG)
504 {
505 /* Check the parameters */
506 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
507 /* Calculate the used DMA */
508  
509 if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
510 {
511 /* Clear the selected DMA flags */
512 DMA2->IFCR = DMA_FLAG;
513 }
514 else
515 {
516 /* Clear the selected DMA flags */
517 DMA1->IFCR = DMA_FLAG;
518 }
519 }
520  
521 /**
522 * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
523 * @param DMA_IT: specifies the DMA interrupt source to check.
524 * This parameter can be one of the following values:
525 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
526 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
527 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
528 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
529 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
530 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
531 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
532 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
533 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
534 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
535 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
536 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
537 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
538 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
539 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
540 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
541 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
542 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
543 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
544 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
545 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
546 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
547 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
548 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
549 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
550 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
551 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
552 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
553 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
554 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
555 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
556 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
557 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
558 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
559 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
560 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
561 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
562 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
563 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
564 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
565 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
566 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
567 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
568 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
569 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
570 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
571 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
572 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
573 * @retval The new state of DMA_IT (SET or RESET).
574 */
575 ITStatus DMA_GetITStatus(uint32_t DMA_IT)
576 {
577 ITStatus bitstatus = RESET;
578 uint32_t tmpreg = 0;
579 /* Check the parameters */
580 assert_param(IS_DMA_GET_IT(DMA_IT));
581  
582 /* Calculate the used DMA */
583 if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
584 {
585 /* Get DMA2 ISR register value */
586 tmpreg = DMA2->ISR ;
587 }
588 else
589 {
590 /* Get DMA1 ISR register value */
591 tmpreg = DMA1->ISR ;
592 }
593  
594 /* Check the status of the specified DMA interrupt */
595 if ((tmpreg & DMA_IT) != (uint32_t)RESET)
596 {
597 /* DMA_IT is set */
598 bitstatus = SET;
599 }
600 else
601 {
602 /* DMA_IT is reset */
603 bitstatus = RESET;
604 }
605 /* Return the DMA_IT status */
606 return bitstatus;
607 }
608  
609 /**
610 * @brief Clears the DMAy Channelx’s interrupt pending bits.
611 * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
612 * This parameter can be any combination (for the same DMA) of the following values:
613 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
614 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
615 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
616 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
617 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
618 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
619 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
620 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
621 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
622 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
623 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
624 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
625 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
626 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
627 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
628 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
629 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
630 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
631 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
632 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
633 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
634 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
635 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
636 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
637 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
638 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
639 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
640 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
641 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
642 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
643 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
644 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
645 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
646 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
647 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
648 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
649 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
650 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
651 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
652 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
653 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
654 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
655 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
656 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
657 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
658 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
659 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
660 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
661 * @retval None
662 */
663 void DMA_ClearITPendingBit(uint32_t DMA_IT)
664 {
665 /* Check the parameters */
666 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
667  
668 /* Calculate the used DMA */
669 if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
670 {
671 /* Clear the selected DMA interrupt pending bits */
672 DMA2->IFCR = DMA_IT;
673 }
674 else
675 {
676 /* Clear the selected DMA interrupt pending bits */
677 DMA1->IFCR = DMA_IT;
678 }
679 }
680  
681 /**
682 * @}
683 */
684  
685 /**
686 * @}
687 */
688  
689 /**
690 * @}
691 */
692  
693 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/