Rev Author Line No. Line
3328 povik 1 /**
2 ******************************************************************************
3 * @file stm32f10x_fsmc.c
4 * @author MCD Application Team
5 * @version V3.1.0
6 * @date 06/19/2009
7 * @brief This file provides all the FSMC firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
19 */
20  
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_fsmc.h"
23 #include "stm32f10x_rcc.h"
24  
25 /** @addtogroup STM32F10x_StdPeriph_Driver
26 * @{
27 */
28  
29 /** @defgroup FSMC
30 * @brief FSMC driver modules
31 * @{
32 */
33  
34 /** @defgroup FSMC_Private_TypesDefinitions
35 * @{
36 */
37 /**
38 * @}
39 */
40  
41 /** @defgroup FSMC_Private_Defines
42 * @{
43 */
44  
45 /* --------------------- FSMC registers bit mask ---------------------------- */
46  
47 /* FSMC BCRx Mask */
48 #define BCR_MBKEN_Set ((uint32_t)0x00000001)
49 #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
50 #define BCR_FACCEN_Set ((uint32_t)0x00000040)
51  
52 /* FSMC PCRx Mask */
53 #define PCR_PBKEN_Set ((uint32_t)0x00000004)
54 #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
55 #define PCR_ECCEN_Set ((uint32_t)0x00000040)
56 #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
57 #define PCR_MemoryType_NAND ((uint32_t)0x00000008)
58 /**
59 * @}
60 */
61  
62 /** @defgroup FSMC_Private_Macros
63 * @{
64 */
65  
66 /**
67 * @}
68 */
69  
70 /** @defgroup FSMC_Private_Variables
71 * @{
72 */
73  
74 /**
75 * @}
76 */
77  
78 /** @defgroup FSMC_Private_FunctionPrototypes
79 * @{
80 */
81  
82 /**
83 * @}
84 */
85  
86 /** @defgroup FSMC_Private_Functions
87 * @{
88 */
89  
90 /**
91 * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
92 * reset values.
93 * @param FSMC_Bank: specifies the FSMC Bank to be used
94 * This parameter can be one of the following values:
95 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
96 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
97 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
98 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
99 * @retval None
100 */
101 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
102 {
103 /* Check the parameter */
104 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
105  
106 /* FSMC_Bank1_NORSRAM1 */
107 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
108 {
109 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
110 }
111 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
112 else
113 {
114 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
115 }
116 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
117 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
118 }
119  
120 /**
121 * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
122 * @param FSMC_Bank: specifies the FSMC Bank to be used
123 * This parameter can be one of the following values:
124 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
125 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
126 * @retval None
127 */
128 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
129 {
130 /* Check the parameter */
131 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
132  
133 if(FSMC_Bank == FSMC_Bank2_NAND)
134 {
135 /* Set the FSMC_Bank2 registers to their reset values */
136 FSMC_Bank2->PCR2 = 0x00000018;
137 FSMC_Bank2->SR2 = 0x00000040;
138 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
139 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
140 }
141 /* FSMC_Bank3_NAND */
142 else
143 {
144 /* Set the FSMC_Bank3 registers to their reset values */
145 FSMC_Bank3->PCR3 = 0x00000018;
146 FSMC_Bank3->SR3 = 0x00000040;
147 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
148 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
149 }
150 }
151  
152 /**
153 * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
154 * @param None
155 * @retval None
156 */
157 void FSMC_PCCARDDeInit(void)
158 {
159 /* Set the FSMC_Bank4 registers to their reset values */
160 FSMC_Bank4->PCR4 = 0x00000018;
161 FSMC_Bank4->SR4 = 0x00000000;
162 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
163 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
164 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
165 }
166  
167 /**
168 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
169 * parameters in the FSMC_NORSRAMInitStruct.
170 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
171 * structure that contains the configuration information for
172 * the FSMC NOR/SRAM specified Banks.
173 * @retval None
174 */
175 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
176 {
177 /* Check the parameters */
178 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
179 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
180 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
181 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
182 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
183 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
184 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
185 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
186 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
187 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
188 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
189 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
190 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
191 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
192 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
193 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
194 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
195 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
196 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
197  
198 /* Bank1 NOR/SRAM control register configuration */
199 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
200 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
201 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
202 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
203 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
204 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
205 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
206 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
207 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
208 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
209 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
210 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
211 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
212 {
213 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
214 }
215 /* Bank1 NOR/SRAM timing register configuration */
216 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
217 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
218 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
219 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
220 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
221 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
222 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
223 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
224  
225  
226 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
227 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
228 {
229 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
230 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
231 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
232 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
233 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
234 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
235 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
236 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
237 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
238 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
239 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
240 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
241 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
242 }
243 else
244 {
245 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
246 }
247 }
248  
249 /**
250 * @brief Initializes the FSMC NAND Banks according to the specified
251 * parameters in the FSMC_NANDInitStruct.
252 * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
253 * structure that contains the configuration information for the FSMC NAND specified Banks.
254 * @retval None
255 */
256 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
257 {
258 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
259  
260 /* Check the parameters */
261 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
262 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
263 assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
264 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
265 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
266 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
267 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
268 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
269 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
270 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
271 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
272 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
273 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
274 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
275 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
276  
277 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
278 tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
279 PCR_MemoryType_NAND |
280 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
281 FSMC_NANDInitStruct->FSMC_ECC |
282 FSMC_NANDInitStruct->FSMC_ECCPageSize |
283 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
284 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
285  
286 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
287 tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
288 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
289 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
290 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
291  
292 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
293 tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
294 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
295 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
296 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
297  
298 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
299 {
300 /* FSMC_Bank2_NAND registers configuration */
301 FSMC_Bank2->PCR2 = tmppcr;
302 FSMC_Bank2->PMEM2 = tmppmem;
303 FSMC_Bank2->PATT2 = tmppatt;
304 }
305 else
306 {
307 /* FSMC_Bank3_NAND registers configuration */
308 FSMC_Bank3->PCR3 = tmppcr;
309 FSMC_Bank3->PMEM3 = tmppmem;
310 FSMC_Bank3->PATT3 = tmppatt;
311 }
312 }
313  
314 /**
315 * @brief Initializes the FSMC PCCARD Bank according to the specified
316 * parameters in the FSMC_PCCARDInitStruct.
317 * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
318 * structure that contains the configuration information for the FSMC PCCARD Bank.
319 * @retval None
320 */
321 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
322 {
323 /* Check the parameters */
324 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
325 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
326 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
327  
328 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
329 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
330 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
331 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
332  
333 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
334 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
335 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
336 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
337 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
338 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
339 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
340 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
341  
342 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
343 FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
344 FSMC_MemoryDataWidth_16b |
345 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
346 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
347  
348 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
349 FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
350 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
351 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
352 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
353  
354 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
355 FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
356 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
357 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
358 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
359  
360 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
361 FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
362 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
363 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
364 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
365 }
366  
367 /**
368 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
369 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
370 * structure which will be initialized.
371 * @retval None
372 */
373 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
374 {
375 /* Reset NOR/SRAM Init structure parameters values */
376 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
377 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
378 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
379 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
380 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
381 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
382 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
383 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
384 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
385 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
386 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
387 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
388 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
389 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
390 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
391 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
392 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
393 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
394 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
395 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
396 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
397 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
398 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
399 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
400 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
401 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
402 }
403  
404 /**
405 * @brief Fills each FSMC_NANDInitStruct member with its default value.
406 * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
407 * structure which will be initialized.
408 * @retval None
409 */
410 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
411 {
412 /* Reset NAND Init structure parameters values */
413 FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
414 FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
415 FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
416 FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
417 FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
418 FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
419 FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
420 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
421 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
422 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
423 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
424 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
425 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
426 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
427 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
428 }
429  
430 /**
431 * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
432 * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
433 * structure which will be initialized.
434 * @retval None
435 */
436 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
437 {
438 /* Reset PCCARD Init structure parameters values */
439 FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
440 FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
441 FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
442 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
443 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
444 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
445 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
446 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
447 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
448 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
449 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
450 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
451 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
452 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
453 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
454 }
455  
456 /**
457 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
458 * @param FSMC_Bank: specifies the FSMC Bank to be used
459 * This parameter can be one of the following values:
460 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
461 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
462 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
463 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
464 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
465 * @retval None
466 */
467 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
468 {
469 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
470 assert_param(IS_FUNCTIONAL_STATE(NewState));
471  
472 if (NewState != DISABLE)
473 {
474 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
475 FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
476 }
477 else
478 {
479 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
480 FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
481 }
482 }
483  
484 /**
485 * @brief Enables or disables the specified NAND Memory Bank.
486 * @param FSMC_Bank: specifies the FSMC Bank to be used
487 * This parameter can be one of the following values:
488 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
489 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
490 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
491 * @retval None
492 */
493 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
494 {
495 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
496 assert_param(IS_FUNCTIONAL_STATE(NewState));
497  
498 if (NewState != DISABLE)
499 {
500 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
501 if(FSMC_Bank == FSMC_Bank2_NAND)
502 {
503 FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
504 }
505 else
506 {
507 FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
508 }
509 }
510 else
511 {
512 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
513 if(FSMC_Bank == FSMC_Bank2_NAND)
514 {
515 FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
516 }
517 else
518 {
519 FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
520 }
521 }
522 }
523  
524 /**
525 * @brief Enables or disables the PCCARD Memory Bank.
526 * @param NewState: new state of the PCCARD Memory Bank.
527 * This parameter can be: ENABLE or DISABLE.
528 * @retval None
529 */
530 void FSMC_PCCARDCmd(FunctionalState NewState)
531 {
532 assert_param(IS_FUNCTIONAL_STATE(NewState));
533  
534 if (NewState != DISABLE)
535 {
536 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
537 FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
538 }
539 else
540 {
541 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
542 FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
543 }
544 }
545  
546 /**
547 * @brief Enables or disables the FSMC NAND ECC feature.
548 * @param FSMC_Bank: specifies the FSMC Bank to be used
549 * This parameter can be one of the following values:
550 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
551 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
552 * @param NewState: new state of the FSMC NAND ECC feature.
553 * This parameter can be: ENABLE or DISABLE.
554 * @retval None
555 */
556 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
557 {
558 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
559 assert_param(IS_FUNCTIONAL_STATE(NewState));
560  
561 if (NewState != DISABLE)
562 {
563 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
564 if(FSMC_Bank == FSMC_Bank2_NAND)
565 {
566 FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
567 }
568 else
569 {
570 FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
571 }
572 }
573 else
574 {
575 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
576 if(FSMC_Bank == FSMC_Bank2_NAND)
577 {
578 FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
579 }
580 else
581 {
582 FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
583 }
584 }
585 }
586  
587 /**
588 * @brief Returns the error correction code register value.
589 * @param FSMC_Bank: specifies the FSMC Bank to be used
590 * This parameter can be one of the following values:
591 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
592 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
593 * @retval The Error Correction Code (ECC) value.
594 */
595 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
596 {
597 uint32_t eccval = 0x00000000;
598  
599 if(FSMC_Bank == FSMC_Bank2_NAND)
600 {
601 /* Get the ECCR2 register value */
602 eccval = FSMC_Bank2->ECCR2;
603 }
604 else
605 {
606 /* Get the ECCR3 register value */
607 eccval = FSMC_Bank3->ECCR3;
608 }
609 /* Return the error correction code value */
610 return(eccval);
611 }
612  
613 /**
614 * @brief Enables or disables the specified FSMC interrupts.
615 * @param FSMC_Bank: specifies the FSMC Bank to be used
616 * This parameter can be one of the following values:
617 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
618 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
619 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
620 * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
621 * This parameter can be any combination of the following values:
622 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
623 * @arg FSMC_IT_Level: Level edge detection interrupt.
624 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
625 * @param NewState: new state of the specified FSMC interrupts.
626 * This parameter can be: ENABLE or DISABLE.
627 * @retval None
628 */
629 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
630 {
631 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
632 assert_param(IS_FSMC_IT(FSMC_IT));
633 assert_param(IS_FUNCTIONAL_STATE(NewState));
634  
635 if (NewState != DISABLE)
636 {
637 /* Enable the selected FSMC_Bank2 interrupts */
638 if(FSMC_Bank == FSMC_Bank2_NAND)
639 {
640 FSMC_Bank2->SR2 |= FSMC_IT;
641 }
642 /* Enable the selected FSMC_Bank3 interrupts */
643 else if (FSMC_Bank == FSMC_Bank3_NAND)
644 {
645 FSMC_Bank3->SR3 |= FSMC_IT;
646 }
647 /* Enable the selected FSMC_Bank4 interrupts */
648 else
649 {
650 FSMC_Bank4->SR4 |= FSMC_IT;
651 }
652 }
653 else
654 {
655 /* Disable the selected FSMC_Bank2 interrupts */
656 if(FSMC_Bank == FSMC_Bank2_NAND)
657 {
658  
659 FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
660 }
661 /* Disable the selected FSMC_Bank3 interrupts */
662 else if (FSMC_Bank == FSMC_Bank3_NAND)
663 {
664 FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
665 }
666 /* Disable the selected FSMC_Bank4 interrupts */
667 else
668 {
669 FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
670 }
671 }
672 }
673  
674 /**
675 * @brief Checks whether the specified FSMC flag is set or not.
676 * @param FSMC_Bank: specifies the FSMC Bank to be used
677 * This parameter can be one of the following values:
678 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
679 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
680 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
681 * @param FSMC_FLAG: specifies the flag to check.
682 * This parameter can be one of the following values:
683 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
684 * @arg FSMC_FLAG_Level: Level detection Flag.
685 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
686 * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
687 * @retval The new state of FSMC_FLAG (SET or RESET).
688 */
689 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
690 {
691 FlagStatus bitstatus = RESET;
692 uint32_t tmpsr = 0x00000000;
693  
694 /* Check the parameters */
695 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
696 assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
697  
698 if(FSMC_Bank == FSMC_Bank2_NAND)
699 {
700 tmpsr = FSMC_Bank2->SR2;
701 }
702 else if(FSMC_Bank == FSMC_Bank3_NAND)
703 {
704 tmpsr = FSMC_Bank3->SR3;
705 }
706 /* FSMC_Bank4_PCCARD*/
707 else
708 {
709 tmpsr = FSMC_Bank4->SR4;
710 }
711  
712 /* Get the flag status */
713 if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
714 {
715 bitstatus = SET;
716 }
717 else
718 {
719 bitstatus = RESET;
720 }
721 /* Return the flag status */
722 return bitstatus;
723 }
724  
725 /**
726 * @brief Clears the FSMC’s pending flags.
727 * @param FSMC_Bank: specifies the FSMC Bank to be used
728 * This parameter can be one of the following values:
729 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
730 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
731 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
732 * @param FSMC_FLAG: specifies the flag to clear.
733 * This parameter can be any combination of the following values:
734 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
735 * @arg FSMC_FLAG_Level: Level detection Flag.
736 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
737 * @retval None
738 */
739 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
740 {
741 /* Check the parameters */
742 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
743 assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
744  
745 if(FSMC_Bank == FSMC_Bank2_NAND)
746 {
747 FSMC_Bank2->SR2 &= ~FSMC_FLAG;
748 }
749 else if(FSMC_Bank == FSMC_Bank3_NAND)
750 {
751 FSMC_Bank3->SR3 &= ~FSMC_FLAG;
752 }
753 /* FSMC_Bank4_PCCARD*/
754 else
755 {
756 FSMC_Bank4->SR4 &= ~FSMC_FLAG;
757 }
758 }
759  
760 /**
761 * @brief Checks whether the specified FSMC interrupt has occurred or not.
762 * @param FSMC_Bank: specifies the FSMC Bank to be used
763 * This parameter can be one of the following values:
764 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
765 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
766 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
767 * @param FSMC_IT: specifies the FSMC interrupt source to check.
768 * This parameter can be one of the following values:
769 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
770 * @arg FSMC_IT_Level: Level edge detection interrupt.
771 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
772 * @retval The new state of FSMC_IT (SET or RESET).
773 */
774 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
775 {
776 ITStatus bitstatus = RESET;
777 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
778  
779 /* Check the parameters */
780 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
781 assert_param(IS_FSMC_GET_IT(FSMC_IT));
782  
783 if(FSMC_Bank == FSMC_Bank2_NAND)
784 {
785 tmpsr = FSMC_Bank2->SR2;
786 }
787 else if(FSMC_Bank == FSMC_Bank3_NAND)
788 {
789 tmpsr = FSMC_Bank3->SR3;
790 }
791 /* FSMC_Bank4_PCCARD*/
792 else
793 {
794 tmpsr = FSMC_Bank4->SR4;
795 }
796  
797 itstatus = tmpsr & FSMC_IT;
798  
799 itenable = tmpsr & (FSMC_IT >> 3);
800 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
801 {
802 bitstatus = SET;
803 }
804 else
805 {
806 bitstatus = RESET;
807 }
808 return bitstatus;
809 }
810  
811 /**
812 * @brief Clears the FSMC’s interrupt pending bits.
813 * @param FSMC_Bank: specifies the FSMC Bank to be used
814 * This parameter can be one of the following values:
815 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
816 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
817 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
818 * @param FSMC_IT: specifies the interrupt pending bit to clear.
819 * This parameter can be any combination of the following values:
820 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
821 * @arg FSMC_IT_Level: Level edge detection interrupt.
822 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
823 * @retval None
824 */
825 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
826 {
827 /* Check the parameters */
828 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
829 assert_param(IS_FSMC_IT(FSMC_IT));
830  
831 if(FSMC_Bank == FSMC_Bank2_NAND)
832 {
833 FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
834 }
835 else if(FSMC_Bank == FSMC_Bank3_NAND)
836 {
837 FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
838 }
839 /* FSMC_Bank4_PCCARD*/
840 else
841 {
842 FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
843 }
844 }
845  
846 /**
847 * @}
848 */
849  
850 /**
851 * @}
852 */
853  
854 /**
855 * @}
856 */
857  
858 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/