Rev Author Line No. Line
3328 povik 1 /**
2 ******************************************************************************
3 * @file stm32f10x_i2c.c
4 * @author MCD Application Team
5 * @version V3.1.0
6 * @date 06/19/2009
7 * @brief This file provides all the I2C firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
19 */
20  
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_i2c.h"
23 #include "stm32f10x_rcc.h"
24  
25  
26 /** @addtogroup STM32F10x_StdPeriph_Driver
27 * @{
28 */
29  
30 /** @defgroup I2C
31 * @brief I2C driver modules
32 * @{
33 */
34  
35 /** @defgroup I2C_Private_TypesDefinitions
36 * @{
37 */
38  
39 /**
40 * @}
41 */
42  
43 /** @defgroup I2C_Private_Defines
44 * @{
45 */
46  
47 /* I2C SPE mask */
48 #define CR1_PE_Set ((uint16_t)0x0001)
49 #define CR1_PE_Reset ((uint16_t)0xFFFE)
50  
51 /* I2C START mask */
52 #define CR1_START_Set ((uint16_t)0x0100)
53 #define CR1_START_Reset ((uint16_t)0xFEFF)
54  
55 /* I2C STOP mask */
56 #define CR1_STOP_Set ((uint16_t)0x0200)
57 #define CR1_STOP_Reset ((uint16_t)0xFDFF)
58  
59 /* I2C ACK mask */
60 #define CR1_ACK_Set ((uint16_t)0x0400)
61 #define CR1_ACK_Reset ((uint16_t)0xFBFF)
62  
63 /* I2C ENGC mask */
64 #define CR1_ENGC_Set ((uint16_t)0x0040)
65 #define CR1_ENGC_Reset ((uint16_t)0xFFBF)
66  
67 /* I2C SWRST mask */
68 #define CR1_SWRST_Set ((uint16_t)0x8000)
69 #define CR1_SWRST_Reset ((uint16_t)0x7FFF)
70  
71 /* I2C PEC mask */
72 #define CR1_PEC_Set ((uint16_t)0x1000)
73 #define CR1_PEC_Reset ((uint16_t)0xEFFF)
74  
75 /* I2C ENPEC mask */
76 #define CR1_ENPEC_Set ((uint16_t)0x0020)
77 #define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
78  
79 /* I2C ENARP mask */
80 #define CR1_ENARP_Set ((uint16_t)0x0010)
81 #define CR1_ENARP_Reset ((uint16_t)0xFFEF)
82  
83 /* I2C NOSTRETCH mask */
84 #define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
85 #define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
86  
87 /* I2C registers Masks */
88 #define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
89  
90 /* I2C DMAEN mask */
91 #define CR2_DMAEN_Set ((uint16_t)0x0800)
92 #define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
93  
94 /* I2C LAST mask */
95 #define CR2_LAST_Set ((uint16_t)0x1000)
96 #define CR2_LAST_Reset ((uint16_t)0xEFFF)
97  
98 /* I2C FREQ mask */
99 #define CR2_FREQ_Reset ((uint16_t)0xFFC0)
100  
101 /* I2C ADD0 mask */
102 #define OAR1_ADD0_Set ((uint16_t)0x0001)
103 #define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
104  
105 /* I2C ENDUAL mask */
106 #define OAR2_ENDUAL_Set ((uint16_t)0x0001)
107 #define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
108  
109 /* I2C ADD2 mask */
110 #define OAR2_ADD2_Reset ((uint16_t)0xFF01)
111  
112 /* I2C F/S mask */
113 #define CCR_FS_Set ((uint16_t)0x8000)
114  
115 /* I2C CCR mask */
116 #define CCR_CCR_Set ((uint16_t)0x0FFF)
117  
118 /* I2C FLAG mask */
119 #define FLAG_Mask ((uint32_t)0x00FFFFFF)
120  
121 /* I2C Interrupt Enable mask */
122 #define ITEN_Mask ((uint32_t)0x07000000)
123  
124 /**
125 * @}
126 */
127  
128 /** @defgroup I2C_Private_Macros
129 * @{
130 */
131  
132 /**
133 * @}
134 */
135  
136 /** @defgroup I2C_Private_Variables
137 * @{
138 */
139  
140 /**
141 * @}
142 */
143  
144 /** @defgroup I2C_Private_FunctionPrototypes
145 * @{
146 */
147  
148 /**
149 * @}
150 */
151  
152 /** @defgroup I2C_Private_Functions
153 * @{
154 */
155  
156 /**
157 * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
158 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
159 * @retval None
160 */
161 void I2C_DeInit(I2C_TypeDef* I2Cx)
162 {
163 /* Check the parameters */
164 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
165  
166 if (I2Cx == I2C1)
167 {
168 /* Enable I2C1 reset state */
169 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
170 /* Release I2C1 from reset state */
171 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
172 }
173 else
174 {
175 /* Enable I2C2 reset state */
176 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
177 /* Release I2C2 from reset state */
178 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
179 }
180 }
181  
182 /**
183 * @brief Initializes the I2Cx peripheral according to the specified
184 * parameters in the I2C_InitStruct.
185 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
186 * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
187 * contains the configuration information for the specified I2C peripheral.
188 * @retval None
189 */
190 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
191 {
192 uint16_t tmpreg = 0, freqrange = 0;
193 uint16_t result = 0x04;
194 uint32_t pclk1 = 8000000;
195 RCC_ClocksTypeDef rcc_clocks;
196 /* Check the parameters */
197 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
198 assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
199 assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
200 assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
201 assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
202 assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
203 assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
204  
205 /*---------------------------- I2Cx CR2 Configuration ------------------------*/
206 /* Get the I2Cx CR2 value */
207 tmpreg = I2Cx->CR2;
208 /* Clear frequency FREQ[5:0] bits */
209 tmpreg &= CR2_FREQ_Reset;
210 /* Get pclk1 frequency value */
211 RCC_GetClocksFreq(&rcc_clocks);
212 pclk1 = rcc_clocks.PCLK1_Frequency;
213 /* Set frequency bits depending on pclk1 value */
214 freqrange = (uint16_t)(pclk1 / 1000000);
215 tmpreg |= freqrange;
216 /* Write to I2Cx CR2 */
217 I2Cx->CR2 = tmpreg;
218  
219 /*---------------------------- I2Cx CCR Configuration ------------------------*/
220 /* Disable the selected I2C peripheral to configure TRISE */
221 I2Cx->CR1 &= CR1_PE_Reset;
222 /* Reset tmpreg value */
223 /* Clear F/S, DUTY and CCR[11:0] bits */
224 tmpreg = 0;
225  
226 /* Configure speed in standard mode */
227 if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
228 {
229 /* Standard mode speed calculate */
230 result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
231 /* Test if CCR value is under 0x4*/
232 if (result < 0x04)
233 {
234 /* Set minimum allowed value */
235 result = 0x04;
236 }
237 /* Set speed value for standard mode */
238 tmpreg |= result;
239 /* Set Maximum Rise Time for standard mode */
240 I2Cx->TRISE = freqrange + 1;
241 }
242 /* Configure speed in fast mode */
243 else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
244 {
245 if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
246 {
247 /* Fast mode speed calculate: Tlow/Thigh = 2 */
248 result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
249 }
250 else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
251 {
252 /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
253 result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
254 /* Set DUTY bit */
255 result |= I2C_DutyCycle_16_9;
256 }
257  
258 /* Test if CCR value is under 0x1*/
259 if ((result & CCR_CCR_Set) == 0)
260 {
261 /* Set minimum allowed value */
262 result |= (uint16_t)0x0001;
263 }
264 /* Set speed value and set F/S bit for fast mode */
265 tmpreg |= (uint16_t)(result | CCR_FS_Set);
266 /* Set Maximum Rise Time for fast mode */
267 I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
268 }
269  
270 /* Write to I2Cx CCR */
271 I2Cx->CCR = tmpreg;
272 /* Enable the selected I2C peripheral */
273 I2Cx->CR1 |= CR1_PE_Set;
274  
275 /*---------------------------- I2Cx CR1 Configuration ------------------------*/
276 /* Get the I2Cx CR1 value */
277 tmpreg = I2Cx->CR1;
278 /* Clear ACK, SMBTYPE and SMBUS bits */
279 tmpreg &= CR1_CLEAR_Mask;
280 /* Configure I2Cx: mode and acknowledgement */
281 /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
282 /* Set ACK bit according to I2C_Ack value */
283 tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
284 /* Write to I2Cx CR1 */
285 I2Cx->CR1 = tmpreg;
286  
287 /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
288 /* Set I2Cx Own Address1 and acknowledged address */
289 I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
290 }
291  
292 /**
293 * @brief Fills each I2C_InitStruct member with its default value.
294 * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
295 * @retval None
296 */
297 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
298 {
299 /*---------------- Reset I2C init structure parameters values ----------------*/
300 /* initialize the I2C_ClockSpeed member */
301 I2C_InitStruct->I2C_ClockSpeed = 5000;
302 /* Initialize the I2C_Mode member */
303 I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
304 /* Initialize the I2C_DutyCycle member */
305 I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
306 /* Initialize the I2C_OwnAddress1 member */
307 I2C_InitStruct->I2C_OwnAddress1 = 0;
308 /* Initialize the I2C_Ack member */
309 I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
310 /* Initialize the I2C_AcknowledgedAddress member */
311 I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
312 }
313  
314 /**
315 * @brief Enables or disables the specified I2C peripheral.
316 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
317 * @param NewState: new state of the I2Cx peripheral.
318 * This parameter can be: ENABLE or DISABLE.
319 * @retval None
320 */
321 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
322 {
323 /* Check the parameters */
324 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
325 assert_param(IS_FUNCTIONAL_STATE(NewState));
326 if (NewState != DISABLE)
327 {
328 /* Enable the selected I2C peripheral */
329 I2Cx->CR1 |= CR1_PE_Set;
330 }
331 else
332 {
333 /* Disable the selected I2C peripheral */
334 I2Cx->CR1 &= CR1_PE_Reset;
335 }
336 }
337  
338 /**
339 * @brief Enables or disables the specified I2C DMA requests.
340 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
341 * @param NewState: new state of the I2C DMA transfer.
342 * This parameter can be: ENABLE or DISABLE.
343 * @retval None
344 */
345 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
346 {
347 /* Check the parameters */
348 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
349 assert_param(IS_FUNCTIONAL_STATE(NewState));
350 if (NewState != DISABLE)
351 {
352 /* Enable the selected I2C DMA requests */
353 I2Cx->CR2 |= CR2_DMAEN_Set;
354 }
355 else
356 {
357 /* Disable the selected I2C DMA requests */
358 I2Cx->CR2 &= CR2_DMAEN_Reset;
359 }
360 }
361  
362 /**
363 * @brief Specifies that the next DMA transfer is the last one.
364 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
365 * @param NewState: new state of the I2C DMA last transfer.
366 * This parameter can be: ENABLE or DISABLE.
367 * @retval None
368 */
369 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
370 {
371 /* Check the parameters */
372 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
373 assert_param(IS_FUNCTIONAL_STATE(NewState));
374 if (NewState != DISABLE)
375 {
376 /* Next DMA transfer is the last transfer */
377 I2Cx->CR2 |= CR2_LAST_Set;
378 }
379 else
380 {
381 /* Next DMA transfer is not the last transfer */
382 I2Cx->CR2 &= CR2_LAST_Reset;
383 }
384 }
385  
386 /**
387 * @brief Generates I2Cx communication START condition.
388 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
389 * @param NewState: new state of the I2C START condition generation.
390 * This parameter can be: ENABLE or DISABLE.
391 * @retval None.
392 */
393 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
394 {
395 /* Check the parameters */
396 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
397 assert_param(IS_FUNCTIONAL_STATE(NewState));
398 if (NewState != DISABLE)
399 {
400 /* Generate a START condition */
401 I2Cx->CR1 |= CR1_START_Set;
402 }
403 else
404 {
405 /* Disable the START condition generation */
406 I2Cx->CR1 &= CR1_START_Reset;
407 }
408 }
409  
410 /**
411 * @brief Generates I2Cx communication STOP condition.
412 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
413 * @param NewState: new state of the I2C STOP condition generation.
414 * This parameter can be: ENABLE or DISABLE.
415 * @retval None.
416 */
417 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
418 {
419 /* Check the parameters */
420 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
421 assert_param(IS_FUNCTIONAL_STATE(NewState));
422 if (NewState != DISABLE)
423 {
424 /* Generate a STOP condition */
425 I2Cx->CR1 |= CR1_STOP_Set;
426 }
427 else
428 {
429 /* Disable the STOP condition generation */
430 I2Cx->CR1 &= CR1_STOP_Reset;
431 }
432 }
433  
434 /**
435 * @brief Enables or disables the specified I2C acknowledge feature.
436 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
437 * @param NewState: new state of the I2C Acknowledgement.
438 * This parameter can be: ENABLE or DISABLE.
439 * @retval None.
440 */
441 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
442 {
443 /* Check the parameters */
444 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
445 assert_param(IS_FUNCTIONAL_STATE(NewState));
446 if (NewState != DISABLE)
447 {
448 /* Enable the acknowledgement */
449 I2Cx->CR1 |= CR1_ACK_Set;
450 }
451 else
452 {
453 /* Disable the acknowledgement */
454 I2Cx->CR1 &= CR1_ACK_Reset;
455 }
456 }
457  
458 /**
459 * @brief Configures the specified I2C own address2.
460 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
461 * @param Address: specifies the 7bit I2C own address2.
462 * @retval None.
463 */
464 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
465 {
466 uint16_t tmpreg = 0;
467  
468 /* Check the parameters */
469 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
470  
471 /* Get the old register value */
472 tmpreg = I2Cx->OAR2;
473  
474 /* Reset I2Cx Own address2 bit [7:1] */
475 tmpreg &= OAR2_ADD2_Reset;
476  
477 /* Set I2Cx Own address2 */
478 tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
479  
480 /* Store the new register value */
481 I2Cx->OAR2 = tmpreg;
482 }
483  
484 /**
485 * @brief Enables or disables the specified I2C dual addressing mode.
486 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
487 * @param NewState: new state of the I2C dual addressing mode.
488 * This parameter can be: ENABLE or DISABLE.
489 * @retval None
490 */
491 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
492 {
493 /* Check the parameters */
494 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
495 assert_param(IS_FUNCTIONAL_STATE(NewState));
496 if (NewState != DISABLE)
497 {
498 /* Enable dual addressing mode */
499 I2Cx->OAR2 |= OAR2_ENDUAL_Set;
500 }
501 else
502 {
503 /* Disable dual addressing mode */
504 I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
505 }
506 }
507  
508 /**
509 * @brief Enables or disables the specified I2C general call feature.
510 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
511 * @param NewState: new state of the I2C General call.
512 * This parameter can be: ENABLE or DISABLE.
513 * @retval None
514 */
515 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
516 {
517 /* Check the parameters */
518 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
519 assert_param(IS_FUNCTIONAL_STATE(NewState));
520 if (NewState != DISABLE)
521 {
522 /* Enable generall call */
523 I2Cx->CR1 |= CR1_ENGC_Set;
524 }
525 else
526 {
527 /* Disable generall call */
528 I2Cx->CR1 &= CR1_ENGC_Reset;
529 }
530 }
531  
532 /**
533 * @brief Enables or disables the specified I2C interrupts.
534 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
535 * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
536 * This parameter can be any combination of the following values:
537 * @arg I2C_IT_BUF: Buffer interrupt mask
538 * @arg I2C_IT_EVT: Event interrupt mask
539 * @arg I2C_IT_ERR: Error interrupt mask
540 * @param NewState: new state of the specified I2C interrupts.
541 * This parameter can be: ENABLE or DISABLE.
542 * @retval None
543 */
544 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
545 {
546 /* Check the parameters */
547 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
548 assert_param(IS_FUNCTIONAL_STATE(NewState));
549 assert_param(IS_I2C_CONFIG_IT(I2C_IT));
550  
551 if (NewState != DISABLE)
552 {
553 /* Enable the selected I2C interrupts */
554 I2Cx->CR2 |= I2C_IT;
555 }
556 else
557 {
558 /* Disable the selected I2C interrupts */
559 I2Cx->CR2 &= (uint16_t)~I2C_IT;
560 }
561 }
562  
563 /**
564 * @brief Sends a data byte through the I2Cx peripheral.
565 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
566 * @param Data: Byte to be transmitted..
567 * @retval None
568 */
569 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
570 {
571 /* Check the parameters */
572 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
573 /* Write in the DR register the data to be sent */
574 I2Cx->DR = Data;
575 }
576  
577 /**
578 * @brief Returns the most recent received data by the I2Cx peripheral.
579 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
580 * @retval The value of the received data.
581 */
582 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
583 {
584 /* Check the parameters */
585 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
586 /* Return the data in the DR register */
587 return (uint8_t)I2Cx->DR;
588 }
589  
590 /**
591 * @brief Transmits the address byte to select the slave device.
592 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
593 * @param Address: specifies the slave address which will be transmitted
594 * @param I2C_Direction: specifies whether the I2C device will be a
595 * Transmitter or a Receiver. This parameter can be one of the following values
596 * @arg I2C_Direction_Transmitter: Transmitter mode
597 * @arg I2C_Direction_Receiver: Receiver mode
598 * @retval None.
599 */
600 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
601 {
602 /* Check the parameters */
603 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
604 assert_param(IS_I2C_DIRECTION(I2C_Direction));
605 /* Test on the direction to set/reset the read/write bit */
606 if (I2C_Direction != I2C_Direction_Transmitter)
607 {
608 /* Set the address bit0 for read */
609 Address |= OAR1_ADD0_Set;
610 }
611 else
612 {
613 /* Reset the address bit0 for write */
614 Address &= OAR1_ADD0_Reset;
615 }
616 /* Send the address */
617 I2Cx->DR = Address;
618 }
619  
620 /**
621 * @brief Reads the specified I2C register and returns its value.
622 * @param I2C_Register: specifies the register to read.
623 * This parameter can be one of the following values:
624 * @arg I2C_Register_CR1: CR1 register.
625 * @arg I2C_Register_CR2: CR2 register.
626 * @arg I2C_Register_OAR1: OAR1 register.
627 * @arg I2C_Register_OAR2: OAR2 register.
628 * @arg I2C_Register_DR: DR register.
629 * @arg I2C_Register_SR1: SR1 register.
630 * @arg I2C_Register_SR2: SR2 register.
631 * @arg I2C_Register_CCR: CCR register.
632 * @arg I2C_Register_TRISE: TRISE register.
633 * @retval The value of the read register.
634 */
635 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
636 {
637 __IO uint32_t tmp = 0;
638  
639 /* Check the parameters */
640 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
641 assert_param(IS_I2C_REGISTER(I2C_Register));
642  
643 tmp = (uint32_t) I2Cx;
644 tmp += I2C_Register;
645  
646 /* Return the selected register value */
647 return (*(__IO uint16_t *) tmp);
648 }
649  
650 /**
651 * @brief Enables or disables the specified I2C software reset.
652 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
653 * @param NewState: new state of the I2C software reset.
654 * This parameter can be: ENABLE or DISABLE.
655 * @retval None
656 */
657 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
658 {
659 /* Check the parameters */
660 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
661 assert_param(IS_FUNCTIONAL_STATE(NewState));
662 if (NewState != DISABLE)
663 {
664 /* Peripheral under reset */
665 I2Cx->CR1 |= CR1_SWRST_Set;
666 }
667 else
668 {
669 /* Peripheral not under reset */
670 I2Cx->CR1 &= CR1_SWRST_Reset;
671 }
672 }
673  
674 /**
675 * @brief Drives the SMBusAlert pin high or low for the specified I2C.
676 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
677 * @param I2C_SMBusAlert: specifies SMBAlert pin level.
678 * This parameter can be one of the following values:
679 * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
680 * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
681 * @retval None
682 */
683 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
684 {
685 /* Check the parameters */
686 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
687 assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
688 if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
689 {
690 /* Drive the SMBusAlert pin Low */
691 I2Cx->CR1 |= I2C_SMBusAlert_Low;
692 }
693 else
694 {
695 /* Drive the SMBusAlert pin High */
696 I2Cx->CR1 &= I2C_SMBusAlert_High;
697 }
698 }
699  
700 /**
701 * @brief Enables or disables the specified I2C PEC transfer.
702 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
703 * @param NewState: new state of the I2C PEC transmission.
704 * This parameter can be: ENABLE or DISABLE.
705 * @retval None
706 */
707 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
708 {
709 /* Check the parameters */
710 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
711 assert_param(IS_FUNCTIONAL_STATE(NewState));
712 if (NewState != DISABLE)
713 {
714 /* Enable the selected I2C PEC transmission */
715 I2Cx->CR1 |= CR1_PEC_Set;
716 }
717 else
718 {
719 /* Disable the selected I2C PEC transmission */
720 I2Cx->CR1 &= CR1_PEC_Reset;
721 }
722 }
723  
724 /**
725 * @brief Selects the specified I2C PEC position.
726 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
727 * @param I2C_PECPosition: specifies the PEC position.
728 * This parameter can be one of the following values:
729 * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
730 * @arg I2C_PECPosition_Current: indicates that current byte is PEC
731 * @retval None
732 */
733 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
734 {
735 /* Check the parameters */
736 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
737 assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
738 if (I2C_PECPosition == I2C_PECPosition_Next)
739 {
740 /* Next byte in shift register is PEC */
741 I2Cx->CR1 |= I2C_PECPosition_Next;
742 }
743 else
744 {
745 /* Current byte in shift register is PEC */
746 I2Cx->CR1 &= I2C_PECPosition_Current;
747 }
748 }
749  
750 /**
751 * @brief Enables or disables the PEC value calculation of the transfered bytes.
752 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
753 * @param NewState: new state of the I2Cx PEC value calculation.
754 * This parameter can be: ENABLE or DISABLE.
755 * @retval None
756 */
757 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
758 {
759 /* Check the parameters */
760 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
761 assert_param(IS_FUNCTIONAL_STATE(NewState));
762 if (NewState != DISABLE)
763 {
764 /* Enable the selected I2C PEC calculation */
765 I2Cx->CR1 |= CR1_ENPEC_Set;
766 }
767 else
768 {
769 /* Disable the selected I2C PEC calculation */
770 I2Cx->CR1 &= CR1_ENPEC_Reset;
771 }
772 }
773  
774 /**
775 * @brief Returns the PEC value for the specified I2C.
776 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
777 * @retval The PEC value.
778 */
779 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
780 {
781 /* Check the parameters */
782 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
783 /* Return the selected I2C PEC value */
784 return ((I2Cx->SR2) >> 8);
785 }
786  
787 /**
788 * @brief Enables or disables the specified I2C ARP.
789 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
790 * @param NewState: new state of the I2Cx ARP.
791 * This parameter can be: ENABLE or DISABLE.
792 * @retval None
793 */
794 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
795 {
796 /* Check the parameters */
797 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
798 assert_param(IS_FUNCTIONAL_STATE(NewState));
799 if (NewState != DISABLE)
800 {
801 /* Enable the selected I2C ARP */
802 I2Cx->CR1 |= CR1_ENARP_Set;
803 }
804 else
805 {
806 /* Disable the selected I2C ARP */
807 I2Cx->CR1 &= CR1_ENARP_Reset;
808 }
809 }
810  
811 /**
812 * @brief Enables or disables the specified I2C Clock stretching.
813 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
814 * @param NewState: new state of the I2Cx Clock stretching.
815 * This parameter can be: ENABLE or DISABLE.
816 * @retval None
817 */
818 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
819 {
820 /* Check the parameters */
821 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
822 assert_param(IS_FUNCTIONAL_STATE(NewState));
823 if (NewState == DISABLE)
824 {
825 /* Enable the selected I2C Clock stretching */
826 I2Cx->CR1 |= CR1_NOSTRETCH_Set;
827 }
828 else
829 {
830 /* Disable the selected I2C Clock stretching */
831 I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
832 }
833 }
834  
835 /**
836 * @brief Selects the specified I2C fast mode duty cycle.
837 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
838 * @param I2C_DutyCycle: specifies the fast mode duty cycle.
839 * This parameter can be one of the following values:
840 * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
841 * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
842 * @retval None
843 */
844 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
845 {
846 /* Check the parameters */
847 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
848 assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
849 if (I2C_DutyCycle != I2C_DutyCycle_16_9)
850 {
851 /* I2C fast mode Tlow/Thigh=2 */
852 I2Cx->CCR &= I2C_DutyCycle_2;
853 }
854 else
855 {
856 /* I2C fast mode Tlow/Thigh=16/9 */
857 I2Cx->CCR |= I2C_DutyCycle_16_9;
858 }
859 }
860  
861 /**
862 * @brief Returns the last I2Cx Event.
863 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
864 * @retval The last event
865 */
866 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
867 {
868 uint32_t lastevent = 0;
869 uint32_t flag1 = 0, flag2 = 0;
870 /* Check the parameters */
871 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
872 /* Read the I2Cx status register */
873 flag1 = I2Cx->SR1;
874 flag2 = I2Cx->SR2;
875 flag2 = flag2 << 16;
876 /* Get the last event value from I2C status register */
877 lastevent = (flag1 | flag2) & FLAG_Mask;
878 /* Return status */
879 return lastevent;
880 }
881  
882 /**
883 * @brief Checks whether the last I2Cx Event is equal to the one passed
884 * as parameter.
885 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
886 * @param I2C_EVENT: specifies the event to be checked.
887 * This parameter can be one of the following values:
888 * @arg I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1
889 * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
890 * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
891 * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2
892 * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
893 * @arg I2C_EVENT_MASTER_MODE_SELECTED : EV6
894 * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
895 * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8
896 * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
897 * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
898 * @retval An ErrorStatus enumuration value:
899 * - SUCCESS: Last event is equal to the I2C_EVENT
900 * - ERROR: Last event is different from the I2C_EVENT
901 */
902 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
903 {
904 uint32_t lastevent = 0;
905 uint32_t flag1 = 0, flag2 = 0;
906 ErrorStatus status = ERROR;
907 /* Check the parameters */
908 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
909 assert_param(IS_I2C_EVENT(I2C_EVENT));
910 /* Read the I2Cx status register */
911 flag1 = I2Cx->SR1;
912 flag2 = I2Cx->SR2;
913 flag2 = flag2 << 16;
914 /* Get the last event value from I2C status register */
915 lastevent = (flag1 | flag2) & FLAG_Mask;
916 /* Check whether the last event is equal to I2C_EVENT */
917 if (lastevent == I2C_EVENT )
918 {
919 /* SUCCESS: last event is equal to I2C_EVENT */
920 status = SUCCESS;
921 }
922 else
923 {
924 /* ERROR: last event is different from I2C_EVENT */
925 status = ERROR;
926 }
927 /* Return status */
928 return status;
929 }
930  
931 /**
932 * @brief Checks whether the specified I2C flag is set or not.
933 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
934 * @param I2C_FLAG: specifies the flag to check.
935 * This parameter can be one of the following values:
936 * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
937 * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
938 * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
939 * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
940 * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
941 * @arg I2C_FLAG_BUSY: Bus busy flag
942 * @arg I2C_FLAG_MSL: Master/Slave flag
943 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
944 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
945 * @arg I2C_FLAG_PECERR: PEC error in reception flag
946 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
947 * @arg I2C_FLAG_AF: Acknowledge failure flag
948 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
949 * @arg I2C_FLAG_BERR: Bus error flag
950 * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
951 * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
952 * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
953 * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
954 * @arg I2C_FLAG_BTF: Byte transfer finished flag
955 * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL”
956 * Address matched flag (Slave mode)”ENDAD”
957 * @arg I2C_FLAG_SB: Start bit flag (Master mode)
958 * @retval The new state of I2C_FLAG (SET or RESET).
959 */
960 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
961 {
962 FlagStatus bitstatus = RESET;
963 __IO uint32_t i2creg = 0, i2cxbase = 0;
964  
965 /* Check the parameters */
966 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
967 assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
968  
969 /* Get the I2Cx peripheral base address */
970 i2cxbase = (uint32_t)I2Cx;
971  
972 /* Read flag register index */
973 i2creg = I2C_FLAG >> 28;
974  
975 /* Get bit[23:0] of the flag */
976 I2C_FLAG &= FLAG_Mask;
977  
978 if(i2creg != 0)
979 {
980 /* Get the I2Cx SR1 register address */
981 i2cxbase += 0x14;
982 }
983 else
984 {
985 /* Flag in I2Cx SR2 Register */
986 I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
987 /* Get the I2Cx SR2 register address */
988 i2cxbase += 0x18;
989 }
990  
991 if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
992 {
993 /* I2C_FLAG is set */
994 bitstatus = SET;
995 }
996 else
997 {
998 /* I2C_FLAG is reset */
999 bitstatus = RESET;
1000 }
1001  
1002 /* Return the I2C_FLAG status */
1003 return bitstatus;
1004 }
1005  
1006 /**
1007 * @brief Clears the I2Cx's pending flags.
1008 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
1009 * @param I2C_FLAG: specifies the flag to clear.
1010 * This parameter can be any combination of the following values:
1011 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
1012 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
1013 * @arg I2C_FLAG_PECERR: PEC error in reception flag
1014 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
1015 * @arg I2C_FLAG_AF: Acknowledge failure flag
1016 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
1017 * @arg I2C_FLAG_BERR: Bus error flag
1018 *
1019 * @note
1020 * - STOPF (STOP detection) is cleared by software sequence: a read operation
1021 * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
1022 * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
1023 * - ADD10 (10-bit header sent) is cleared by software sequence: a read
1024 * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
1025 * second byte of the address in DR register.
1026 * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
1027 * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
1028 * read/write to I2C_DR register (I2C_SendData()).
1029 * - ADDR (Address sent) is cleared by software sequence: a read operation to
1030 * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
1031 * I2C_SR2 register ((void)(I2Cx->SR2)).
1032 * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
1033 * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
1034 * register (I2C_SendData()).
1035 * @retval None
1036 */
1037 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
1038 {
1039 uint32_t flagpos = 0;
1040 /* Check the parameters */
1041 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
1042 assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
1043 /* Get the I2C flag position */
1044 flagpos = I2C_FLAG & FLAG_Mask;
1045 /* Clear the selected I2C flag */
1046 I2Cx->SR1 = (uint16_t)~flagpos;
1047 }
1048  
1049 /**
1050 * @brief Checks whether the specified I2C interrupt has occurred or not.
1051 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
1052 * @param I2C_IT: specifies the interrupt source to check.
1053 * This parameter can be one of the following values:
1054 * @arg I2C_IT_SMBALERT: SMBus Alert flag
1055 * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
1056 * @arg I2C_IT_PECERR: PEC error in reception flag
1057 * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
1058 * @arg I2C_IT_AF: Acknowledge failure flag
1059 * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
1060 * @arg I2C_IT_BERR: Bus error flag
1061 * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
1062 * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
1063 * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
1064 * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
1065 * @arg I2C_IT_BTF: Byte transfer finished flag
1066 * @arg I2C_IT_ADDR: Address sent flag (Master mode) “ADSL”
1067 * Address matched flag (Slave mode)”ENDAD”
1068 * @arg I2C_IT_SB: Start bit flag (Master mode)
1069 * @retval The new state of I2C_IT (SET or RESET).
1070 */
1071 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
1072 {
1073 ITStatus bitstatus = RESET;
1074 uint32_t enablestatus = 0;
1075 /* Check the parameters */
1076 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
1077 assert_param(IS_I2C_GET_IT(I2C_IT));
1078 /* Check if the interrupt source is enabled or not */
1079 enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
1080 /* Get bit[23:0] of the flag */
1081 I2C_IT &= FLAG_Mask;
1082 /* Check the status of the specified I2C flag */
1083 if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
1084 {
1085 /* I2C_IT is set */
1086 bitstatus = SET;
1087 }
1088 else
1089 {
1090 /* I2C_IT is reset */
1091 bitstatus = RESET;
1092 }
1093 /* Return the I2C_IT status */
1094 return bitstatus;
1095 }
1096  
1097 /**
1098 * @brief Clears the I2Cx’s interrupt pending bits.
1099 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
1100 * @param I2C_IT: specifies the interrupt pending bit to clear.
1101 * This parameter can be any combination of the following values:
1102 * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
1103 * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
1104 * @arg I2C_IT_PECERR: PEC error in reception interrupt
1105 * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
1106 * @arg I2C_IT_AF: Acknowledge failure interrupt
1107 * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
1108 * @arg I2C_IT_BERR: Bus error interrupt
1109 *
1110 * @note
1111 * - STOPF (STOP detection) is cleared by software sequence: a read operation
1112 * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
1113 * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
1114 * - ADD10 (10-bit header sent) is cleared by software sequence: a read
1115 * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
1116 * byte of the address in I2C_DR register.
1117 * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
1118 * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
1119 * read/write to I2C_DR register (I2C_SendData()).
1120 * - ADDR (Address sent) is cleared by software sequence: a read operation to
1121 * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
1122 * I2C_SR2 register ((void)(I2Cx->SR2)).
1123 * - SB (Start Bit) is cleared by software sequence: a read operation to
1124 * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
1125 * I2C_DR register (I2C_SendData()).
1126 * @retval None
1127 */
1128 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
1129 {
1130 uint32_t flagpos = 0;
1131 /* Check the parameters */
1132 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
1133 assert_param(IS_I2C_CLEAR_IT(I2C_IT));
1134 /* Get the I2C flag position */
1135 flagpos = I2C_IT & FLAG_Mask;
1136 /* Clear the selected I2C flag */
1137 I2Cx->SR1 = (uint16_t)~flagpos;
1138 }
1139  
1140 /**
1141 * @}
1142 */
1143  
1144 /**
1145 * @}
1146 */
1147  
1148 /**
1149 * @}
1150 */
1151  
1152 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/