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/** |
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****************************************************************************** |
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* @file stm32f10x_sdio.c |
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* @author MCD Application Team |
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* @version V3.1.0 |
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* @date 06/19/2009 |
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* @brief This file provides all the SDIO firmware functions. |
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****************************************************************************** |
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* @copy |
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* |
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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* |
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> |
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*/ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f10x_sdio.h" |
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#include "stm32f10x_rcc.h" |
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/** @addtogroup STM32F10x_StdPeriph_Driver |
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* @{ |
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*/ |
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/** @defgroup SDIO |
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* @brief SDIO driver modules |
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* @{ |
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*/ |
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/** @defgroup SDIO_Private_TypesDefinitions |
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* @{ |
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*/ |
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/* ------------ SDIO registers bit address in the alias region ----------- */ |
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#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) |
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/* --- CLKCR Register ---*/ |
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/* Alias word address of CLKEN bit */ |
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#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) |
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#define CLKEN_BitNumber 0x08 |
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#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) |
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/* --- CMD Register ---*/ |
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/* Alias word address of SDIOSUSPEND bit */ |
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#define CMD_OFFSET (SDIO_OFFSET + 0x0C) |
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#define SDIOSUSPEND_BitNumber 0x0B |
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#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) |
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/* Alias word address of ENCMDCOMPL bit */ |
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#define ENCMDCOMPL_BitNumber 0x0C |
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#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) |
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/* Alias word address of NIEN bit */ |
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#define NIEN_BitNumber 0x0D |
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#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) |
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/* Alias word address of ATACMD bit */ |
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#define ATACMD_BitNumber 0x0E |
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#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) |
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/* --- DCTRL Register ---*/ |
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/* Alias word address of DMAEN bit */ |
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#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) |
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#define DMAEN_BitNumber 0x03 |
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#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) |
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/* Alias word address of RWSTART bit */ |
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#define RWSTART_BitNumber 0x08 |
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#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) |
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/* Alias word address of RWSTOP bit */ |
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#define RWSTOP_BitNumber 0x09 |
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#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) |
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/* Alias word address of RWMOD bit */ |
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#define RWMOD_BitNumber 0x0A |
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#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) |
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/* Alias word address of SDIOEN bit */ |
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#define SDIOEN_BitNumber 0x0B |
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#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) |
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/* ---------------------- SDIO registers bit mask ------------------------ */ |
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/* --- CLKCR Register ---*/ |
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/* CLKCR register clear mask */ |
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#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) |
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/* --- PWRCTRL Register ---*/ |
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/* SDIO PWRCTRL Mask */ |
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#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) |
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/* --- DCTRL Register ---*/ |
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/* SDIO DCTRL Clear Mask */ |
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#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) |
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/* --- CMD Register ---*/ |
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/* CMD Register clear mask */ |
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#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) |
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/* SDIO RESP Registers Address */ |
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#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) |
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/** |
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* @} |
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*/ |
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/** @defgroup SDIO_Private_Defines |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup SDIO_Private_Macros |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup SDIO_Private_Variables |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup SDIO_Private_FunctionPrototypes |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @defgroup SDIO_Private_Functions |
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* @{ |
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*/ |
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/** |
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* @brief Deinitializes the SDIO peripheral registers to their default reset values. |
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* @param None |
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* @retval None |
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*/ |
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void SDIO_DeInit(void) |
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{ |
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SDIO->POWER = 0x00000000; |
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SDIO->CLKCR = 0x00000000; |
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SDIO->ARG = 0x00000000; |
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SDIO->CMD = 0x00000000; |
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SDIO->DTIMER = 0x00000000; |
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SDIO->DLEN = 0x00000000; |
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SDIO->DCTRL = 0x00000000; |
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SDIO->ICR = 0x00C007FF; |
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SDIO->MASK = 0x00000000; |
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} |
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/** |
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* @brief Initializes the SDIO peripheral according to the specified |
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* parameters in the SDIO_InitStruct. |
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* @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure |
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* that contains the configuration information for the SDIO peripheral. |
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* @retval None |
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*/ |
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void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) |
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{ |
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uint32_t tmpreg = 0; |
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/* Check the parameters */ |
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assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); |
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assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); |
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assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); |
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assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); |
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assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); |
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/*---------------------------- SDIO CLKCR Configuration ------------------------*/ |
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/* Get the SDIO CLKCR value */ |
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tmpreg = SDIO->CLKCR; |
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/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ |
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tmpreg &= CLKCR_CLEAR_MASK; |
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/* Set CLKDIV bits according to SDIO_ClockDiv value */ |
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/* Set PWRSAV bit according to SDIO_ClockPowerSave value */ |
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/* Set BYPASS bit according to SDIO_ClockBypass value */ |
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/* Set WIDBUS bits according to SDIO_BusWide value */ |
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/* Set NEGEDGE bits according to SDIO_ClockEdge value */ |
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/* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ |
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tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | |
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SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | |
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SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); |
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/* Write to SDIO CLKCR */ |
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SDIO->CLKCR = tmpreg; |
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} |
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/** |
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* @brief Fills each SDIO_InitStruct member with its default value. |
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* @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which |
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* will be initialized. |
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* @retval None |
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*/ |
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void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) |
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{ |
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/* SDIO_InitStruct members default value */ |
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SDIO_InitStruct->SDIO_ClockDiv = 0x00; |
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SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; |
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SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; |
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SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; |
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SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; |
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SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; |
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} |
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/** |
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* @brief Enables or disables the SDIO Clock. |
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* @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. |
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* @retval None |
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*/ |
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void SDIO_ClockCmd(FunctionalState NewState) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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*(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; |
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} |
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/** |
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* @brief Sets the power status of the controller. |
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* @param SDIO_PowerState: new state of the Power state. |
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* This parameter can be one of the following values: |
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* @arg SDIO_PowerState_OFF |
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* @arg SDIO_PowerState_ON |
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* @retval None |
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*/ |
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void SDIO_SetPowerState(uint32_t SDIO_PowerState) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); |
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SDIO->POWER &= PWR_PWRCTRL_MASK; |
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SDIO->POWER |= SDIO_PowerState; |
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} |
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/** |
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* @brief Gets the power status of the controller. |
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* @param None |
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* @retval Power status of the controller. The returned value can |
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* be one of the following: |
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* - 0x00: Power OFF |
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* - 0x02: Power UP |
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* - 0x03: Power ON |
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*/ |
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uint32_t SDIO_GetPowerState(void) |
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{ |
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return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); |
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} |
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/** |
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* @brief Enables or disables the SDIO interrupts. |
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* @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. |
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* This parameter can be one or a combination of the following values: |
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* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
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* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
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* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
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* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
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* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
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* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
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* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
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* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
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* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
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* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
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* bus mode interrupt |
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* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
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* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
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* @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
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* @arg SDIO_IT_RXACT: Data receive in progress interrupt |
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* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
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* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
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* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
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* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
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* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
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* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
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* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
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* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
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* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
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* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
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* @param NewState: new state of the specified SDIO interrupts. |
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* This parameter can be: ENABLE or DISABLE. |
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* @retval None |
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*/ |
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void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_SDIO_IT(SDIO_IT)); |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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if (NewState != DISABLE) |
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{ |
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/* Enable the SDIO interrupts */ |
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SDIO->MASK |= SDIO_IT; |
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} |
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else |
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{ |
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/* Disable the SDIO interrupts */ |
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SDIO->MASK &= ~SDIO_IT; |
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} |
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} |
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/** |
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* @brief Enables or disables the SDIO DMA request. |
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* @param NewState: new state of the selected SDIO DMA request. |
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* This parameter can be: ENABLE or DISABLE. |
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* @retval None |
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*/ |
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void SDIO_DMACmd(FunctionalState NewState) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; |
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} |
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/** |
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* @brief Initializes the SDIO Command according to the specified |
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* parameters in the SDIO_CmdInitStruct and send the command. |
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* @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef |
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* structure that contains the configuration information for the SDIO command. |
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* @retval None |
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*/ |
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void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) |
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{ |
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uint32_t tmpreg = 0; |
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/* Check the parameters */ |
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assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); |
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assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); |
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assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); |
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assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); |
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/*---------------------------- SDIO ARG Configuration ------------------------*/ |
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/* Set the SDIO Argument value */ |
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SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; |
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/*---------------------------- SDIO CMD Configuration ------------------------*/ |
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/* Get the SDIO CMD value */ |
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|
361 |
tmpreg = SDIO->CMD; |
|
|
362 |
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ |
|
|
363 |
tmpreg &= CMD_CLEAR_MASK; |
|
|
364 |
/* Set CMDINDEX bits according to SDIO_CmdIndex value */ |
|
|
365 |
/* Set WAITRESP bits according to SDIO_Response value */ |
|
|
366 |
/* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ |
|
|
367 |
/* Set CPSMEN bits according to SDIO_CPSM value */ |
|
|
368 |
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response |
|
|
369 |
| SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; |
|
|
370 |
|
|
|
371 |
/* Write to SDIO CMD */ |
|
|
372 |
SDIO->CMD = tmpreg; |
|
|
373 |
} |
|
|
374 |
|
|
|
375 |
/** |
|
|
376 |
* @brief Fills each SDIO_CmdInitStruct member with its default value. |
|
|
377 |
* @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef |
|
|
378 |
* structure which will be initialized. |
|
|
379 |
* @retval None |
|
|
380 |
*/ |
|
|
381 |
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) |
|
|
382 |
{ |
|
|
383 |
/* SDIO_CmdInitStruct members default value */ |
|
|
384 |
SDIO_CmdInitStruct->SDIO_Argument = 0x00; |
|
|
385 |
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; |
|
|
386 |
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; |
|
|
387 |
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; |
|
|
388 |
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; |
|
|
389 |
} |
|
|
390 |
|
|
|
391 |
/** |
|
|
392 |
* @brief Returns command index of last command for which response received. |
|
|
393 |
* @param None |
|
|
394 |
* @retval Returns the command index of the last command response received. |
|
|
395 |
*/ |
|
|
396 |
uint8_t SDIO_GetCommandResponse(void) |
|
|
397 |
{ |
|
|
398 |
return (uint8_t)(SDIO->RESPCMD); |
|
|
399 |
} |
|
|
400 |
|
|
|
401 |
/** |
|
|
402 |
* @brief Returns response received from the card for the last command. |
|
|
403 |
* @param SDIO_RESP: Specifies the SDIO response register. |
|
|
404 |
* This parameter can be one of the following values: |
|
|
405 |
* @arg SDIO_RESP1: Response Register 1 |
|
|
406 |
* @arg SDIO_RESP2: Response Register 2 |
|
|
407 |
* @arg SDIO_RESP3: Response Register 3 |
|
|
408 |
* @arg SDIO_RESP4: Response Register 4 |
|
|
409 |
* @retval The Corresponding response register value. |
|
|
410 |
*/ |
|
|
411 |
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) |
|
|
412 |
{ |
|
|
413 |
__IO uint32_t tmp = 0; |
|
|
414 |
|
|
|
415 |
/* Check the parameters */ |
|
|
416 |
assert_param(IS_SDIO_RESP(SDIO_RESP)); |
|
|
417 |
|
|
|
418 |
tmp = SDIO_RESP_ADDR + SDIO_RESP; |
|
|
419 |
|
|
|
420 |
return (*(__IO uint32_t *) tmp); |
|
|
421 |
} |
|
|
422 |
|
|
|
423 |
/** |
|
|
424 |
* @brief Initializes the SDIO data path according to the specified |
|
|
425 |
* parameters in the SDIO_DataInitStruct. |
|
|
426 |
* @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that |
|
|
427 |
* contains the configuration information for the SDIO command. |
|
|
428 |
* @retval None |
|
|
429 |
*/ |
|
|
430 |
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) |
|
|
431 |
{ |
|
|
432 |
uint32_t tmpreg = 0; |
|
|
433 |
|
|
|
434 |
/* Check the parameters */ |
|
|
435 |
assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); |
|
|
436 |
assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); |
|
|
437 |
assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); |
|
|
438 |
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); |
|
|
439 |
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); |
|
|
440 |
|
|
|
441 |
/*---------------------------- SDIO DTIMER Configuration ---------------------*/ |
|
|
442 |
/* Set the SDIO Data TimeOut value */ |
|
|
443 |
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; |
|
|
444 |
|
|
|
445 |
/*---------------------------- SDIO DLEN Configuration -----------------------*/ |
|
|
446 |
/* Set the SDIO DataLength value */ |
|
|
447 |
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; |
|
|
448 |
|
|
|
449 |
/*---------------------------- SDIO DCTRL Configuration ----------------------*/ |
|
|
450 |
/* Get the SDIO DCTRL value */ |
|
|
451 |
tmpreg = SDIO->DCTRL; |
|
|
452 |
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ |
|
|
453 |
tmpreg &= DCTRL_CLEAR_MASK; |
|
|
454 |
/* Set DEN bit according to SDIO_DPSM value */ |
|
|
455 |
/* Set DTMODE bit according to SDIO_TransferMode value */ |
|
|
456 |
/* Set DTDIR bit according to SDIO_TransferDir value */ |
|
|
457 |
/* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ |
|
|
458 |
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir |
|
|
459 |
| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; |
|
|
460 |
|
|
|
461 |
/* Write to SDIO DCTRL */ |
|
|
462 |
SDIO->DCTRL = tmpreg; |
|
|
463 |
} |
|
|
464 |
|
|
|
465 |
/** |
|
|
466 |
* @brief Fills each SDIO_DataInitStruct member with its default value. |
|
|
467 |
* @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which |
|
|
468 |
* will be initialized. |
|
|
469 |
* @retval None |
|
|
470 |
*/ |
|
|
471 |
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) |
|
|
472 |
{ |
|
|
473 |
/* SDIO_DataInitStruct members default value */ |
|
|
474 |
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; |
|
|
475 |
SDIO_DataInitStruct->SDIO_DataLength = 0x00; |
|
|
476 |
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; |
|
|
477 |
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; |
|
|
478 |
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; |
|
|
479 |
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; |
|
|
480 |
} |
|
|
481 |
|
|
|
482 |
/** |
|
|
483 |
* @brief Returns number of remaining data bytes to be transferred. |
|
|
484 |
* @param None |
|
|
485 |
* @retval Number of remaining data bytes to be transferred |
|
|
486 |
*/ |
|
|
487 |
uint32_t SDIO_GetDataCounter(void) |
|
|
488 |
{ |
|
|
489 |
return SDIO->DCOUNT; |
|
|
490 |
} |
|
|
491 |
|
|
|
492 |
/** |
|
|
493 |
* @brief Read one data word from Rx FIFO. |
|
|
494 |
* @param None |
|
|
495 |
* @retval Data received |
|
|
496 |
*/ |
|
|
497 |
uint32_t SDIO_ReadData(void) |
|
|
498 |
{ |
|
|
499 |
return SDIO->FIFO; |
|
|
500 |
} |
|
|
501 |
|
|
|
502 |
/** |
|
|
503 |
* @brief Write one data word to Tx FIFO. |
|
|
504 |
* @param Data: 32-bit data word to write. |
|
|
505 |
* @retval None |
|
|
506 |
*/ |
|
|
507 |
void SDIO_WriteData(uint32_t Data) |
|
|
508 |
{ |
|
|
509 |
SDIO->FIFO = Data; |
|
|
510 |
} |
|
|
511 |
|
|
|
512 |
/** |
|
|
513 |
* @brief Returns the number of words left to be written to or read from FIFO. |
|
|
514 |
* @param None |
|
|
515 |
* @retval Remaining number of words. |
|
|
516 |
*/ |
|
|
517 |
uint32_t SDIO_GetFIFOCount(void) |
|
|
518 |
{ |
|
|
519 |
return SDIO->FIFOCNT; |
|
|
520 |
} |
|
|
521 |
|
|
|
522 |
/** |
|
|
523 |
* @brief Starts the SD I/O Read Wait operation. |
|
|
524 |
* @param NewState: new state of the Start SDIO Read Wait operation. |
|
|
525 |
* This parameter can be: ENABLE or DISABLE. |
|
|
526 |
* @retval None |
|
|
527 |
*/ |
|
|
528 |
void SDIO_StartSDIOReadWait(FunctionalState NewState) |
|
|
529 |
{ |
|
|
530 |
/* Check the parameters */ |
|
|
531 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
532 |
|
|
|
533 |
*(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; |
|
|
534 |
} |
|
|
535 |
|
|
|
536 |
/** |
|
|
537 |
* @brief Stops the SD I/O Read Wait operation. |
|
|
538 |
* @param NewState: new state of the Stop SDIO Read Wait operation. |
|
|
539 |
* This parameter can be: ENABLE or DISABLE. |
|
|
540 |
* @retval None |
|
|
541 |
*/ |
|
|
542 |
void SDIO_StopSDIOReadWait(FunctionalState NewState) |
|
|
543 |
{ |
|
|
544 |
/* Check the parameters */ |
|
|
545 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
546 |
|
|
|
547 |
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; |
|
|
548 |
} |
|
|
549 |
|
|
|
550 |
/** |
|
|
551 |
* @brief Sets one of the two options of inserting read wait interval. |
|
|
552 |
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. |
|
|
553 |
* This parametre can be: |
|
|
554 |
* @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK |
|
|
555 |
* @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 |
|
|
556 |
* @retval None |
|
|
557 |
*/ |
|
|
558 |
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) |
|
|
559 |
{ |
|
|
560 |
/* Check the parameters */ |
|
|
561 |
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); |
|
|
562 |
|
|
|
563 |
*(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; |
|
|
564 |
} |
|
|
565 |
|
|
|
566 |
/** |
|
|
567 |
* @brief Enables or disables the SD I/O Mode Operation. |
|
|
568 |
* @param NewState: new state of SDIO specific operation. |
|
|
569 |
* This parameter can be: ENABLE or DISABLE. |
|
|
570 |
* @retval None |
|
|
571 |
*/ |
|
|
572 |
void SDIO_SetSDIOOperation(FunctionalState NewState) |
|
|
573 |
{ |
|
|
574 |
/* Check the parameters */ |
|
|
575 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
576 |
|
|
|
577 |
*(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; |
|
|
578 |
} |
|
|
579 |
|
|
|
580 |
/** |
|
|
581 |
* @brief Enables or disables the SD I/O Mode suspend command sending. |
|
|
582 |
* @param NewState: new state of the SD I/O Mode suspend command. |
|
|
583 |
* This parameter can be: ENABLE or DISABLE. |
|
|
584 |
* @retval None |
|
|
585 |
*/ |
|
|
586 |
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) |
|
|
587 |
{ |
|
|
588 |
/* Check the parameters */ |
|
|
589 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
590 |
|
|
|
591 |
*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; |
|
|
592 |
} |
|
|
593 |
|
|
|
594 |
/** |
|
|
595 |
* @brief Enables or disables the command completion signal. |
|
|
596 |
* @param NewState: new state of command completion signal. |
|
|
597 |
* This parameter can be: ENABLE or DISABLE. |
|
|
598 |
* @retval None |
|
|
599 |
*/ |
|
|
600 |
void SDIO_CommandCompletionCmd(FunctionalState NewState) |
|
|
601 |
{ |
|
|
602 |
/* Check the parameters */ |
|
|
603 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
604 |
|
|
|
605 |
*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; |
|
|
606 |
} |
|
|
607 |
|
|
|
608 |
/** |
|
|
609 |
* @brief Enables or disables the CE-ATA interrupt. |
|
|
610 |
* @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. |
|
|
611 |
* @retval None |
|
|
612 |
*/ |
|
|
613 |
void SDIO_CEATAITCmd(FunctionalState NewState) |
|
|
614 |
{ |
|
|
615 |
/* Check the parameters */ |
|
|
616 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
617 |
|
|
|
618 |
*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); |
|
|
619 |
} |
|
|
620 |
|
|
|
621 |
/** |
|
|
622 |
* @brief Sends CE-ATA command (CMD61). |
|
|
623 |
* @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. |
|
|
624 |
* @retval None |
|
|
625 |
*/ |
|
|
626 |
void SDIO_SendCEATACmd(FunctionalState NewState) |
|
|
627 |
{ |
|
|
628 |
/* Check the parameters */ |
|
|
629 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
|
|
630 |
|
|
|
631 |
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; |
|
|
632 |
} |
|
|
633 |
|
|
|
634 |
/** |
|
|
635 |
* @brief Checks whether the specified SDIO flag is set or not. |
|
|
636 |
* @param SDIO_FLAG: specifies the flag to check. |
|
|
637 |
* This parameter can be one of the following values: |
|
|
638 |
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|
|
639 |
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|
|
640 |
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
|
|
641 |
* @arg SDIO_FLAG_DTIMEOUT: Data timeout |
|
|
642 |
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
|
|
643 |
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
|
|
644 |
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
|
|
645 |
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
|
|
646 |
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
|
|
647 |
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide |
|
|
648 |
* bus mode. |
|
|
649 |
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|
|
650 |
* @arg SDIO_FLAG_CMDACT: Command transfer in progress |
|
|
651 |
* @arg SDIO_FLAG_TXACT: Data transmit in progress |
|
|
652 |
* @arg SDIO_FLAG_RXACT: Data receive in progress |
|
|
653 |
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
|
|
654 |
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
|
|
655 |
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
|
|
656 |
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
|
|
657 |
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
|
|
658 |
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
|
|
659 |
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
|
|
660 |
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
|
|
661 |
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
|
|
662 |
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
|
|
663 |
* @retval The new state of SDIO_FLAG (SET or RESET). |
|
|
664 |
*/ |
|
|
665 |
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) |
|
|
666 |
{ |
|
|
667 |
FlagStatus bitstatus = RESET; |
|
|
668 |
|
|
|
669 |
/* Check the parameters */ |
|
|
670 |
assert_param(IS_SDIO_FLAG(SDIO_FLAG)); |
|
|
671 |
|
|
|
672 |
if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) |
|
|
673 |
{ |
|
|
674 |
bitstatus = SET; |
|
|
675 |
} |
|
|
676 |
else |
|
|
677 |
{ |
|
|
678 |
bitstatus = RESET; |
|
|
679 |
} |
|
|
680 |
return bitstatus; |
|
|
681 |
} |
|
|
682 |
|
|
|
683 |
/** |
|
|
684 |
* @brief Clears the SDIO's pending flags. |
|
|
685 |
* @param SDIO_FLAG: specifies the flag to clear. |
|
|
686 |
* This parameter can be one or a combination of the following values: |
|
|
687 |
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
|
|
688 |
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
|
|
689 |
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
|
|
690 |
* @arg SDIO_FLAG_DTIMEOUT: Data timeout |
|
|
691 |
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
|
|
692 |
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
|
|
693 |
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
|
|
694 |
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
|
|
695 |
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
|
|
696 |
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide |
|
|
697 |
* bus mode |
|
|
698 |
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
|
|
699 |
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
|
|
700 |
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
|
|
701 |
* @retval None |
|
|
702 |
*/ |
|
|
703 |
void SDIO_ClearFlag(uint32_t SDIO_FLAG) |
|
|
704 |
{ |
|
|
705 |
/* Check the parameters */ |
|
|
706 |
assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); |
|
|
707 |
|
|
|
708 |
SDIO->ICR = SDIO_FLAG; |
|
|
709 |
} |
|
|
710 |
|
|
|
711 |
/** |
|
|
712 |
* @brief Checks whether the specified SDIO interrupt has occurred or not. |
|
|
713 |
* @param SDIO_IT: specifies the SDIO interrupt source to check. |
|
|
714 |
* This parameter can be one of the following values: |
|
|
715 |
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|
|
716 |
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|
|
717 |
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|
|
718 |
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|
|
719 |
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|
|
720 |
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|
|
721 |
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|
|
722 |
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|
|
723 |
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
|
|
724 |
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
|
|
725 |
* bus mode interrupt |
|
|
726 |
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
|
|
727 |
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
|
|
728 |
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
|
|
729 |
* @arg SDIO_IT_RXACT: Data receive in progress interrupt |
|
|
730 |
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
|
|
731 |
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
|
|
732 |
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
|
|
733 |
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
|
|
734 |
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
|
|
735 |
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
|
|
736 |
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
|
|
737 |
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
|
|
738 |
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
|
|
739 |
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
|
|
740 |
* @retval The new state of SDIO_IT (SET or RESET). |
|
|
741 |
*/ |
|
|
742 |
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) |
|
|
743 |
{ |
|
|
744 |
ITStatus bitstatus = RESET; |
|
|
745 |
|
|
|
746 |
/* Check the parameters */ |
|
|
747 |
assert_param(IS_SDIO_GET_IT(SDIO_IT)); |
|
|
748 |
if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) |
|
|
749 |
{ |
|
|
750 |
bitstatus = SET; |
|
|
751 |
} |
|
|
752 |
else |
|
|
753 |
{ |
|
|
754 |
bitstatus = RESET; |
|
|
755 |
} |
|
|
756 |
return bitstatus; |
|
|
757 |
} |
|
|
758 |
|
|
|
759 |
/** |
|
|
760 |
* @brief Clears the SDIOs interrupt pending bits. |
|
|
761 |
* @param SDIO_IT: specifies the interrupt pending bit to clear. |
|
|
762 |
* This parameter can be one or a combination of the following values: |
|
|
763 |
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
|
|
764 |
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
|
|
765 |
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
|
|
766 |
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
|
|
767 |
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
|
|
768 |
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
|
|
769 |
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
|
|
770 |
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
|
|
771 |
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
|
|
772 |
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
|
|
773 |
* bus mode interrupt |
|
|
774 |
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
|
|
775 |
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 |
|
|
776 |
* @retval None |
|
|
777 |
*/ |
|
|
778 |
void SDIO_ClearITPendingBit(uint32_t SDIO_IT) |
|
|
779 |
{ |
|
|
780 |
/* Check the parameters */ |
|
|
781 |
assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); |
|
|
782 |
|
|
|
783 |
SDIO->ICR = SDIO_IT; |
|
|
784 |
} |
|
|
785 |
|
|
|
786 |
/** |
|
|
787 |
* @} |
|
|
788 |
*/ |
|
|
789 |
|
|
|
790 |
/** |
|
|
791 |
* @} |
|
|
792 |
*/ |
|
|
793 |
|
|
|
794 |
/** |
|
|
795 |
* @} |
|
|
796 |
*/ |
|
|
797 |
|
|
|
798 |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ |