Rev Author Line No. Line
3328 povik 1 /**
2 ******************************************************************************
3 * @file stm32f10x_tim.c
4 * @author MCD Application Team
5 * @version V3.1.0
6 * @date 06/19/2009
7 * @brief This file provides all the TIM firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
19 */
20  
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f10x_tim.h"
23 #include "stm32f10x_rcc.h"
24  
25 /** @addtogroup STM32F10x_StdPeriph_Driver
26 * @{
27 */
28  
29 /** @defgroup TIM
30 * @brief TIM driver modules
31 * @{
32 */
33  
34 /** @defgroup TIM_Private_TypesDefinitions
35 * @{
36 */
37  
38 /**
39 * @}
40 */
41  
42 /** @defgroup TIM_Private_Defines
43 * @{
44 */
45  
46 /* ---------------------- TIM registers bit mask ------------------------ */
47 #define CR1_CEN_Set ((uint16_t)0x0001)
48 #define CR1_CEN_Reset ((uint16_t)0x03FE)
49 #define CR1_UDIS_Set ((uint16_t)0x0002)
50 #define CR1_UDIS_Reset ((uint16_t)0x03FD)
51 #define CR1_URS_Set ((uint16_t)0x0004)
52 #define CR1_URS_Reset ((uint16_t)0x03FB)
53 #define CR1_OPM_Reset ((uint16_t)0x03F7)
54 #define CR1_CounterMode_Mask ((uint16_t)0x038F)
55 #define CR1_ARPE_Set ((uint16_t)0x0080)
56 #define CR1_ARPE_Reset ((uint16_t)0x037F)
57 #define CR1_CKD_Mask ((uint16_t)0x00FF)
58 #define CR2_CCPC_Set ((uint16_t)0x0001)
59 #define CR2_CCPC_Reset ((uint16_t)0xFFFE)
60 #define CR2_CCUS_Set ((uint16_t)0x0004)
61 #define CR2_CCUS_Reset ((uint16_t)0xFFFB)
62 #define CR2_CCDS_Set ((uint16_t)0x0008)
63 #define CR2_CCDS_Reset ((uint16_t)0xFFF7)
64 #define CR2_MMS_Mask ((uint16_t)0xFF8F)
65 #define CR2_TI1S_Set ((uint16_t)0x0080)
66 #define CR2_TI1S_Reset ((uint16_t)0xFF7F)
67 #define CR2_OIS1_Reset ((uint16_t)0x7EFF)
68 #define CR2_OIS1N_Reset ((uint16_t)0x7DFF)
69 #define CR2_OIS2_Reset ((uint16_t)0x7BFF)
70 #define CR2_OIS2N_Reset ((uint16_t)0x77FF)
71 #define CR2_OIS3_Reset ((uint16_t)0x6FFF)
72 #define CR2_OIS3N_Reset ((uint16_t)0x5FFF)
73 #define CR2_OIS4_Reset ((uint16_t)0x3FFF)
74 #define SMCR_SMS_Mask ((uint16_t)0xFFF8)
75 #define SMCR_ETR_Mask ((uint16_t)0x00FF)
76 #define SMCR_TS_Mask ((uint16_t)0xFF8F)
77 #define SMCR_MSM_Reset ((uint16_t)0xFF7F)
78 #define SMCR_ECE_Set ((uint16_t)0x4000)
79 #define CCMR_CC13S_Mask ((uint16_t)0xFFFC)
80 #define CCMR_CC24S_Mask ((uint16_t)0xFCFF)
81 #define CCMR_TI13Direct_Set ((uint16_t)0x0001)
82 #define CCMR_TI24Direct_Set ((uint16_t)0x0100)
83 #define CCMR_OC13FE_Reset ((uint16_t)0xFFFB)
84 #define CCMR_OC24FE_Reset ((uint16_t)0xFBFF)
85 #define CCMR_OC13PE_Reset ((uint16_t)0xFFF7)
86 #define CCMR_OC24PE_Reset ((uint16_t)0xF7FF)
87 #define CCMR_OC13M_Mask ((uint16_t)0xFF8F)
88 #define CCMR_OC24M_Mask ((uint16_t)0x8FFF)
89 #define CCMR_OC13CE_Reset ((uint16_t)0xFF7F)
90 #define CCMR_OC24CE_Reset ((uint16_t)0x7FFF)
91 #define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3)
92 #define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF)
93 #define CCMR_IC13F_Mask ((uint16_t)0xFF0F)
94 #define CCMR_IC24F_Mask ((uint16_t)0x0FFF)
95 #define CCMR_Offset ((uint16_t)0x0018)
96 #define CCER_CCE_Set ((uint16_t)0x0001)
97 #define CCER_CCNE_Set ((uint16_t)0x0004)
98 #define CCER_CC1P_Reset ((uint16_t)0xFFFD)
99 #define CCER_CC2P_Reset ((uint16_t)0xFFDF)
100 #define CCER_CC3P_Reset ((uint16_t)0xFDFF)
101 #define CCER_CC4P_Reset ((uint16_t)0xDFFF)
102 #define CCER_CC1NP_Reset ((uint16_t)0xFFF7)
103 #define CCER_CC2NP_Reset ((uint16_t)0xFF7F)
104 #define CCER_CC3NP_Reset ((uint16_t)0xF7FF)
105 #define CCER_CC1E_Set ((uint16_t)0x0001)
106 #define CCER_CC1E_Reset ((uint16_t)0xFFFE)
107 #define CCER_CC1NE_Reset ((uint16_t)0xFFFB)
108 #define CCER_CC2E_Set ((uint16_t)0x0010)
109 #define CCER_CC2E_Reset ((uint16_t)0xFFEF)
110 #define CCER_CC2NE_Reset ((uint16_t)0xFFBF)
111 #define CCER_CC3E_Set ((uint16_t)0x0100)
112 #define CCER_CC3E_Reset ((uint16_t)0xFEFF)
113 #define CCER_CC3NE_Reset ((uint16_t)0xFBFF)
114 #define CCER_CC4E_Set ((uint16_t)0x1000)
115 #define CCER_CC4E_Reset ((uint16_t)0xEFFF)
116 #define BDTR_MOE_Set ((uint16_t)0x8000)
117 #define BDTR_MOE_Reset ((uint16_t)0x7FFF)
118 /**
119 * @}
120 */
121  
122 /** @defgroup TIM_Private_Macros
123 * @{
124 */
125  
126 /**
127 * @}
128 */
129  
130 /** @defgroup TIM_Private_Variables
131 * @{
132 */
133  
134 /**
135 * @}
136 */
137  
138 /** @defgroup TIM_Private_FunctionPrototypes
139 * @{
140 */
141  
142 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
143 uint16_t TIM_ICFilter);
144 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
145 uint16_t TIM_ICFilter);
146 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
147 uint16_t TIM_ICFilter);
148 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
149 uint16_t TIM_ICFilter);
150 /**
151 * @}
152 */
153  
154 /** @defgroup TIM_Private_Macros
155 * @{
156 */
157  
158 /**
159 * @}
160 */
161  
162 /** @defgroup TIM_Private_Variables
163 * @{
164 */
165  
166 /**
167 * @}
168 */
169  
170 /** @defgroup TIM_Private_FunctionPrototypes
171 * @{
172 */
173  
174 /**
175 * @}
176 */
177  
178 /** @defgroup TIM_Private_Functions
179 * @{
180 */
181  
182 /**
183 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
184 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
185 * @retval None
186 */
187 void TIM_DeInit(TIM_TypeDef* TIMx)
188 {
189 /* Check the parameters */
190 assert_param(IS_TIM_ALL_PERIPH(TIMx));
191  
192 if (TIMx == TIM1)
193 {
194 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
195 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
196 }
197 else if (TIMx == TIM2)
198 {
199 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
200 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
201 }
202 else if (TIMx == TIM3)
203 {
204 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
205 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
206 }
207 else if (TIMx == TIM4)
208 {
209 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
210 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
211 }
212 else if (TIMx == TIM5)
213 {
214 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
215 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
216 }
217 else if (TIMx == TIM6)
218 {
219 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
220 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
221 }
222 else if (TIMx == TIM7)
223 {
224 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
225 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
226 }
227 else
228 {
229 if (TIMx == TIM8)
230 {
231 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
232 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
233 }
234 }
235 }
236  
237 /**
238 * @brief Initializes the TIMx Time Base Unit peripheral according to
239 * the specified parameters in the TIM_TimeBaseInitStruct.
240 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
241 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
242 * structure that contains the configuration information for the specified TIM peripheral.
243 * @retval None
244 */
245 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
246 {
247 /* Check the parameters */
248 assert_param(IS_TIM_123458_PERIPH(TIMx));
249 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
250 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
251 /* Select the Counter Mode and set the clock division */
252 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
253 TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision |
254 TIM_TimeBaseInitStruct->TIM_CounterMode;
255  
256 /* Set the Autoreload value */
257 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
258  
259 /* Set the Prescaler value */
260 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
261  
262 if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE))
263 {
264 /* Set the Repetition Counter value */
265 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
266 }
267  
268 /* Generate an update event to reload the Prescaler value immediatly */
269 TIMx->EGR = TIM_PSCReloadMode_Immediate;
270 }
271  
272 /**
273 * @brief Initializes the TIMx Channel1 according to the specified
274 * parameters in the TIM_OCInitStruct.
275 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
276 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
277 * that contains the configuration information for the specified TIM peripheral.
278 * @retval None
279 */
280 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
281 {
282 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
283  
284 /* Check the parameters */
285 assert_param(IS_TIM_123458_PERIPH(TIMx));
286 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
287 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
288 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
289 /* Disable the Channel 1: Reset the CC1E Bit */
290 TIMx->CCER &= CCER_CC1E_Reset;
291  
292 /* Get the TIMx CCER register value */
293 tmpccer = TIMx->CCER;
294 /* Get the TIMx CR2 register value */
295 tmpcr2 = TIMx->CR2;
296  
297 /* Get the TIMx CCMR1 register value */
298 tmpccmrx = TIMx->CCMR1;
299  
300 /* Reset the Output Compare Mode Bits */
301 tmpccmrx &= CCMR_OC13M_Mask;
302  
303 /* Select the Output Compare Mode */
304 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
305  
306 /* Reset the Output Polarity level */
307 tmpccer &= CCER_CC1P_Reset;
308 /* Set the Output Compare Polarity */
309 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
310  
311 /* Set the Output State */
312 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
313  
314 /* Set the Capture Compare Register value */
315 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
316  
317 if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
318 {
319 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
320 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
321 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
322 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
323  
324 /* Reset the Output N Polarity level */
325 tmpccer &= CCER_CC1NP_Reset;
326 /* Set the Output N Polarity */
327 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
328 /* Reset the Output N State */
329 tmpccer &= CCER_CC1NE_Reset;
330  
331 /* Set the Output N State */
332 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
333 /* Reset the Ouput Compare and Output Compare N IDLE State */
334 tmpcr2 &= CR2_OIS1_Reset;
335 tmpcr2 &= CR2_OIS1N_Reset;
336 /* Set the Output Idle state */
337 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
338 /* Set the Output N Idle state */
339 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
340 }
341 /* Write to TIMx CR2 */
342 TIMx->CR2 = tmpcr2;
343  
344 /* Write to TIMx CCMR1 */
345 TIMx->CCMR1 = tmpccmrx;
346  
347 /* Write to TIMx CCER */
348 TIMx->CCER = tmpccer;
349 }
350  
351 /**
352 * @brief Initializes the TIMx Channel2 according to the specified
353 * parameters in the TIM_OCInitStruct.
354 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
355 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
356 * that contains the configuration information for the specified TIM peripheral.
357 * @retval None
358 */
359 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
360 {
361 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
362  
363 /* Check the parameters */
364 assert_param(IS_TIM_123458_PERIPH(TIMx));
365 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
366 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
367 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
368 /* Disable the Channel 2: Reset the CC2E Bit */
369 TIMx->CCER &= CCER_CC2E_Reset;
370  
371 /* Get the TIMx CCER register value */
372 tmpccer = TIMx->CCER;
373 /* Get the TIMx CR2 register value */
374 tmpcr2 = TIMx->CR2;
375  
376 /* Get the TIMx CCMR1 register value */
377 tmpccmrx = TIMx->CCMR1;
378  
379 /* Reset the Output Compare Mode Bits */
380 tmpccmrx &= CCMR_OC24M_Mask;
381  
382 /* Select the Output Compare Mode */
383 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
384  
385 /* Reset the Output Polarity level */
386 tmpccer &= CCER_CC2P_Reset;
387 /* Set the Output Compare Polarity */
388 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
389  
390 /* Set the Output State */
391 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
392  
393 /* Set the Capture Compare Register value */
394 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
395  
396 if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
397 {
398 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
399 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
400 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
401 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
402  
403 /* Reset the Output N Polarity level */
404 tmpccer &= CCER_CC2NP_Reset;
405 /* Set the Output N Polarity */
406 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
407 /* Reset the Output N State */
408 tmpccer &= CCER_CC2NE_Reset;
409  
410 /* Set the Output N State */
411 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
412 /* Reset the Ouput Compare and Output Compare N IDLE State */
413 tmpcr2 &= CR2_OIS2_Reset;
414 tmpcr2 &= CR2_OIS2N_Reset;
415 /* Set the Output Idle state */
416 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
417 /* Set the Output N Idle state */
418 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
419 }
420 /* Write to TIMx CR2 */
421 TIMx->CR2 = tmpcr2;
422  
423 /* Write to TIMx CCMR1 */
424 TIMx->CCMR1 = tmpccmrx;
425  
426 /* Write to TIMx CCER */
427 TIMx->CCER = tmpccer;
428 }
429  
430 /**
431 * @brief Initializes the TIMx Channel3 according to the specified
432 * parameters in the TIM_OCInitStruct.
433 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
434 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
435 * that contains the configuration information for the specified TIM peripheral.
436 * @retval None
437 */
438 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
439 {
440 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
441  
442 /* Check the parameters */
443 assert_param(IS_TIM_123458_PERIPH(TIMx));
444 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
445 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
446 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
447 /* Disable the Channel 2: Reset the CC2E Bit */
448 TIMx->CCER &= CCER_CC3E_Reset;
449  
450 /* Get the TIMx CCER register value */
451 tmpccer = TIMx->CCER;
452 /* Get the TIMx CR2 register value */
453 tmpcr2 = TIMx->CR2;
454  
455 /* Get the TIMx CCMR2 register value */
456 tmpccmrx = TIMx->CCMR2;
457  
458 /* Reset the Output Compare Mode Bits */
459 tmpccmrx &= CCMR_OC13M_Mask;
460  
461 /* Select the Output Compare Mode */
462 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
463  
464 /* Reset the Output Polarity level */
465 tmpccer &= CCER_CC3P_Reset;
466 /* Set the Output Compare Polarity */
467 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
468  
469 /* Set the Output State */
470 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
471  
472 /* Set the Capture Compare Register value */
473 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
474  
475 if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
476 {
477 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
478 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
479 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
480 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
481  
482 /* Reset the Output N Polarity level */
483 tmpccer &= CCER_CC3NP_Reset;
484 /* Set the Output N Polarity */
485 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
486 /* Reset the Output N State */
487 tmpccer &= CCER_CC3NE_Reset;
488  
489 /* Set the Output N State */
490 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
491 /* Reset the Ouput Compare and Output Compare N IDLE State */
492 tmpcr2 &= CR2_OIS3_Reset;
493 tmpcr2 &= CR2_OIS3N_Reset;
494 /* Set the Output Idle state */
495 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
496 /* Set the Output N Idle state */
497 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
498 }
499 /* Write to TIMx CR2 */
500 TIMx->CR2 = tmpcr2;
501  
502 /* Write to TIMx CCMR2 */
503 TIMx->CCMR2 = tmpccmrx;
504  
505 /* Write to TIMx CCER */
506 TIMx->CCER = tmpccer;
507 }
508  
509 /**
510 * @brief Initializes the TIMx Channel4 according to the specified
511 * parameters in the TIM_OCInitStruct.
512 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
513 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
514 * that contains the configuration information for the specified TIM peripheral.
515 * @retval None
516 */
517 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
518 {
519 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
520  
521 /* Check the parameters */
522 assert_param(IS_TIM_123458_PERIPH(TIMx));
523 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
524 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
525 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
526 /* Disable the Channel 2: Reset the CC4E Bit */
527 TIMx->CCER &= CCER_CC4E_Reset;
528  
529 /* Get the TIMx CCER register value */
530 tmpccer = TIMx->CCER;
531 /* Get the TIMx CR2 register value */
532 tmpcr2 = TIMx->CR2;
533  
534 /* Get the TIMx CCMR2 register value */
535 tmpccmrx = TIMx->CCMR2;
536  
537 /* Reset the Output Compare Mode Bits */
538 tmpccmrx &= CCMR_OC24M_Mask;
539  
540 /* Select the Output Compare Mode */
541 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
542  
543 /* Reset the Output Polarity level */
544 tmpccer &= CCER_CC4P_Reset;
545 /* Set the Output Compare Polarity */
546 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
547  
548 /* Set the Output State */
549 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
550  
551 /* Set the Capture Compare Register value */
552 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
553  
554 if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
555 {
556 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
557 /* Reset the Ouput Compare IDLE State */
558 tmpcr2 &= CR2_OIS4_Reset;
559 /* Set the Output Idle state */
560 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
561 }
562 /* Write to TIMx CR2 */
563 TIMx->CR2 = tmpcr2;
564  
565 /* Write to TIMx CCMR2 */
566 TIMx->CCMR2 = tmpccmrx;
567  
568 /* Write to TIMx CCER */
569 TIMx->CCER = tmpccer;
570 }
571  
572 /**
573 * @brief Initializes the TIM peripheral according to the specified
574 * parameters in the TIM_ICInitStruct.
575 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
576 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
577 * that contains the configuration information for the specified TIM peripheral.
578 * @retval None
579 */
580 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
581 {
582 /* Check the parameters */
583 assert_param(IS_TIM_123458_PERIPH(TIMx));
584 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
585 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
586 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
587 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
588 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
589  
590 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
591 {
592 /* TI1 Configuration */
593 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
594 TIM_ICInitStruct->TIM_ICSelection,
595 TIM_ICInitStruct->TIM_ICFilter);
596 /* Set the Input Capture Prescaler value */
597 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
598 }
599 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
600 {
601 /* TI2 Configuration */
602 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
603 TIM_ICInitStruct->TIM_ICSelection,
604 TIM_ICInitStruct->TIM_ICFilter);
605 /* Set the Input Capture Prescaler value */
606 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
607 }
608 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
609 {
610 /* TI3 Configuration */
611 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
612 TIM_ICInitStruct->TIM_ICSelection,
613 TIM_ICInitStruct->TIM_ICFilter);
614 /* Set the Input Capture Prescaler value */
615 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
616 }
617 else
618 {
619 /* TI4 Configuration */
620 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
621 TIM_ICInitStruct->TIM_ICSelection,
622 TIM_ICInitStruct->TIM_ICFilter);
623 /* Set the Input Capture Prescaler value */
624 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
625 }
626 }
627  
628 /**
629 * @brief Configures the TIM peripheral according to the specified
630 * parameters in the TIM_ICInitStruct to measure an external PWM signal.
631 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
632 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
633 * that contains the configuration information for the specified TIM peripheral.
634 * @retval None
635 */
636 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
637 {
638 uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
639 uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
640 /* Check the parameters */
641 assert_param(IS_TIM_123458_PERIPH(TIMx));
642 /* Select the Opposite Input Polarity */
643 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
644 {
645 icoppositepolarity = TIM_ICPolarity_Falling;
646 }
647 else
648 {
649 icoppositepolarity = TIM_ICPolarity_Rising;
650 }
651 /* Select the Opposite Input */
652 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
653 {
654 icoppositeselection = TIM_ICSelection_IndirectTI;
655 }
656 else
657 {
658 icoppositeselection = TIM_ICSelection_DirectTI;
659 }
660 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
661 {
662 /* TI1 Configuration */
663 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
664 TIM_ICInitStruct->TIM_ICFilter);
665 /* Set the Input Capture Prescaler value */
666 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
667 /* TI2 Configuration */
668 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
669 /* Set the Input Capture Prescaler value */
670 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
671 }
672 else
673 {
674 /* TI2 Configuration */
675 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
676 TIM_ICInitStruct->TIM_ICFilter);
677 /* Set the Input Capture Prescaler value */
678 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
679 /* TI1 Configuration */
680 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
681 /* Set the Input Capture Prescaler value */
682 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
683 }
684 }
685  
686 /**
687 * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
688 * the OSSR State and the AOE(automatic output enable).
689 * @param TIMx: where x can be 1 or 8 to select the TIM
690 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
691 * contains the BDTR Register configuration information for the TIM peripheral.
692 * @retval None
693 */
694 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
695 {
696 /* Check the parameters */
697 assert_param(IS_TIM_18_PERIPH(TIMx));
698 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
699 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
700 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
701 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
702 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
703 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
704 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
705 the OSSI State, the dead time value and the Automatic Output Enable Bit */
706 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
707 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
708 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
709 TIM_BDTRInitStruct->TIM_AutomaticOutput;
710 }
711  
712 /**
713 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
714 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
715 * structure which will be initialized.
716 * @retval None
717 */
718 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
719 {
720 /* Set the default configuration */
721 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
722 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
723 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
724 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
725 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
726 }
727  
728 /**
729 * @brief Fills each TIM_OCInitStruct member with its default value.
730 * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
731 * be initialized.
732 * @retval None
733 */
734 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
735 {
736 /* Set the default configuration */
737 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
738 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
739 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
740 TIM_OCInitStruct->TIM_Pulse = 0x0000;
741 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
742 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
743 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
744 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
745 }
746  
747 /**
748 * @brief Fills each TIM_ICInitStruct member with its default value.
749 * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
750 * be initialized.
751 * @retval None
752 */
753 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
754 {
755 /* Set the default configuration */
756 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
757 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
758 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
759 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
760 TIM_ICInitStruct->TIM_ICFilter = 0x00;
761 }
762  
763 /**
764 * @brief Fills each TIM_BDTRInitStruct member with its default value.
765 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
766 * will be initialized.
767 * @retval None
768 */
769 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
770 {
771 /* Set the default configuration */
772 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
773 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
774 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
775 TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
776 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
777 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
778 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
779 }
780  
781 /**
782 * @brief Enables or disables the specified TIM peripheral.
783 * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
784 * @param NewState: new state of the TIMx peripheral.
785 * This parameter can be: ENABLE or DISABLE.
786 * @retval None
787 */
788 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
789 {
790 /* Check the parameters */
791 assert_param(IS_TIM_ALL_PERIPH(TIMx));
792 assert_param(IS_FUNCTIONAL_STATE(NewState));
793  
794 if (NewState != DISABLE)
795 {
796 /* Enable the TIM Counter */
797 TIMx->CR1 |= CR1_CEN_Set;
798 }
799 else
800 {
801 /* Disable the TIM Counter */
802 TIMx->CR1 &= CR1_CEN_Reset;
803 }
804 }
805  
806 /**
807 * @brief Enables or disables the TIM peripheral Main Outputs.
808 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
809 * @param NewState: new state of the TIM peripheral Main Outputs.
810 * This parameter can be: ENABLE or DISABLE.
811 * @retval None
812 */
813 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
814 {
815 /* Check the parameters */
816 assert_param(IS_TIM_18_PERIPH(TIMx));
817 assert_param(IS_FUNCTIONAL_STATE(NewState));
818 if (NewState != DISABLE)
819 {
820 /* Enable the TIM Main Output */
821 TIMx->BDTR |= BDTR_MOE_Set;
822 }
823 else
824 {
825 /* Disable the TIM Main Output */
826 TIMx->BDTR &= BDTR_MOE_Reset;
827 }
828 }
829  
830 /**
831 * @brief Enables or disables the specified TIM interrupts.
832 * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
833 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
834 * This parameter can be any combination of the following values:
835 * @arg TIM_IT_Update: TIM update Interrupt source
836 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
837 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
838 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
839 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
840 * @arg TIM_IT_COM: TIM Commutation Interrupt source
841 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
842 * @arg TIM_IT_Break: TIM Break Interrupt source
843 * @note
844 * - TIM6 and TIM7 can only generate an update interrupt.
845 * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
846 * @param NewState: new state of the TIM interrupts.
847 * This parameter can be: ENABLE or DISABLE.
848 * @retval None
849 */
850 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
851 {
852 /* Check the parameters */
853 assert_param(IS_TIM_ALL_PERIPH(TIMx));
854 assert_param(IS_TIM_IT(TIM_IT));
855 assert_param(IS_FUNCTIONAL_STATE(NewState));
856  
857 if (NewState != DISABLE)
858 {
859 /* Enable the Interrupt sources */
860 TIMx->DIER |= TIM_IT;
861 }
862 else
863 {
864 /* Disable the Interrupt sources */
865 TIMx->DIER &= (uint16_t)~TIM_IT;
866 }
867 }
868  
869 /**
870 * @brief Configures the TIMx event to be generate by software.
871 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
872 * @param TIM_EventSource: specifies the event source.
873 * This parameter can be one or more of the following values:
874 * @arg TIM_EventSource_Update: Timer update Event source
875 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
876 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
877 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
878 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
879 * @arg TIM_EventSource_COM: Timer COM event source
880 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
881 * @arg TIM_EventSource_Break: Timer Break event source
882 * @note
883 * - TIM6 and TIM7 can only generate an update event.
884 * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
885 * @retval None
886 */
887 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
888 {
889 /* Check the parameters */
890 assert_param(IS_TIM_ALL_PERIPH(TIMx));
891 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
892  
893 /* Set the event sources */
894 TIMx->EGR = TIM_EventSource;
895 }
896  
897 /**
898 * @brief Configures the TIMx’s DMA interface.
899 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
900 * @param TIM_DMABase: DMA Base address.
901 * This parameter can be one of the following values:
902 * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
903 * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
904 * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
905 * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
906 * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
907 * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
908 * TIM_DMABase_DCR.
909 * @param TIM_DMABurstLength: DMA Burst length.
910 * This parameter can be one value between:
911 * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
912 * @retval None
913 */
914 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
915 {
916 /* Check the parameters */
917 assert_param(IS_TIM_123458_PERIPH(TIMx));
918 assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
919 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
920 /* Set the DMA Base and the DMA Burst Length */
921 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
922 }
923  
924 /**
925 * @brief Enables or disables the TIMx’s DMA Requests.
926 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
927 * @param TIM_DMASource: specifies the DMA Request sources.
928 * This parameter can be any combination of the following values:
929 * @arg TIM_DMA_Update: TIM update Interrupt source
930 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
931 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
932 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
933 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
934 * @arg TIM_DMA_COM: TIM Commutation DMA source
935 * @arg TIM_DMA_Trigger: TIM Trigger DMA source
936 * @param NewState: new state of the DMA Request sources.
937 * This parameter can be: ENABLE or DISABLE.
938 * @retval None
939 */
940 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
941 {
942 /* Check the parameters */
943 assert_param(IS_TIM_ALL_PERIPH(TIMx));
944 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
945 assert_param(IS_FUNCTIONAL_STATE(NewState));
946  
947 if (NewState != DISABLE)
948 {
949 /* Enable the DMA sources */
950 TIMx->DIER |= TIM_DMASource;
951 }
952 else
953 {
954 /* Disable the DMA sources */
955 TIMx->DIER &= (uint16_t)~TIM_DMASource;
956 }
957 }
958  
959 /**
960 * @brief Configures the TIMx interrnal Clock
961 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
962 * @retval None
963 */
964 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
965 {
966 /* Check the parameters */
967 assert_param(IS_TIM_123458_PERIPH(TIMx));
968 /* Disable slave mode to clock the prescaler directly with the internal clock */
969 TIMx->SMCR &= SMCR_SMS_Mask;
970 }
971  
972 /**
973 * @brief Configures the TIMx Internal Trigger as External Clock
974 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
975 * @param TIM_ITRSource: Trigger source.
976 * This parameter can be one of the following values:
977 * @param TIM_TS_ITR0: Internal Trigger 0
978 * @param TIM_TS_ITR1: Internal Trigger 1
979 * @param TIM_TS_ITR2: Internal Trigger 2
980 * @param TIM_TS_ITR3: Internal Trigger 3
981 * @retval None
982 */
983 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
984 {
985 /* Check the parameters */
986 assert_param(IS_TIM_123458_PERIPH(TIMx));
987 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
988 /* Select the Internal Trigger */
989 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
990 /* Select the External clock mode1 */
991 TIMx->SMCR |= TIM_SlaveMode_External1;
992 }
993  
994 /**
995 * @brief Configures the TIMx Trigger as External Clock
996 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
997 * @param TIM_TIxExternalCLKSource: Trigger source.
998 * This parameter can be one of the following values:
999 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
1000 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
1001 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
1002 * @param TIM_ICPolarity: specifies the TIx Polarity.
1003 * This parameter can be one of the following values:
1004 * @arg TIM_ICPolarity_Rising
1005 * @arg TIM_ICPolarity_Falling
1006 * @param ICFilter : specifies the filter value.
1007 * This parameter must be a value between 0x0 and 0xF.
1008 * @retval None
1009 */
1010 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
1011 uint16_t TIM_ICPolarity, uint16_t ICFilter)
1012 {
1013 /* Check the parameters */
1014 assert_param(IS_TIM_123458_PERIPH(TIMx));
1015 assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
1016 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
1017 assert_param(IS_TIM_IC_FILTER(ICFilter));
1018 /* Configure the Timer Input Clock Source */
1019 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
1020 {
1021 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
1022 }
1023 else
1024 {
1025 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
1026 }
1027 /* Select the Trigger source */
1028 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
1029 /* Select the External clock mode1 */
1030 TIMx->SMCR |= TIM_SlaveMode_External1;
1031 }
1032  
1033 /**
1034 * @brief Configures the External clock Mode1
1035 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1036 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
1037 * This parameter can be one of the following values:
1038 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
1039 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
1040 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
1041 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
1042 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
1043 * This parameter can be one of the following values:
1044 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
1045 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
1046 * @param ExtTRGFilter: External Trigger Filter.
1047 * This parameter must be a value between 0x00 and 0x0F
1048 * @retval None
1049 */
1050 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1051 uint16_t ExtTRGFilter)
1052 {
1053 uint16_t tmpsmcr = 0;
1054 /* Check the parameters */
1055 assert_param(IS_TIM_123458_PERIPH(TIMx));
1056 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
1057 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
1058 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
1059 /* Configure the ETR Clock source */
1060 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
1061  
1062 /* Get the TIMx SMCR register value */
1063 tmpsmcr = TIMx->SMCR;
1064 /* Reset the SMS Bits */
1065 tmpsmcr &= SMCR_SMS_Mask;
1066 /* Select the External clock mode1 */
1067 tmpsmcr |= TIM_SlaveMode_External1;
1068 /* Select the Trigger selection : ETRF */
1069 tmpsmcr &= SMCR_TS_Mask;
1070 tmpsmcr |= TIM_TS_ETRF;
1071 /* Write to TIMx SMCR */
1072 TIMx->SMCR = tmpsmcr;
1073 }
1074  
1075 /**
1076 * @brief Configures the External clock Mode2
1077 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1078 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
1079 * This parameter can be one of the following values:
1080 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
1081 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
1082 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
1083 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
1084 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
1085 * This parameter can be one of the following values:
1086 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
1087 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
1088 * @param ExtTRGFilter: External Trigger Filter.
1089 * This parameter must be a value between 0x00 and 0x0F
1090 * @retval None
1091 */
1092 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
1093 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
1094 {
1095 /* Check the parameters */
1096 assert_param(IS_TIM_123458_PERIPH(TIMx));
1097 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
1098 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
1099 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
1100 /* Configure the ETR Clock source */
1101 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
1102 /* Enable the External clock mode2 */
1103 TIMx->SMCR |= SMCR_ECE_Set;
1104 }
1105  
1106 /**
1107 * @brief Configures the TIMx External Trigger (ETR).
1108 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1109 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
1110 * This parameter can be one of the following values:
1111 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
1112 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
1113 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
1114 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
1115 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
1116 * This parameter can be one of the following values:
1117 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
1118 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
1119 * @param ExtTRGFilter: External Trigger Filter.
1120 * This parameter must be a value between 0x00 and 0x0F
1121 * @retval None
1122 */
1123 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1124 uint16_t ExtTRGFilter)
1125 {
1126 uint16_t tmpsmcr = 0;
1127 /* Check the parameters */
1128 assert_param(IS_TIM_123458_PERIPH(TIMx));
1129 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
1130 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
1131 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
1132 tmpsmcr = TIMx->SMCR;
1133 /* Reset the ETR Bits */
1134 tmpsmcr &= SMCR_ETR_Mask;
1135 /* Set the Prescaler, the Filter value and the Polarity */
1136 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
1137 /* Write to TIMx SMCR */
1138 TIMx->SMCR = tmpsmcr;
1139 }
1140  
1141 /**
1142 * @brief Configures the TIMx Prescaler.
1143 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
1144 * @param Prescaler: specifies the Prescaler Register value
1145 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
1146 * This parameter can be one of the following values:
1147 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
1148 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
1149 * @retval None
1150 */
1151 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
1152 {
1153 /* Check the parameters */
1154 assert_param(IS_TIM_ALL_PERIPH(TIMx));
1155 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
1156 /* Set the Prescaler value */
1157 TIMx->PSC = Prescaler;
1158 /* Set or reset the UG Bit */
1159 TIMx->EGR = TIM_PSCReloadMode;
1160 }
1161  
1162 /**
1163 * @brief Specifies the TIMx Counter Mode to be used.
1164 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1165 * @param TIM_CounterMode: specifies the Counter Mode to be used
1166 * This parameter can be one of the following values:
1167 * @arg TIM_CounterMode_Up: TIM Up Counting Mode
1168 * @arg TIM_CounterMode_Down: TIM Down Counting Mode
1169 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
1170 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
1171 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
1172 * @retval None
1173 */
1174 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
1175 {
1176 uint16_t tmpcr1 = 0;
1177 /* Check the parameters */
1178 assert_param(IS_TIM_123458_PERIPH(TIMx));
1179 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
1180 tmpcr1 = TIMx->CR1;
1181 /* Reset the CMS and DIR Bits */
1182 tmpcr1 &= CR1_CounterMode_Mask;
1183 /* Set the Counter Mode */
1184 tmpcr1 |= TIM_CounterMode;
1185 /* Write to TIMx CR1 register */
1186 TIMx->CR1 = tmpcr1;
1187 }
1188  
1189 /**
1190 * @brief Selects the Input Trigger source
1191 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1192 * @param TIM_InputTriggerSource: The Input Trigger source.
1193 * This parameter can be one of the following values:
1194 * @arg TIM_TS_ITR0: Internal Trigger 0
1195 * @arg TIM_TS_ITR1: Internal Trigger 1
1196 * @arg TIM_TS_ITR2: Internal Trigger 2
1197 * @arg TIM_TS_ITR3: Internal Trigger 3
1198 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
1199 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
1200 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
1201 * @arg TIM_TS_ETRF: External Trigger input
1202 * @retval None
1203 */
1204 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
1205 {
1206 uint16_t tmpsmcr = 0;
1207 /* Check the parameters */
1208 assert_param(IS_TIM_123458_PERIPH(TIMx));
1209 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
1210 /* Get the TIMx SMCR register value */
1211 tmpsmcr = TIMx->SMCR;
1212 /* Reset the TS Bits */
1213 tmpsmcr &= SMCR_TS_Mask;
1214 /* Set the Input Trigger source */
1215 tmpsmcr |= TIM_InputTriggerSource;
1216 /* Write to TIMx SMCR */
1217 TIMx->SMCR = tmpsmcr;
1218 }
1219  
1220 /**
1221 * @brief Configures the TIMx Encoder Interface.
1222 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1223 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
1224 * This parameter can be one of the following values:
1225 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
1226 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
1227 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
1228 * on the level of the other input.
1229 * @param TIM_IC1Polarity: specifies the IC1 Polarity
1230 * This parmeter can be one of the following values:
1231 * @arg TIM_ICPolarity_Falling: IC Falling edge.
1232 * @arg TIM_ICPolarity_Rising: IC Rising edge.
1233 * @param TIM_IC2Polarity: specifies the IC2 Polarity
1234 * This parmeter can be one of the following values:
1235 * @arg TIM_ICPolarity_Falling: IC Falling edge.
1236 * @arg TIM_ICPolarity_Rising: IC Rising edge.
1237 * @retval None
1238 */
1239 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
1240 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
1241 {
1242 uint16_t tmpsmcr = 0;
1243 uint16_t tmpccmr1 = 0;
1244 uint16_t tmpccer = 0;
1245  
1246 /* Check the parameters */
1247 assert_param(IS_TIM_123458_PERIPH(TIMx));
1248 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
1249 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
1250 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
1251  
1252 /* Get the TIMx SMCR register value */
1253 tmpsmcr = TIMx->SMCR;
1254  
1255 /* Get the TIMx CCMR1 register value */
1256 tmpccmr1 = TIMx->CCMR1;
1257  
1258 /* Get the TIMx CCER register value */
1259 tmpccer = TIMx->CCER;
1260  
1261 /* Set the encoder Mode */
1262 tmpsmcr &= SMCR_SMS_Mask;
1263 tmpsmcr |= TIM_EncoderMode;
1264  
1265 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
1266 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
1267 tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
1268  
1269 /* Set the TI1 and the TI2 Polarities */
1270 tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
1271 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
1272  
1273 /* Write to TIMx SMCR */
1274 TIMx->SMCR = tmpsmcr;
1275  
1276 /* Write to TIMx CCMR1 */
1277 TIMx->CCMR1 = tmpccmr1;
1278  
1279 /* Write to TIMx CCER */
1280 TIMx->CCER = tmpccer;
1281 }
1282  
1283 /**
1284 * @brief Forces the TIMx output 1 waveform to active or inactive level.
1285 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1286 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1287 * This parameter can be one of the following values:
1288 * @arg TIM_ForcedAction_Active: Force active level on OC1REF
1289 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
1290 * @retval None
1291 */
1292 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1293 {
1294 uint16_t tmpccmr1 = 0;
1295 /* Check the parameters */
1296 assert_param(IS_TIM_123458_PERIPH(TIMx));
1297 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1298 tmpccmr1 = TIMx->CCMR1;
1299 /* Reset the OC1M Bits */
1300 tmpccmr1 &= CCMR_OC13M_Mask;
1301 /* Configure The Forced output Mode */
1302 tmpccmr1 |= TIM_ForcedAction;
1303 /* Write to TIMx CCMR1 register */
1304 TIMx->CCMR1 = tmpccmr1;
1305 }
1306  
1307 /**
1308 * @brief Forces the TIMx output 2 waveform to active or inactive level.
1309 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1310 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1311 * This parameter can be one of the following values:
1312 * @arg TIM_ForcedAction_Active: Force active level on OC2REF
1313 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
1314 * @retval None
1315 */
1316 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1317 {
1318 uint16_t tmpccmr1 = 0;
1319 /* Check the parameters */
1320 assert_param(IS_TIM_123458_PERIPH(TIMx));
1321 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1322 tmpccmr1 = TIMx->CCMR1;
1323 /* Reset the OC2M Bits */
1324 tmpccmr1 &= CCMR_OC24M_Mask;
1325 /* Configure The Forced output Mode */
1326 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
1327 /* Write to TIMx CCMR1 register */
1328 TIMx->CCMR1 = tmpccmr1;
1329 }
1330  
1331 /**
1332 * @brief Forces the TIMx output 3 waveform to active or inactive level.
1333 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1334 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1335 * This parameter can be one of the following values:
1336 * @arg TIM_ForcedAction_Active: Force active level on OC3REF
1337 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
1338 * @retval None
1339 */
1340 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1341 {
1342 uint16_t tmpccmr2 = 0;
1343 /* Check the parameters */
1344 assert_param(IS_TIM_123458_PERIPH(TIMx));
1345 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1346 tmpccmr2 = TIMx->CCMR2;
1347 /* Reset the OC1M Bits */
1348 tmpccmr2 &= CCMR_OC13M_Mask;
1349 /* Configure The Forced output Mode */
1350 tmpccmr2 |= TIM_ForcedAction;
1351 /* Write to TIMx CCMR2 register */
1352 TIMx->CCMR2 = tmpccmr2;
1353 }
1354  
1355 /**
1356 * @brief Forces the TIMx output 4 waveform to active or inactive level.
1357 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1358 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1359 * This parameter can be one of the following values:
1360 * @arg TIM_ForcedAction_Active: Force active level on OC4REF
1361 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
1362 * @retval None
1363 */
1364 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1365 {
1366 uint16_t tmpccmr2 = 0;
1367 /* Check the parameters */
1368 assert_param(IS_TIM_123458_PERIPH(TIMx));
1369 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1370 tmpccmr2 = TIMx->CCMR2;
1371 /* Reset the OC2M Bits */
1372 tmpccmr2 &= CCMR_OC24M_Mask;
1373 /* Configure The Forced output Mode */
1374 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
1375 /* Write to TIMx CCMR2 register */
1376 TIMx->CCMR2 = tmpccmr2;
1377 }
1378  
1379 /**
1380 * @brief Enables or disables TIMx peripheral Preload register on ARR.
1381 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1382 * @param NewState: new state of the TIMx peripheral Preload register
1383 * This parameter can be: ENABLE or DISABLE.
1384 * @retval None
1385 */
1386 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
1387 {
1388 /* Check the parameters */
1389 assert_param(IS_TIM_ALL_PERIPH(TIMx));
1390 assert_param(IS_FUNCTIONAL_STATE(NewState));
1391 if (NewState != DISABLE)
1392 {
1393 /* Set the ARR Preload Bit */
1394 TIMx->CR1 |= CR1_ARPE_Set;
1395 }
1396 else
1397 {
1398 /* Reset the ARR Preload Bit */
1399 TIMx->CR1 &= CR1_ARPE_Reset;
1400 }
1401 }
1402  
1403 /**
1404 * @brief Selects the TIM peripheral Commutation event.
1405 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
1406 * @param NewState: new state of the Commutation event.
1407 * This parameter can be: ENABLE or DISABLE.
1408 * @retval None
1409 */
1410 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
1411 {
1412 /* Check the parameters */
1413 assert_param(IS_TIM_18_PERIPH(TIMx));
1414 assert_param(IS_FUNCTIONAL_STATE(NewState));
1415 if (NewState != DISABLE)
1416 {
1417 /* Set the COM Bit */
1418 TIMx->CR2 |= CR2_CCUS_Set;
1419 }
1420 else
1421 {
1422 /* Reset the COM Bit */
1423 TIMx->CR2 &= CR2_CCUS_Reset;
1424 }
1425 }
1426  
1427 /**
1428 * @brief Selects the TIMx peripheral Capture Compare DMA source.
1429 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1430 * @param NewState: new state of the Capture Compare DMA source
1431 * This parameter can be: ENABLE or DISABLE.
1432 * @retval None
1433 */
1434 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
1435 {
1436 /* Check the parameters */
1437 assert_param(IS_TIM_123458_PERIPH(TIMx));
1438 assert_param(IS_FUNCTIONAL_STATE(NewState));
1439 if (NewState != DISABLE)
1440 {
1441 /* Set the CCDS Bit */
1442 TIMx->CR2 |= CR2_CCDS_Set;
1443 }
1444 else
1445 {
1446 /* Reset the CCDS Bit */
1447 TIMx->CR2 &= CR2_CCDS_Reset;
1448 }
1449 }
1450  
1451 /**
1452 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
1453 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
1454 * @param NewState: new state of the Capture Compare Preload Control bit
1455 * This parameter can be: ENABLE or DISABLE.
1456 * @retval None
1457 */
1458 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
1459 {
1460 /* Check the parameters */
1461 assert_param(IS_TIM_18_PERIPH(TIMx));
1462 assert_param(IS_FUNCTIONAL_STATE(NewState));
1463 if (NewState != DISABLE)
1464 {
1465 /* Set the CCPC Bit */
1466 TIMx->CR2 |= CR2_CCPC_Set;
1467 }
1468 else
1469 {
1470 /* Reset the CCPC Bit */
1471 TIMx->CR2 &= CR2_CCPC_Reset;
1472 }
1473 }
1474  
1475 /**
1476 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
1477 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1478 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1479 * This parameter can be one of the following values:
1480 * @arg TIM_OCPreload_Enable
1481 * @arg TIM_OCPreload_Disable
1482 * @retval None
1483 */
1484 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1485 {
1486 uint16_t tmpccmr1 = 0;
1487 /* Check the parameters */
1488 assert_param(IS_TIM_123458_PERIPH(TIMx));
1489 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1490 tmpccmr1 = TIMx->CCMR1;
1491 /* Reset the OC1PE Bit */
1492 tmpccmr1 &= CCMR_OC13PE_Reset;
1493 /* Enable or Disable the Output Compare Preload feature */
1494 tmpccmr1 |= TIM_OCPreload;
1495 /* Write to TIMx CCMR1 register */
1496 TIMx->CCMR1 = tmpccmr1;
1497 }
1498  
1499 /**
1500 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
1501 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1502 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1503 * This parameter can be one of the following values:
1504 * @arg TIM_OCPreload_Enable
1505 * @arg TIM_OCPreload_Disable
1506 * @retval None
1507 */
1508 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1509 {
1510 uint16_t tmpccmr1 = 0;
1511 /* Check the parameters */
1512 assert_param(IS_TIM_123458_PERIPH(TIMx));
1513 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1514 tmpccmr1 = TIMx->CCMR1;
1515 /* Reset the OC2PE Bit */
1516 tmpccmr1 &= CCMR_OC24PE_Reset;
1517 /* Enable or Disable the Output Compare Preload feature */
1518 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
1519 /* Write to TIMx CCMR1 register */
1520 TIMx->CCMR1 = tmpccmr1;
1521 }
1522  
1523 /**
1524 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
1525 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1526 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1527 * This parameter can be one of the following values:
1528 * @arg TIM_OCPreload_Enable
1529 * @arg TIM_OCPreload_Disable
1530 * @retval None
1531 */
1532 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1533 {
1534 uint16_t tmpccmr2 = 0;
1535 /* Check the parameters */
1536 assert_param(IS_TIM_123458_PERIPH(TIMx));
1537 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1538 tmpccmr2 = TIMx->CCMR2;
1539 /* Reset the OC3PE Bit */
1540 tmpccmr2 &= CCMR_OC13PE_Reset;
1541 /* Enable or Disable the Output Compare Preload feature */
1542 tmpccmr2 |= TIM_OCPreload;
1543 /* Write to TIMx CCMR2 register */
1544 TIMx->CCMR2 = tmpccmr2;
1545 }
1546  
1547 /**
1548 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
1549 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1550 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1551 * This parameter can be one of the following values:
1552 * @arg TIM_OCPreload_Enable
1553 * @arg TIM_OCPreload_Disable
1554 * @retval None
1555 */
1556 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1557 {
1558 uint16_t tmpccmr2 = 0;
1559 /* Check the parameters */
1560 assert_param(IS_TIM_123458_PERIPH(TIMx));
1561 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1562 tmpccmr2 = TIMx->CCMR2;
1563 /* Reset the OC4PE Bit */
1564 tmpccmr2 &= CCMR_OC24PE_Reset;
1565 /* Enable or Disable the Output Compare Preload feature */
1566 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
1567 /* Write to TIMx CCMR2 register */
1568 TIMx->CCMR2 = tmpccmr2;
1569 }
1570  
1571 /**
1572 * @brief Configures the TIMx Output Compare 1 Fast feature.
1573 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1574 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1575 * This parameter can be one of the following values:
1576 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1577 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1578 * @retval None
1579 */
1580 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1581 {
1582 uint16_t tmpccmr1 = 0;
1583 /* Check the parameters */
1584 assert_param(IS_TIM_123458_PERIPH(TIMx));
1585 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1586 /* Get the TIMx CCMR1 register value */
1587 tmpccmr1 = TIMx->CCMR1;
1588 /* Reset the OC1FE Bit */
1589 tmpccmr1 &= CCMR_OC13FE_Reset;
1590 /* Enable or Disable the Output Compare Fast Bit */
1591 tmpccmr1 |= TIM_OCFast;
1592 /* Write to TIMx CCMR1 */
1593 TIMx->CCMR1 = tmpccmr1;
1594 }
1595  
1596 /**
1597 * @brief Configures the TIMx Output Compare 2 Fast feature.
1598 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1599 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1600 * This parameter can be one of the following values:
1601 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1602 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1603 * @retval None
1604 */
1605 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1606 {
1607 uint16_t tmpccmr1 = 0;
1608 /* Check the parameters */
1609 assert_param(IS_TIM_123458_PERIPH(TIMx));
1610 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1611 /* Get the TIMx CCMR1 register value */
1612 tmpccmr1 = TIMx->CCMR1;
1613 /* Reset the OC2FE Bit */
1614 tmpccmr1 &= CCMR_OC24FE_Reset;
1615 /* Enable or Disable the Output Compare Fast Bit */
1616 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
1617 /* Write to TIMx CCMR1 */
1618 TIMx->CCMR1 = tmpccmr1;
1619 }
1620  
1621 /**
1622 * @brief Configures the TIMx Output Compare 3 Fast feature.
1623 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1624 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1625 * This parameter can be one of the following values:
1626 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1627 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1628 * @retval None
1629 */
1630 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1631 {
1632 uint16_t tmpccmr2 = 0;
1633 /* Check the parameters */
1634 assert_param(IS_TIM_123458_PERIPH(TIMx));
1635 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1636 /* Get the TIMx CCMR2 register value */
1637 tmpccmr2 = TIMx->CCMR2;
1638 /* Reset the OC3FE Bit */
1639 tmpccmr2 &= CCMR_OC13FE_Reset;
1640 /* Enable or Disable the Output Compare Fast Bit */
1641 tmpccmr2 |= TIM_OCFast;
1642 /* Write to TIMx CCMR2 */
1643 TIMx->CCMR2 = tmpccmr2;
1644 }
1645  
1646 /**
1647 * @brief Configures the TIMx Output Compare 4 Fast feature.
1648 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1649 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1650 * This parameter can be one of the following values:
1651 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1652 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1653 * @retval None
1654 */
1655 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1656 {
1657 uint16_t tmpccmr2 = 0;
1658 /* Check the parameters */
1659 assert_param(IS_TIM_123458_PERIPH(TIMx));
1660 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1661 /* Get the TIMx CCMR2 register value */
1662 tmpccmr2 = TIMx->CCMR2;
1663 /* Reset the OC4FE Bit */
1664 tmpccmr2 &= CCMR_OC24FE_Reset;
1665 /* Enable or Disable the Output Compare Fast Bit */
1666 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
1667 /* Write to TIMx CCMR2 */
1668 TIMx->CCMR2 = tmpccmr2;
1669 }
1670  
1671 /**
1672 * @brief Clears or safeguards the OCREF1 signal on an external event
1673 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1674 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1675 * This parameter can be one of the following values:
1676 * @arg TIM_OCClear_Enable: TIM Output clear enable
1677 * @arg TIM_OCClear_Disable: TIM Output clear disable
1678 * @retval None
1679 */
1680 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1681 {
1682 uint16_t tmpccmr1 = 0;
1683 /* Check the parameters */
1684 assert_param(IS_TIM_123458_PERIPH(TIMx));
1685 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1686 tmpccmr1 = TIMx->CCMR1;
1687 /* Reset the OC1CE Bit */
1688 tmpccmr1 &= CCMR_OC13CE_Reset;
1689 /* Enable or Disable the Output Compare Clear Bit */
1690 tmpccmr1 |= TIM_OCClear;
1691 /* Write to TIMx CCMR1 register */
1692 TIMx->CCMR1 = tmpccmr1;
1693 }
1694  
1695 /**
1696 * @brief Clears or safeguards the OCREF2 signal on an external event
1697 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1698 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1699 * This parameter can be one of the following values:
1700 * @arg TIM_OCClear_Enable: TIM Output clear enable
1701 * @arg TIM_OCClear_Disable: TIM Output clear disable
1702 * @retval None
1703 */
1704 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1705 {
1706 uint16_t tmpccmr1 = 0;
1707 /* Check the parameters */
1708 assert_param(IS_TIM_123458_PERIPH(TIMx));
1709 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1710 tmpccmr1 = TIMx->CCMR1;
1711 /* Reset the OC2CE Bit */
1712 tmpccmr1 &= CCMR_OC24CE_Reset;
1713 /* Enable or Disable the Output Compare Clear Bit */
1714 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
1715 /* Write to TIMx CCMR1 register */
1716 TIMx->CCMR1 = tmpccmr1;
1717 }
1718  
1719 /**
1720 * @brief Clears or safeguards the OCREF3 signal on an external event
1721 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1722 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1723 * This parameter can be one of the following values:
1724 * @arg TIM_OCClear_Enable: TIM Output clear enable
1725 * @arg TIM_OCClear_Disable: TIM Output clear disable
1726 * @retval None
1727 */
1728 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1729 {
1730 uint16_t tmpccmr2 = 0;
1731 /* Check the parameters */
1732 assert_param(IS_TIM_123458_PERIPH(TIMx));
1733 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1734 tmpccmr2 = TIMx->CCMR2;
1735 /* Reset the OC3CE Bit */
1736 tmpccmr2 &= CCMR_OC13CE_Reset;
1737 /* Enable or Disable the Output Compare Clear Bit */
1738 tmpccmr2 |= TIM_OCClear;
1739 /* Write to TIMx CCMR2 register */
1740 TIMx->CCMR2 = tmpccmr2;
1741 }
1742  
1743 /**
1744 * @brief Clears or safeguards the OCREF4 signal on an external event
1745 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1746 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1747 * This parameter can be one of the following values:
1748 * @arg TIM_OCClear_Enable: TIM Output clear enable
1749 * @arg TIM_OCClear_Disable: TIM Output clear disable
1750 * @retval None
1751 */
1752 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1753 {
1754 uint16_t tmpccmr2 = 0;
1755 /* Check the parameters */
1756 assert_param(IS_TIM_123458_PERIPH(TIMx));
1757 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1758 tmpccmr2 = TIMx->CCMR2;
1759 /* Reset the OC4CE Bit */
1760 tmpccmr2 &= CCMR_OC24CE_Reset;
1761 /* Enable or Disable the Output Compare Clear Bit */
1762 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
1763 /* Write to TIMx CCMR2 register */
1764 TIMx->CCMR2 = tmpccmr2;
1765 }
1766  
1767 /**
1768 * @brief Configures the TIMx channel 1 polarity.
1769 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1770 * @param TIM_OCPolarity: specifies the OC1 Polarity
1771 * This parmeter can be one of the following values:
1772 * @arg TIM_OCPolarity_High: Output Compare active high
1773 * @arg TIM_OCPolarity_Low: Output Compare active low
1774 * @retval None
1775 */
1776 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1777 {
1778 uint16_t tmpccer = 0;
1779 /* Check the parameters */
1780 assert_param(IS_TIM_123458_PERIPH(TIMx));
1781 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1782 tmpccer = TIMx->CCER;
1783 /* Set or Reset the CC1P Bit */
1784 tmpccer &= CCER_CC1P_Reset;
1785 tmpccer |= TIM_OCPolarity;
1786 /* Write to TIMx CCER register */
1787 TIMx->CCER = tmpccer;
1788 }
1789  
1790 /**
1791 * @brief Configures the TIMx Channel 1N polarity.
1792 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1793 * @param TIM_OCNPolarity: specifies the OC1N Polarity
1794 * This parmeter can be one of the following values:
1795 * @arg TIM_OCNPolarity_High: Output Compare active high
1796 * @arg TIM_OCNPolarity_Low: Output Compare active low
1797 * @retval None
1798 */
1799 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1800 {
1801 uint16_t tmpccer = 0;
1802 /* Check the parameters */
1803 assert_param(IS_TIM_18_PERIPH(TIMx));
1804 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1805  
1806 tmpccer = TIMx->CCER;
1807 /* Set or Reset the CC1NP Bit */
1808 tmpccer &= CCER_CC1NP_Reset;
1809 tmpccer |= TIM_OCNPolarity;
1810 /* Write to TIMx CCER register */
1811 TIMx->CCER = tmpccer;
1812 }
1813  
1814 /**
1815 * @brief Configures the TIMx channel 2 polarity.
1816 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1817 * @param TIM_OCPolarity: specifies the OC2 Polarity
1818 * This parmeter can be one of the following values:
1819 * @arg TIM_OCPolarity_High: Output Compare active high
1820 * @arg TIM_OCPolarity_Low: Output Compare active low
1821 * @retval None
1822 */
1823 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1824 {
1825 uint16_t tmpccer = 0;
1826 /* Check the parameters */
1827 assert_param(IS_TIM_123458_PERIPH(TIMx));
1828 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1829 tmpccer = TIMx->CCER;
1830 /* Set or Reset the CC2P Bit */
1831 tmpccer &= CCER_CC2P_Reset;
1832 tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
1833 /* Write to TIMx CCER register */
1834 TIMx->CCER = tmpccer;
1835 }
1836  
1837 /**
1838 * @brief Configures the TIMx Channel 2N polarity.
1839 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1840 * @param TIM_OCNPolarity: specifies the OC2N Polarity
1841 * This parmeter can be one of the following values:
1842 * @arg TIM_OCNPolarity_High: Output Compare active high
1843 * @arg TIM_OCNPolarity_Low: Output Compare active low
1844 * @retval None
1845 */
1846 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1847 {
1848 uint16_t tmpccer = 0;
1849 /* Check the parameters */
1850 assert_param(IS_TIM_18_PERIPH(TIMx));
1851 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1852  
1853 tmpccer = TIMx->CCER;
1854 /* Set or Reset the CC2NP Bit */
1855 tmpccer &= CCER_CC2NP_Reset;
1856 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
1857 /* Write to TIMx CCER register */
1858 TIMx->CCER = tmpccer;
1859 }
1860  
1861 /**
1862 * @brief Configures the TIMx channel 3 polarity.
1863 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1864 * @param TIM_OCPolarity: specifies the OC3 Polarity
1865 * This parmeter can be one of the following values:
1866 * @arg TIM_OCPolarity_High: Output Compare active high
1867 * @arg TIM_OCPolarity_Low: Output Compare active low
1868 * @retval None
1869 */
1870 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1871 {
1872 uint16_t tmpccer = 0;
1873 /* Check the parameters */
1874 assert_param(IS_TIM_123458_PERIPH(TIMx));
1875 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1876 tmpccer = TIMx->CCER;
1877 /* Set or Reset the CC3P Bit */
1878 tmpccer &= CCER_CC3P_Reset;
1879 tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
1880 /* Write to TIMx CCER register */
1881 TIMx->CCER = tmpccer;
1882 }
1883  
1884 /**
1885 * @brief Configures the TIMx Channel 3N polarity.
1886 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1887 * @param TIM_OCNPolarity: specifies the OC3N Polarity
1888 * This parmeter can be one of the following values:
1889 * @arg TIM_OCNPolarity_High: Output Compare active high
1890 * @arg TIM_OCNPolarity_Low: Output Compare active low
1891 * @retval None
1892 */
1893 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1894 {
1895 uint16_t tmpccer = 0;
1896  
1897 /* Check the parameters */
1898 assert_param(IS_TIM_18_PERIPH(TIMx));
1899 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1900  
1901 tmpccer = TIMx->CCER;
1902 /* Set or Reset the CC3NP Bit */
1903 tmpccer &= CCER_CC3NP_Reset;
1904 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
1905 /* Write to TIMx CCER register */
1906 TIMx->CCER = tmpccer;
1907 }
1908  
1909 /**
1910 * @brief Configures the TIMx channel 4 polarity.
1911 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1912 * @param TIM_OCPolarity: specifies the OC4 Polarity
1913 * This parmeter can be one of the following values:
1914 * @arg TIM_OCPolarity_High: Output Compare active high
1915 * @arg TIM_OCPolarity_Low: Output Compare active low
1916 * @retval None
1917 */
1918 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1919 {
1920 uint16_t tmpccer = 0;
1921 /* Check the parameters */
1922 assert_param(IS_TIM_123458_PERIPH(TIMx));
1923 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1924 tmpccer = TIMx->CCER;
1925 /* Set or Reset the CC4P Bit */
1926 tmpccer &= CCER_CC4P_Reset;
1927 tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
1928 /* Write to TIMx CCER register */
1929 TIMx->CCER = tmpccer;
1930 }
1931  
1932 /**
1933 * @brief Enables or disables the TIM Capture Compare Channel x.
1934 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1935 * @param TIM_Channel: specifies the TIM Channel
1936 * This parmeter can be one of the following values:
1937 * @arg TIM_Channel_1: TIM Channel 1
1938 * @arg TIM_Channel_2: TIM Channel 2
1939 * @arg TIM_Channel_3: TIM Channel 3
1940 * @arg TIM_Channel_4: TIM Channel 4
1941 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
1942 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
1943 * @retval None
1944 */
1945 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
1946 {
1947 uint16_t tmp = 0;
1948  
1949 /* Check the parameters */
1950 assert_param(IS_TIM_123458_PERIPH(TIMx));
1951 assert_param(IS_TIM_CHANNEL(TIM_Channel));
1952 assert_param(IS_TIM_CCX(TIM_CCx));
1953  
1954 tmp = CCER_CCE_Set << TIM_Channel;
1955  
1956 /* Reset the CCxE Bit */
1957 TIMx->CCER &= (uint16_t)~ tmp;
1958  
1959 /* Set or reset the CCxE Bit */
1960 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
1961 }
1962  
1963 /**
1964 * @brief Enables or disables the TIM Capture Compare Channel xN.
1965 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1966 * @param TIM_Channel: specifies the TIM Channel
1967 * This parmeter can be one of the following values:
1968 * @arg TIM_Channel_1: TIM Channel 1
1969 * @arg TIM_Channel_2: TIM Channel 2
1970 * @arg TIM_Channel_3: TIM Channel 3
1971 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
1972 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
1973 * @retval None
1974 */
1975 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
1976 {
1977 uint16_t tmp = 0;
1978  
1979 /* Check the parameters */
1980 assert_param(IS_TIM_18_PERIPH(TIMx));
1981 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
1982 assert_param(IS_TIM_CCXN(TIM_CCxN));
1983  
1984 tmp = CCER_CCNE_Set << TIM_Channel;
1985  
1986 /* Reset the CCxNE Bit */
1987 TIMx->CCER &= (uint16_t) ~tmp;
1988  
1989 /* Set or reset the CCxNE Bit */
1990 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
1991 }
1992  
1993 /**
1994 * @brief Selects the TIM Ouput Compare Mode.
1995 * @note This function disables the selected channel before changing the Ouput
1996 * Compare Mode.
1997 * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
1998 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1999 * @param TIM_Channel: specifies the TIM Channel
2000 * This parmeter can be one of the following values:
2001 * @arg TIM_Channel_1: TIM Channel 1
2002 * @arg TIM_Channel_2: TIM Channel 2
2003 * @arg TIM_Channel_3: TIM Channel 3
2004 * @arg TIM_Channel_4: TIM Channel 4
2005 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
2006 * This paramter can be one of the following values:
2007 * @arg TIM_OCMode_Timing
2008 * @arg TIM_OCMode_Active
2009 * @arg TIM_OCMode_Toggle
2010 * @arg TIM_OCMode_PWM1
2011 * @arg TIM_OCMode_PWM2
2012 * @arg TIM_ForcedAction_Active
2013 * @arg TIM_ForcedAction_InActive
2014 * @retval None
2015 */
2016 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
2017 {
2018 uint32_t tmp = 0;
2019 uint16_t tmp1 = 0;
2020  
2021 /* Check the parameters */
2022 assert_param(IS_TIM_123458_PERIPH(TIMx));
2023 assert_param(IS_TIM_CHANNEL(TIM_Channel));
2024 assert_param(IS_TIM_OCM(TIM_OCMode));
2025  
2026 tmp = (uint32_t) TIMx;
2027 tmp += CCMR_Offset;
2028  
2029 tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
2030  
2031 /* Disable the Channel: Reset the CCxE Bit */
2032 TIMx->CCER &= (uint16_t) ~tmp1;
2033  
2034 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
2035 {
2036 tmp += (TIM_Channel>>1);
2037  
2038 /* Reset the OCxM bits in the CCMRx register */
2039 *(__IO uint32_t *) tmp &= CCMR_OC13M_Mask;
2040  
2041 /* Configure the OCxM bits in the CCMRx register */
2042 *(__IO uint32_t *) tmp |= TIM_OCMode;
2043 }
2044 else
2045 {
2046 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
2047  
2048 /* Reset the OCxM bits in the CCMRx register */
2049 *(__IO uint32_t *) tmp &= CCMR_OC24M_Mask;
2050  
2051 /* Configure the OCxM bits in the CCMRx register */
2052 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
2053 }
2054 }
2055  
2056 /**
2057 * @brief Enables or Disables the TIMx Update event.
2058 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2059 * @param NewState: new state of the TIMx UDIS bit
2060 * This parameter can be: ENABLE or DISABLE.
2061 * @retval None
2062 */
2063 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
2064 {
2065 /* Check the parameters */
2066 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2067 assert_param(IS_FUNCTIONAL_STATE(NewState));
2068 if (NewState != DISABLE)
2069 {
2070 /* Set the Update Disable Bit */
2071 TIMx->CR1 |= CR1_UDIS_Set;
2072 }
2073 else
2074 {
2075 /* Reset the Update Disable Bit */
2076 TIMx->CR1 &= CR1_UDIS_Reset;
2077 }
2078 }
2079  
2080 /**
2081 * @brief Configures the TIMx Update Request Interrupt source.
2082 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2083 * @param TIM_UpdateSource: specifies the Update source.
2084 * This parameter can be one of the following values:
2085 * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
2086 or the setting of UG bit, or an update generation
2087 through the slave mode controller.
2088 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
2089 * @retval None
2090 */
2091 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
2092 {
2093 /* Check the parameters */
2094 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2095 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
2096 if (TIM_UpdateSource != TIM_UpdateSource_Global)
2097 {
2098 /* Set the URS Bit */
2099 TIMx->CR1 |= CR1_URS_Set;
2100 }
2101 else
2102 {
2103 /* Reset the URS Bit */
2104 TIMx->CR1 &= CR1_URS_Reset;
2105 }
2106 }
2107  
2108 /**
2109 * @brief Enables or disables the TIMx’s Hall sensor interface.
2110 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2111 * @param NewState: new state of the TIMx Hall sensor interface.
2112 * This parameter can be: ENABLE or DISABLE.
2113 * @retval None
2114 */
2115 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
2116 {
2117 /* Check the parameters */
2118 assert_param(IS_TIM_123458_PERIPH(TIMx));
2119 assert_param(IS_FUNCTIONAL_STATE(NewState));
2120 if (NewState != DISABLE)
2121 {
2122 /* Set the TI1S Bit */
2123 TIMx->CR2 |= CR2_TI1S_Set;
2124 }
2125 else
2126 {
2127 /* Reset the TI1S Bit */
2128 TIMx->CR2 &= CR2_TI1S_Reset;
2129 }
2130 }
2131  
2132 /**
2133 * @brief Selects the TIMx’s One Pulse Mode.
2134 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2135 * @param TIM_OPMode: specifies the OPM Mode to be used.
2136 * This parameter can be one of the following values:
2137 * @arg TIM_OPMode_Single
2138 * @arg TIM_OPMode_Repetitive
2139 * @retval None
2140 */
2141 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
2142 {
2143 /* Check the parameters */
2144 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2145 assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
2146 /* Reset the OPM Bit */
2147 TIMx->CR1 &= CR1_OPM_Reset;
2148 /* Configure the OPM Mode */
2149 TIMx->CR1 |= TIM_OPMode;
2150 }
2151  
2152 /**
2153 * @brief Selects the TIMx Trigger Output Mode.
2154 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2155 * @param TIM_TRGOSource: specifies the Trigger Output source.
2156 * This paramter can be one of the following values:
2157 *
2158 * - For all TIMx
2159 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
2160 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
2161 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
2162 *
2163 * - For all TIMx except TIM6 and TIM7
2164 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
2165 * is to be set, as soon as a capture or compare match occurs (TRGO).
2166 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
2167 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
2168 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
2169 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
2170 *
2171 * @retval None
2172 */
2173 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
2174 {
2175 /* Check the parameters */
2176 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2177 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
2178 /* Reset the MMS Bits */
2179 TIMx->CR2 &= CR2_MMS_Mask;
2180 /* Select the TRGO source */
2181 TIMx->CR2 |= TIM_TRGOSource;
2182 }
2183  
2184 /**
2185 * @brief Selects the TIMx Slave Mode.
2186 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2187 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
2188 * This paramter can be one of the following values:
2189 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
2190 * the counter and triggers an update of the registers.
2191 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
2192 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
2193 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
2194 * @retval None
2195 */
2196 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
2197 {
2198 /* Check the parameters */
2199 assert_param(IS_TIM_123458_PERIPH(TIMx));
2200 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
2201 /* Reset the SMS Bits */
2202 TIMx->SMCR &= SMCR_SMS_Mask;
2203 /* Select the Slave Mode */
2204 TIMx->SMCR |= TIM_SlaveMode;
2205 }
2206  
2207 /**
2208 * @brief Sets or Resets the TIMx Master/Slave Mode.
2209 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2210 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
2211 * This paramter can be one of the following values:
2212 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
2213 * and its slaves (through TRGO).
2214 * @arg TIM_MasterSlaveMode_Disable: No action
2215 * @retval None
2216 */
2217 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
2218 {
2219 /* Check the parameters */
2220 assert_param(IS_TIM_123458_PERIPH(TIMx));
2221 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
2222 /* Reset the MSM Bit */
2223 TIMx->SMCR &= SMCR_MSM_Reset;
2224  
2225 /* Set or Reset the MSM Bit */
2226 TIMx->SMCR |= TIM_MasterSlaveMode;
2227 }
2228  
2229 /**
2230 * @brief Sets the TIMx Counter Register value
2231 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2232 * @param Counter: specifies the Counter register new value.
2233 * @retval None
2234 */
2235 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
2236 {
2237 /* Check the parameters */
2238 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2239 /* Set the Counter Register value */
2240 TIMx->CNT = Counter;
2241 }
2242  
2243 /**
2244 * @brief Sets the TIMx Autoreload Register value
2245 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2246 * @param Autoreload: specifies the Autoreload register new value.
2247 * @retval None
2248 */
2249 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
2250 {
2251 /* Check the parameters */
2252 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2253 /* Set the Autoreload Register value */
2254 TIMx->ARR = Autoreload;
2255 }
2256  
2257 /**
2258 * @brief Sets the TIMx Capture Compare1 Register value
2259 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2260 * @param Compare1: specifies the Capture Compare1 register new value.
2261 * @retval None
2262 */
2263 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
2264 {
2265 /* Check the parameters */
2266 assert_param(IS_TIM_123458_PERIPH(TIMx));
2267 /* Set the Capture Compare1 Register value */
2268 TIMx->CCR1 = Compare1;
2269 }
2270  
2271 /**
2272 * @brief Sets the TIMx Capture Compare2 Register value
2273 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2274 * @param Compare2: specifies the Capture Compare2 register new value.
2275 * @retval None
2276 */
2277 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
2278 {
2279 /* Check the parameters */
2280 assert_param(IS_TIM_123458_PERIPH(TIMx));
2281 /* Set the Capture Compare2 Register value */
2282 TIMx->CCR2 = Compare2;
2283 }
2284  
2285 /**
2286 * @brief Sets the TIMx Capture Compare3 Register value
2287 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2288 * @param Compare3: specifies the Capture Compare3 register new value.
2289 * @retval None
2290 */
2291 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
2292 {
2293 /* Check the parameters */
2294 assert_param(IS_TIM_123458_PERIPH(TIMx));
2295 /* Set the Capture Compare3 Register value */
2296 TIMx->CCR3 = Compare3;
2297 }
2298  
2299 /**
2300 * @brief Sets the TIMx Capture Compare4 Register value
2301 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2302 * @param Compare4: specifies the Capture Compare4 register new value.
2303 * @retval None
2304 */
2305 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
2306 {
2307 /* Check the parameters */
2308 assert_param(IS_TIM_123458_PERIPH(TIMx));
2309 /* Set the Capture Compare4 Register value */
2310 TIMx->CCR4 = Compare4;
2311 }
2312  
2313 /**
2314 * @brief Sets the TIMx Input Capture 1 prescaler.
2315 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2316 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
2317 * This parameter can be one of the following values:
2318 * @arg TIM_ICPSC_DIV1: no prescaler
2319 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2320 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2321 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2322 * @retval None
2323 */
2324 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2325 {
2326 /* Check the parameters */
2327 assert_param(IS_TIM_123458_PERIPH(TIMx));
2328 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2329 /* Reset the IC1PSC Bits */
2330 TIMx->CCMR1 &= CCMR_IC13PSC_Mask;
2331 /* Set the IC1PSC value */
2332 TIMx->CCMR1 |= TIM_ICPSC;
2333 }
2334  
2335 /**
2336 * @brief Sets the TIMx Input Capture 2 prescaler.
2337 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2338 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
2339 * This parameter can be one of the following values:
2340 * @arg TIM_ICPSC_DIV1: no prescaler
2341 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2342 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2343 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2344 * @retval None
2345 */
2346 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2347 {
2348 /* Check the parameters */
2349 assert_param(IS_TIM_123458_PERIPH(TIMx));
2350 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2351 /* Reset the IC2PSC Bits */
2352 TIMx->CCMR1 &= CCMR_IC24PSC_Mask;
2353 /* Set the IC2PSC value */
2354 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
2355 }
2356  
2357 /**
2358 * @brief Sets the TIMx Input Capture 3 prescaler.
2359 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2360 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
2361 * This parameter can be one of the following values:
2362 * @arg TIM_ICPSC_DIV1: no prescaler
2363 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2364 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2365 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2366 * @retval None
2367 */
2368 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2369 {
2370 /* Check the parameters */
2371 assert_param(IS_TIM_123458_PERIPH(TIMx));
2372 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2373 /* Reset the IC3PSC Bits */
2374 TIMx->CCMR2 &= CCMR_IC13PSC_Mask;
2375 /* Set the IC3PSC value */
2376 TIMx->CCMR2 |= TIM_ICPSC;
2377 }
2378  
2379 /**
2380 * @brief Sets the TIMx Input Capture 4 prescaler.
2381 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2382 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
2383 * This parameter can be one of the following values:
2384 * @arg TIM_ICPSC_DIV1: no prescaler
2385 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2386 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2387 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2388 * @retval None
2389 */
2390 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2391 {
2392 /* Check the parameters */
2393 assert_param(IS_TIM_123458_PERIPH(TIMx));
2394 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2395 /* Reset the IC4PSC Bits */
2396 TIMx->CCMR2 &= CCMR_IC24PSC_Mask;
2397 /* Set the IC4PSC value */
2398 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
2399 }
2400  
2401 /**
2402 * @brief Sets the TIMx Clock Division value.
2403 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2404 * @param TIM_CKD: specifies the clock division value.
2405 * This parameter can be one of the following value:
2406 * @arg TIM_CKD_DIV1: TDTS = Tck_tim
2407 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
2408 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
2409 * @retval None
2410 */
2411 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
2412 {
2413 /* Check the parameters */
2414 assert_param(IS_TIM_123458_PERIPH(TIMx));
2415 assert_param(IS_TIM_CKD_DIV(TIM_CKD));
2416 /* Reset the CKD Bits */
2417 TIMx->CR1 &= CR1_CKD_Mask;
2418 /* Set the CKD value */
2419 TIMx->CR1 |= TIM_CKD;
2420 }
2421  
2422 /**
2423 * @brief Gets the TIMx Input Capture 1 value.
2424 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2425 * @retval Capture Compare 1 Register value.
2426 */
2427 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
2428 {
2429 /* Check the parameters */
2430 assert_param(IS_TIM_123458_PERIPH(TIMx));
2431 /* Get the Capture 1 Register value */
2432 return TIMx->CCR1;
2433 }
2434  
2435 /**
2436 * @brief Gets the TIMx Input Capture 2 value.
2437 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2438 * @retval Capture Compare 2 Register value.
2439 */
2440 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
2441 {
2442 /* Check the parameters */
2443 assert_param(IS_TIM_123458_PERIPH(TIMx));
2444 /* Get the Capture 2 Register value */
2445 return TIMx->CCR2;
2446 }
2447  
2448 /**
2449 * @brief Gets the TIMx Input Capture 3 value.
2450 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2451 * @retval Capture Compare 3 Register value.
2452 */
2453 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
2454 {
2455 /* Check the parameters */
2456 assert_param(IS_TIM_123458_PERIPH(TIMx));
2457 /* Get the Capture 3 Register value */
2458 return TIMx->CCR3;
2459 }
2460  
2461 /**
2462 * @brief Gets the TIMx Input Capture 4 value.
2463 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2464 * @retval Capture Compare 4 Register value.
2465 */
2466 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
2467 {
2468 /* Check the parameters */
2469 assert_param(IS_TIM_123458_PERIPH(TIMx));
2470 /* Get the Capture 4 Register value */
2471 return TIMx->CCR4;
2472 }
2473  
2474 /**
2475 * @brief Gets the TIMx Counter value.
2476 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2477 * @retval Counter Register value.
2478 */
2479 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
2480 {
2481 /* Check the parameters */
2482 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2483 /* Get the Counter Register value */
2484 return TIMx->CNT;
2485 }
2486  
2487 /**
2488 * @brief Gets the TIMx Prescaler value.
2489 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2490 * @retval Prescaler Register value.
2491 */
2492 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
2493 {
2494 /* Check the parameters */
2495 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2496 /* Get the Prescaler Register value */
2497 return TIMx->PSC;
2498 }
2499  
2500 /**
2501 * @brief Checks whether the specified TIM flag is set or not.
2502 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2503 * @param TIM_FLAG: specifies the flag to check.
2504 * This parameter can be one of the following values:
2505 * @arg TIM_FLAG_Update: TIM update Flag
2506 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
2507 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
2508 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
2509 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
2510 * @arg TIM_FLAG_COM: TIM Commutation Flag
2511 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
2512 * @arg TIM_FLAG_Break: TIM Break Flag
2513 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
2514 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
2515 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
2516 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
2517 * @note
2518 * - TIM6 and TIM7 can have only one update flag.
2519 * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
2520 * @retval The new state of TIM_FLAG (SET or RESET).
2521 */
2522 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
2523 {
2524 ITStatus bitstatus = RESET;
2525 /* Check the parameters */
2526 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2527 assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
2528  
2529 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
2530 {
2531 bitstatus = SET;
2532 }
2533 else
2534 {
2535 bitstatus = RESET;
2536 }
2537 return bitstatus;
2538 }
2539  
2540 /**
2541 * @brief Clears the TIMx's pending flags.
2542 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2543 * @param TIM_FLAG: specifies the flag bit to clear.
2544 * This parameter can be any combination of the following values:
2545 * @arg TIM_FLAG_Update: TIM update Flag
2546 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
2547 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
2548 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
2549 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
2550 * @arg TIM_FLAG_COM: TIM Commutation Flag
2551 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
2552 * @arg TIM_FLAG_Break: TIM Break Flag
2553 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
2554 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
2555 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
2556 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
2557 * @note
2558 * - TIM6 and TIM7 can have only one update flag.
2559 * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
2560 * @retval None
2561 */
2562 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
2563 {
2564 /* Check the parameters */
2565 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2566 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
2567  
2568 /* Clear the flags */
2569 TIMx->SR = (uint16_t)~TIM_FLAG;
2570 }
2571  
2572 /**
2573 * @brief Checks whether the TIM interrupt has occurred or not.
2574 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2575 * @param TIM_IT: specifies the TIM interrupt source to check.
2576 * This parameter can be one of the following values:
2577 * @arg TIM_IT_Update: TIM update Interrupt source
2578 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
2579 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
2580 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
2581 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
2582 * @arg TIM_IT_COM: TIM Commutation Interrupt source
2583 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
2584 * @arg TIM_IT_Break: TIM Break Interrupt source
2585 * @note
2586 * - TIM6 and TIM7 can generate only an update interrupt.
2587 * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
2588 * @retval The new state of the TIM_IT(SET or RESET).
2589 */
2590 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
2591 {
2592 ITStatus bitstatus = RESET;
2593 uint16_t itstatus = 0x0, itenable = 0x0;
2594 /* Check the parameters */
2595 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2596 assert_param(IS_TIM_GET_IT(TIM_IT));
2597  
2598 itstatus = TIMx->SR & TIM_IT;
2599  
2600 itenable = TIMx->DIER & TIM_IT;
2601 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
2602 {
2603 bitstatus = SET;
2604 }
2605 else
2606 {
2607 bitstatus = RESET;
2608 }
2609 return bitstatus;
2610 }
2611  
2612 /**
2613 * @brief Clears the TIMx's interrupt pending bits.
2614 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
2615 * @param TIM_IT: specifies the pending bit to clear.
2616 * This parameter can be any combination of the following values:
2617 * @arg TIM_IT_Update: TIM1 update Interrupt source
2618 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
2619 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
2620 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
2621 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
2622 * @arg TIM_IT_COM: TIM Commutation Interrupt source
2623 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
2624 * @arg TIM_IT_Break: TIM Break Interrupt source
2625 * @note
2626 * - TIM6 and TIM7 can generate only an update interrupt.
2627 * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
2628 * @retval None
2629 */
2630 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
2631 {
2632 /* Check the parameters */
2633 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2634 assert_param(IS_TIM_IT(TIM_IT));
2635 /* Clear the IT pending Bit */
2636 TIMx->SR = (uint16_t)~TIM_IT;
2637 }
2638  
2639 /**
2640 * @brief Configure the TI1 as Input.
2641 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2642 * @param TIM_ICPolarity : The Input Polarity.
2643 * This parameter can be one of the following values:
2644 * @arg TIM_ICPolarity_Rising
2645 * @arg TIM_ICPolarity_Falling
2646 * @param TIM_ICSelection: specifies the input to be used.
2647 * This parameter can be one of the following values:
2648 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
2649 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
2650 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
2651 * @param TIM_ICFilter: Specifies the Input Capture Filter.
2652 * This parameter must be a value between 0x00 and 0x0F.
2653 * @retval None
2654 */
2655 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
2656 uint16_t TIM_ICFilter)
2657 {
2658 uint16_t tmpccmr1 = 0, tmpccer = 0;
2659 /* Disable the Channel 1: Reset the CC1E Bit */
2660 TIMx->CCER &= CCER_CC1E_Reset;
2661 tmpccmr1 = TIMx->CCMR1;
2662 tmpccer = TIMx->CCER;
2663 /* Select the Input and set the filter */
2664 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
2665 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
2666 /* Select the Polarity and set the CC1E Bit */
2667 tmpccer &= CCER_CC1P_Reset;
2668 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)CCER_CC1E_Set);
2669 /* Write to TIMx CCMR1 and CCER registers */
2670 TIMx->CCMR1 = tmpccmr1;
2671 TIMx->CCER = tmpccer;
2672 }
2673  
2674 /**
2675 * @brief Configure the TI2 as Input.
2676 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2677 * @param TIM_ICPolarity : The Input Polarity.
2678 * This parameter can be one of the following values:
2679 * @arg TIM_ICPolarity_Rising
2680 * @arg TIM_ICPolarity_Falling
2681 * @param TIM_ICSelection: specifies the input to be used.
2682 * This parameter can be one of the following values:
2683 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
2684 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
2685 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
2686 * @param TIM_ICFilter: Specifies the Input Capture Filter.
2687 * This parameter must be a value between 0x00 and 0x0F.
2688 * @retval None
2689 */
2690 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
2691 uint16_t TIM_ICFilter)
2692 {
2693 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
2694 /* Disable the Channel 2: Reset the CC2E Bit */
2695 TIMx->CCER &= CCER_CC2E_Reset;
2696 tmpccmr1 = TIMx->CCMR1;
2697 tmpccer = TIMx->CCER;
2698 tmp = (uint16_t)(TIM_ICPolarity << 4);
2699 /* Select the Input and set the filter */
2700 tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
2701 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
2702 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
2703 /* Select the Polarity and set the CC2E Bit */
2704 tmpccer &= CCER_CC2P_Reset;
2705 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC2E_Set);
2706 /* Write to TIMx CCMR1 and CCER registers */
2707 TIMx->CCMR1 = tmpccmr1 ;
2708 TIMx->CCER = tmpccer;
2709 }
2710  
2711 /**
2712 * @brief Configure the TI3 as Input.
2713 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2714 * @param TIM_ICPolarity : The Input Polarity.
2715 * This parameter can be one of the following values:
2716 * @arg TIM_ICPolarity_Rising
2717 * @arg TIM_ICPolarity_Falling
2718 * @param TIM_ICSelection: specifies the input to be used.
2719 * This parameter can be one of the following values:
2720 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
2721 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
2722 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
2723 * @param TIM_ICFilter: Specifies the Input Capture Filter.
2724 * This parameter must be a value between 0x00 and 0x0F.
2725 * @retval None
2726 */
2727 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
2728 uint16_t TIM_ICFilter)
2729 {
2730 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
2731 /* Disable the Channel 3: Reset the CC3E Bit */
2732 TIMx->CCER &= CCER_CC3E_Reset;
2733 tmpccmr2 = TIMx->CCMR2;
2734 tmpccer = TIMx->CCER;
2735 tmp = (uint16_t)(TIM_ICPolarity << 8);
2736 /* Select the Input and set the filter */
2737 tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
2738 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
2739 /* Select the Polarity and set the CC3E Bit */
2740 tmpccer &= CCER_CC3P_Reset;
2741 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC3E_Set);
2742 /* Write to TIMx CCMR2 and CCER registers */
2743 TIMx->CCMR2 = tmpccmr2;
2744 TIMx->CCER = tmpccer;
2745 }
2746  
2747 /**
2748 * @brief Configure the TI1 as Input.
2749 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2750 * @param TIM_ICPolarity : The Input Polarity.
2751 * This parameter can be one of the following values:
2752 * @arg TIM_ICPolarity_Rising
2753 * @arg TIM_ICPolarity_Falling
2754 * @param TIM_ICSelection: specifies the input to be used.
2755 * This parameter can be one of the following values:
2756 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
2757 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
2758 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
2759 * @param TIM_ICFilter: Specifies the Input Capture Filter.
2760 * This parameter must be a value between 0x00 and 0x0F.
2761 * @retval None
2762 */
2763 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
2764 uint16_t TIM_ICFilter)
2765 {
2766 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
2767  
2768 /* Disable the Channel 4: Reset the CC4E Bit */
2769 TIMx->CCER &= CCER_CC4E_Reset;
2770 tmpccmr2 = TIMx->CCMR2;
2771 tmpccer = TIMx->CCER;
2772 tmp = (uint16_t)(TIM_ICPolarity << 12);
2773  
2774 /* Select the Input and set the filter */
2775 tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
2776 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
2777 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
2778  
2779 /* Select the Polarity and set the CC4E Bit */
2780 tmpccer &= CCER_CC4P_Reset;
2781 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC4E_Set);
2782 /* Write to TIMx CCMR2 and CCER registers */
2783 TIMx->CCMR2 = tmpccmr2;
2784 TIMx->CCER = tmpccer ;
2785 }
2786  
2787 /**
2788 * @}
2789 */
2790  
2791 /**
2792 * @}
2793 */
2794  
2795 /**
2796 * @}
2797 */
2798  
2799 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/