Rev Author Line No. Line
3328 povik 1 /**
2 ******************************************************************************
3 * @file stm32_eth.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 06/19/2009
7 * @brief This file provides all the ETH firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
19 */
20  
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32_eth.h"
23 #include "stm32f10x_rcc.h"
24  
25 /** @addtogroup STM32_ETH_Driver
26 * @brief ETH driver modules
27 * @{
28 */
29  
30 /** @defgroup ETH_Private_TypesDefinitions
31 * @{
32 */
33 /**
34 * @}
35 */
36  
37  
38 /** @defgroup ETH_Private_Defines
39 * @{
40 */
41 /* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
42 ETH_DMADESCTypeDef *DMATxDescToSet;
43 ETH_DMADESCTypeDef *DMARxDescToGet;
44 ETH_DMADESCTypeDef *DMAPTPTxDescToSet;
45 ETH_DMADESCTypeDef *DMAPTPRxDescToGet;
46  
47 /* ETHERNET MAC address offsets */
48 #define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */
49 #define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */
50 /* ETHERNET MACMIIAR register Mask */
51 #define MACMIIAR_CR_Mask ((uint32_t)0xFFFFFFE3)
52 /* ETHERNET MACCR register Mask */
53 #define MACCR_CLEAR_Mask ((uint32_t)0xFF20810F)
54 /* ETHERNET MACFCR register Mask */
55 #define MACFCR_CLEAR_Mask ((uint32_t)0x0000FF41)
56 /* ETHERNET DMAOMR register Mask */
57 #define DMAOMR_CLEAR_Mask ((uint32_t)0xF8DE3F23)
58 /* ETHERNET Remote Wake-up frame register length */
59 #define ETH_WakeupRegisterLength 8
60 /* ETHERNET Missed frames counter Shift */
61 #define ETH_DMA_RxOverflowMissedFramesCounterShift 17
62 /* ETHERNET DMA Tx descriptors Collision Count Shift */
63 #define ETH_DMATxDesc_CollisionCountShift 3
64 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
65 #define ETH_DMATxDesc_BufferSize2Shift 16
66 /* ETHERNET DMA Rx descriptors Frame Length Shift */
67 #define ETH_DMARxDesc_FrameLengthShift 16
68 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
69 #define ETH_DMARxDesc_Buffer2SizeShift 16
70 /* ETHERNET errors */
71 #define ETH_ERROR ((uint32_t)0)
72 #define ETH_SUCCESS ((uint32_t)1)
73 /**
74 * @}
75 */
76  
77 /** @defgroup ETH_Private_Macros
78 * @{
79 */
80 /**
81 * @}
82 */
83  
84 /** @defgroup ETH_Private_Variables
85 * @{
86 */
87 /**
88 * @}
89 */
90  
91 /** @defgroup ETH_Private_FunctionPrototypes
92 * @{
93 */
94 /**
95 * @}
96 */
97  
98 /** @defgroup ETH_Private_Functions
99 * @{
100 */
101  
102 /**
103 * @brief Deinitializes the ETHERNET peripheral registers to their
104 * default reset values.
105 * @param None
106 * @retval : None
107 */
108 void ETH_DeInit(void)
109 {
110 RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
111 RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
112 }
113  
114 /**
115 * @brief Initializes the ETHERNET peripheral according to the specified
116 * parameters in the ETH_InitStruct .
117 * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
118 * that contains the configuration information for the
119 * specified ETHERNET peripheral.
120 * @param PHYAddress: external PHY address
121 * @retval : ETH_ERROR: Ethernet initialization failed
122 * ETH_SUCCESS: Ethernet successfully initialized
123 */
124 uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
125 {
126 uint32_t RegValue = 0, tmpreg = 0;
127 __IO uint32_t i = 0;
128 RCC_ClocksTypeDef rcc_clocks;
129 uint32_t hclk = 60000000;
130 __IO uint32_t timeout = 0;
131 /* Check the parameters */
132 /* MAC --------------------------*/
133 assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
134 assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
135 assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
136 assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
137 assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
138 assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
139 assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
140 assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
141 assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
142 assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
143 assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
144 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
145 assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
146 assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
147 assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
148 assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
149 assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
150 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
151 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
152 assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
153 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
154 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
155 assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
156 assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
157 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
158 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
159 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
160 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
161 assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
162 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
163 /* DMA --------------------------*/
164 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
165 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
166 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
167 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
168 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
169 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
170 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
171 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
172 assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
173 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
174 assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
175 assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
176 assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
177 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
178 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
179 /*-------------------------------- MAC Config ------------------------------*/
180 /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
181 /* Get the ETHERNET MACMIIAR value */
182 tmpreg = ETH->MACMIIAR;
183 /* Clear CSR Clock Range CR[2:0] bits */
184 tmpreg &= MACMIIAR_CR_Mask;
185 /* Get hclk frequency value */
186 RCC_GetClocksFreq(&rcc_clocks);
187 hclk = rcc_clocks.HCLK_Frequency;
188 /* Set CR bits depending on hclk value */
189 if((hclk >= 20000000)&&(hclk < 35000000))
190 {
191 /* CSR Clock Range between 20-35 MHz */
192 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
193 }
194 else if((hclk >= 35000000)&&(hclk < 60000000))
195 {
196 /* CSR Clock Range between 35-60 MHz */
197 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
198 }
199 else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
200 {
201 /* CSR Clock Range between 60-72 MHz */
202 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
203 }
204 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
205 ETH->MACMIIAR = (uint32_t)tmpreg;
206 /*-------------------- PHY initialization and configuration ----------------*/
207 /* Put the PHY in reset mode */
208 if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
209 {
210 /* Return ERROR in case of write timeout */
211 return ETH_ERROR;
212 }
213  
214 /* Delay to assure PHY reset */
215 for(i = PHY_ResetDelay; i != 0; i--)
216 {
217 }
218  
219 if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
220 {
221 /* We wait for linked satus... */
222 do
223 {
224 timeout++;
225 } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
226 /* Return ERROR in case of timeout */
227 if(timeout == PHY_READ_TO)
228 {
229 return ETH_ERROR;
230 }
231 /* Reset Timeout counter */
232 timeout = 0;
233  
234 /* Enable Auto-Negotiation */
235 if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
236 {
237 /* Return ERROR in case of write timeout */
238 return ETH_ERROR;
239 }
240  
241 /* Wait until the autonegotiation will be completed */
242 do
243 {
244 timeout++;
245 } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
246 /* Return ERROR in case of timeout */
247 if(timeout == PHY_READ_TO)
248 {
249 return ETH_ERROR;
250 }
251 /* Reset Timeout counter */
252 timeout = 0;
253  
254 /* Read the result of the autonegotiation */
255 RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
256  
257 /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
258 if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)
259 {
260 /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
261 ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
262  
263 }
264 else
265 {
266 /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
267 ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
268 }
269 /* Configure the MAC with the speed fixed by the autonegotiation process */
270 if(RegValue & PHY_Speed_Status)
271 {
272 /* Set Ethernet speed to 10M following the autonegotiation */
273 ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
274 }
275 else
276 {
277 /* Set Ethernet speed to 100M following the autonegotiation */
278 ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
279 }
280 }
281 else
282 {
283 if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
284 (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
285 {
286 /* Return ERROR in case of write timeout */
287 return ETH_ERROR;
288 }
289 /* Delay to assure PHY configuration */
290 for(i = PHY_ConfigDelay; i != 0; i--)
291 {
292 }
293 }
294 /*------------------------ ETHERNET MACCR Configuration --------------------*/
295 /* Get the ETHERNET MACCR value */
296 tmpreg = ETH->MACCR;
297 /* Clear WD, PCE, PS, TE and RE bits */
298 tmpreg &= MACCR_CLEAR_Mask;
299 /* Set the WD bit according to ETH_Watchdog value */
300 /* Set the JD: bit according to ETH_Jabber value */
301 /* Set the IFG bit according to ETH_InterFrameGap value */
302 /* Set the DCRS bit according to ETH_CarrierSense value */
303 /* Set the FES bit according to ETH_Speed value */
304 /* Set the DO bit according to ETH_ReceiveOwn value */
305 /* Set the LM bit according to ETH_LoopbackMode value */
306 /* Set the DM bit according to ETH_Mode value */
307 /* Set the IPC bit according to ETH_ChecksumOffload value */
308 /* Set the DR bit according to ETH_RetryTransmission value */
309 /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
310 /* Set the BL bit according to ETH_BackOffLimit value */
311 /* Set the DC bit according to ETH_DeferralCheck value */
312 tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
313 ETH_InitStruct->ETH_Jabber |
314 ETH_InitStruct->ETH_InterFrameGap |
315 ETH_InitStruct->ETH_CarrierSense |
316 ETH_InitStruct->ETH_Speed |
317 ETH_InitStruct->ETH_ReceiveOwn |
318 ETH_InitStruct->ETH_LoopbackMode |
319 ETH_InitStruct->ETH_Mode |
320 ETH_InitStruct->ETH_ChecksumOffload |
321 ETH_InitStruct->ETH_RetryTransmission |
322 ETH_InitStruct->ETH_AutomaticPadCRCStrip |
323 ETH_InitStruct->ETH_BackOffLimit |
324 ETH_InitStruct->ETH_DeferralCheck);
325 /* Write to ETHERNET MACCR */
326 ETH->MACCR = (uint32_t)tmpreg;
327  
328 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
329 /* Set the RA bit according to ETH_ReceiveAll value */
330 /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
331 /* Set the PCF bit according to ETH_PassControlFrames value */
332 /* Set the DBF bit according to ETH_BroadcastFramesReception value */
333 /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
334 /* Set the PR bit according to ETH_PromiscuousMode value */
335 /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
336 /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
337 /* Write to ETHERNET MACFFR */
338 ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
339 ETH_InitStruct->ETH_SourceAddrFilter |
340 ETH_InitStruct->ETH_PassControlFrames |
341 ETH_InitStruct->ETH_BroadcastFramesReception |
342 ETH_InitStruct->ETH_DestinationAddrFilter |
343 ETH_InitStruct->ETH_PromiscuousMode |
344 ETH_InitStruct->ETH_MulticastFramesFilter |
345 ETH_InitStruct->ETH_UnicastFramesFilter);
346 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
347 /* Write to ETHERNET MACHTHR */
348 ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
349 /* Write to ETHERNET MACHTLR */
350 ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
351 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
352 /* Get the ETHERNET MACFCR value */
353 tmpreg = ETH->MACFCR;
354 /* Clear xx bits */
355 tmpreg &= MACFCR_CLEAR_Mask;
356  
357 /* Set the PT bit according to ETH_PauseTime value */
358 /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
359 /* Set the PLT bit according to ETH_PauseLowThreshold value */
360 /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
361 /* Set the RFE bit according to ETH_ReceiveFlowControl value */
362 /* Set the TFE bit according to ETH_TransmitFlowControl value */
363 tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
364 ETH_InitStruct->ETH_ZeroQuantaPause |
365 ETH_InitStruct->ETH_PauseLowThreshold |
366 ETH_InitStruct->ETH_UnicastPauseFrameDetect |
367 ETH_InitStruct->ETH_ReceiveFlowControl |
368 ETH_InitStruct->ETH_TransmitFlowControl);
369 /* Write to ETHERNET MACFCR */
370 ETH->MACFCR = (uint32_t)tmpreg;
371 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
372 /* Set the ETV bit according to ETH_VLANTagComparison value */
373 /* Set the VL bit according to ETH_VLANTagIdentifier value */
374 ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
375 ETH_InitStruct->ETH_VLANTagIdentifier);
376  
377 /*-------------------------------- DMA Config ------------------------------*/
378 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
379 /* Get the ETHERNET DMAOMR value */
380 tmpreg = ETH->DMAOMR;
381 /* Clear xx bits */
382 tmpreg &= DMAOMR_CLEAR_Mask;
383  
384 /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
385 /* Set the RSF bit according to ETH_ReceiveStoreForward value */
386 /* Set the DFF bit according to ETH_FlushReceivedFrame value */
387 /* Set the TSF bit according to ETH_TransmitStoreForward value */
388 /* Set the TTC bit according to ETH_TransmitThresholdControl value */
389 /* Set the FEF bit according to ETH_ForwardErrorFrames value */
390 /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
391 /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
392 /* Set the OSF bit according to ETH_SecondFrameOperate value */
393 tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
394 ETH_InitStruct->ETH_ReceiveStoreForward |
395 ETH_InitStruct->ETH_FlushReceivedFrame |
396 ETH_InitStruct->ETH_TransmitStoreForward |
397 ETH_InitStruct->ETH_TransmitThresholdControl |
398 ETH_InitStruct->ETH_ForwardErrorFrames |
399 ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
400 ETH_InitStruct->ETH_ReceiveThresholdControl |
401 ETH_InitStruct->ETH_SecondFrameOperate);
402 /* Write to ETHERNET DMAOMR */
403 ETH->DMAOMR = (uint32_t)tmpreg;
404  
405 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
406 /* Set the AAL bit according to ETH_AddressAlignedBeats value */
407 /* Set the FB bit according to ETH_FixedBurst value */
408 /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
409 /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
410 /* Set the DSL bit according to ETH_DesciptorSkipLength value */
411 /* Set the PR and DA bits according to ETH_DMAArbitration value */
412 ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
413 ETH_InitStruct->ETH_FixedBurst |
414 ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
415 ETH_InitStruct->ETH_TxDMABurstLength |
416 (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
417 ETH_InitStruct->ETH_DMAArbitration |
418 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
419 /* Return Ethernet configuration success */
420 return ETH_SUCCESS;
421 }
422  
423 /**
424 * @brief Fills each ETH_InitStruct member with its default value.
425 * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
426 * which will be initialized.
427 * @retval : None
428 */
429 void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
430 {
431 /* ETH_InitStruct members default value */
432 /*------------------------ MAC -----------------------------------*/
433 ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
434 ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
435 ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
436 ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
437 ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
438 ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
439 ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
440 ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
441 ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
442 ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
443 ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
444 ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
445 ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
446 ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
447 ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
448 ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
449 ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
450 ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
451 ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
452 ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
453 ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
454 ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
455 ETH_InitStruct->ETH_HashTableHigh = 0x0;
456 ETH_InitStruct->ETH_HashTableLow = 0x0;
457 ETH_InitStruct->ETH_PauseTime = 0x0;
458 ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
459 ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
460 ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
461 ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
462 ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
463 ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
464 ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
465 /*------------------------ DMA -----------------------------------*/
466 ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
467 ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
468 ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
469 ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
470 ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
471 ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
472 ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
473 ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
474 ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
475 ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
476 ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
477 ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
478 ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
479 ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
480 ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
481 }
482  
483 /**
484 * @brief Enables ENET MAC and DMA reception/transmission
485 * @param None
486 * @retval : None
487 */
488 void ETH_Start(void)
489 {
490 /* Enable transmit state machine of the MAC for transmission on the MII */
491 ETH_MACTransmissionCmd(ENABLE);
492 /* Flush Transmit FIFO */
493 ETH_FlushTransmitFIFO();
494 /* Enable receive state machine of the MAC for reception from the MII */
495 ETH_MACReceptionCmd(ENABLE);
496  
497 /* Start DMA transmission */
498 ETH_DMATransmissionCmd(ENABLE);
499 /* Start DMA reception */
500 ETH_DMAReceptionCmd(ENABLE);
501 }
502  
503 /**
504 * @brief Transmits a packet, from application buffer, pointed by ppkt.
505 * @param ppkt: pointer to application packet buffer to transmit.
506 * @param FrameLength: Tx Packet size.
507 * @retval : ETH_ERROR: in case of Tx desc owned by DMA
508 * ETH_SUCCESS: for correct transmission
509 */
510 uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)
511 {
512 uint32_t offset = 0;
513  
514 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
515 if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
516 {
517 /* Return ERROR: OWN bit set */
518 return ETH_ERROR;
519 }
520  
521 /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
522 for(offset=0; offset<FrameLength; offset++)
523 {
524 (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
525 }
526  
527 /* Setting the Frame Length: bits[12:0] */
528 DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
529 /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
530 DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
531 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
532 DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
533 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
534 if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
535 {
536 /* Clear TBUS ETHERNET DMA flag */
537 ETH->DMASR = ETH_DMASR_TBUS;
538 /* Resume DMA transmission*/
539 ETH->DMATPDR = 0;
540 }
541  
542 /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */
543 /* Chained Mode */
544 if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
545 {
546 /* Selects the next DMA Tx descriptor list for next buffer to send */
547 DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
548 }
549 else /* Ring Mode */
550 {
551 if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
552 {
553 /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
554 DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
555 }
556 else
557 {
558 /* Selects the next DMA Tx descriptor list for next buffer to send */
559 DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
560 }
561 }
562 /* Return SUCCESS */
563 return ETH_SUCCESS;
564 }
565  
566 /**
567 * @brief Receives a packet and copies it to memory pointed by ppkt.
568 * @param ppkt: pointer to application packet receive buffer.
569 * @retval : ETH_ERROR: if there is error in reception
570 * framelength: received packet size if packet reception is correct
571 */
572 uint32_t ETH_HandleRxPkt(uint8_t *ppkt)
573 {
574 uint32_t offset = 0, framelength = 0;
575 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
576 if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
577 {
578 /* Return error: OWN bit set */
579 return ETH_ERROR;
580 }
581  
582 if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
583 ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
584 ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
585 {
586 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
587 framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
588 /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
589 for(offset=0; offset<framelength; offset++)
590 {
591 (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
592 }
593 }
594 else
595 {
596 /* Return ERROR */
597 framelength = ETH_ERROR;
598 }
599 /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
600 DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
601  
602 /* When Rx Buffer unavailable flag is set: clear it and resume reception */
603 if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
604 {
605 /* Clear RBUS ETHERNET DMA flag */
606 ETH->DMASR = ETH_DMASR_RBUS;
607 /* Resume DMA reception */
608 ETH->DMARPDR = 0;
609 }
610  
611 /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
612 /* Chained Mode */
613 if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
614 {
615 /* Selects the next DMA Rx descriptor list for next buffer to read */
616 DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
617 }
618 else /* Ring Mode */
619 {
620 if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
621 {
622 /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
623 DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
624 }
625 else
626 {
627 /* Selects the next DMA Rx descriptor list for next buffer to read */
628 DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
629 }
630 }
631  
632 /* Return Frame Length/ERROR */
633 return (framelength);
634 }
635  
636 /**
637 * @brief Get the size of received the received packet.
638 * @param None
639 * @retval : framelength: received packet size
640 */
641 uint32_t ETH_GetRxPktSize(void)
642 {
643 uint32_t frameLength = 0;
644 if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
645 ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
646 ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
647 ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
648 {
649 /* Get the size of the packet: including 4 bytes of the CRC */
650 frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
651 }
652  
653 /* Return Frame Length */
654 return frameLength;
655 }
656  
657 /**
658 * @brief Drop a Received packet (too small packet, etc...)
659 * @param None
660 * @retval : None
661 */
662 void ETH_DropRxPkt(void)
663 {
664 /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
665 DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
666 /* Chained Mode */
667 if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
668 {
669 /* Selects the next DMA Rx descriptor list for next buffer read */
670 DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
671 }
672 else /* Ring Mode */
673 {
674 if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
675 {
676 /* Selects the next DMA Rx descriptor list for next buffer read: this will
677 be the first Rx descriptor in this case */
678 DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
679 }
680 else
681 {
682 /* Selects the next DMA Rx descriptor list for next buffer read */
683 DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
684 }
685 }
686 }
687  
688 /*--------------------------------- PHY ------------------------------------*/
689 /**
690 * @brief Read a PHY register
691 * @param PHYAddress: PHY device address, is the index of one of supported
692 * 32 PHY devices.
693 * This parameter can be one of the following values: 0,..,31
694 * @param PHYReg: PHY register address, is the index of one of the 32
695 * PHY register.
696 * This parameter can be one of the following values:
697 * @arg PHY_BCR : Tranceiver Basic Control Register
698 * @arg PHY_BSR : Tranceiver Basic Status Register
699 * @arg PHY_SR : Tranceiver Status Register
700 * @arg More PHY register could be read depending on the used PHY
701 * @retval : ETH_ERROR: in case of timeout
702 * MAC MIIDR register value: Data read from the selected PHY register (correct read )
703 */
704 uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
705 {
706 uint32_t tmpreg = 0;
707 __IO uint32_t timeout = 0;
708 /* Check the parameters */
709 assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
710 assert_param(IS_ETH_PHY_REG(PHYReg));
711  
712 /* Get the ETHERNET MACMIIAR value */
713 tmpreg = ETH->MACMIIAR;
714 /* Keep only the CSR Clock Range CR[2:0] bits value */
715 tmpreg &= ~MACMIIAR_CR_Mask;
716 /* Prepare the MII address register value */
717 tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
718 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
719 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
720 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
721 /* Write the result value into the MII Address register */
722 ETH->MACMIIAR = tmpreg;
723 /* Check for the Busy flag */
724 do
725 {
726 timeout++;
727 tmpreg = ETH->MACMIIAR;
728 } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
729 /* Return ERROR in case of timeout */
730 if(timeout == PHY_READ_TO)
731 {
732 return (uint16_t)ETH_ERROR;
733 }
734  
735 /* Return data register value */
736 return (uint16_t)(ETH->MACMIIDR);
737 }
738  
739 /**
740 * @brief Write to a PHY register
741 * @param PHYAddress: PHY device address, is the index of one of supported
742 * 32 PHY devices.
743 * This parameter can be one of the following values: 0,..,31
744 * @param PHYReg: PHY register address, is the index of one of the 32
745 * PHY register.
746 * This parameter can be one of the following values:
747 * @arg PHY_BCR : Tranceiver Control Register
748 * @arg More PHY register could be written depending on the used PHY
749 * @param PHYValue: the value to write
750 * @retval : ETH_ERROR: in case of timeout
751 * ETH_SUCCESS: for correct write
752 */
753 uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
754 {
755 uint32_t tmpreg = 0;
756 __IO uint32_t timeout = 0;
757 /* Check the parameters */
758 assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
759 assert_param(IS_ETH_PHY_REG(PHYReg));
760  
761 /* Get the ETHERNET MACMIIAR value */
762 tmpreg = ETH->MACMIIAR;
763 /* Keep only the CSR Clock Range CR[2:0] bits value */
764 tmpreg &= ~MACMIIAR_CR_Mask;
765 /* Prepare the MII register address value */
766 tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
767 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
768 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
769 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
770 /* Give the value to the MII data register */
771 ETH->MACMIIDR = PHYValue;
772 /* Write the result value into the MII Address register */
773 ETH->MACMIIAR = tmpreg;
774 /* Check for the Busy flag */
775 do
776 {
777 timeout++;
778 tmpreg = ETH->MACMIIAR;
779 } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
780 /* Return ERROR in case of timeout */
781 if(timeout == PHY_WRITE_TO)
782 {
783 return ETH_ERROR;
784 }
785  
786 /* Return SUCCESS */
787 return ETH_SUCCESS;
788 }
789  
790 /**
791 * @brief Enables or disables the PHY loopBack mode.
792 * @param PHYAddress: PHY device address, is the index of one of supported
793 * 32 PHY devices.
794 * This parameter can be one of the following values:
795 * @param NewState: new state of the PHY loopBack mode.
796 * This parameter can be: ENABLE or DISABLE.
797 * Note: Don't be confused with ETH_MACLoopBackCmd function
798 * which enables internal loopback at MII level
799 * @retval : ETH_ERROR: in case of bad PHY configuration
800 * ETH_SUCCESS: for correct PHY configuration
801 */
802 uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
803 {
804 uint16_t tmpreg = 0;
805 /* Check the parameters */
806 assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
807 assert_param(IS_FUNCTIONAL_STATE(NewState));
808  
809 /* Get the PHY configuration to update it */
810 tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
811  
812 if (NewState != DISABLE)
813 {
814 /* Enable the PHY loopback mode */
815 tmpreg |= PHY_Loopback;
816 }
817 else
818 {
819 /* Disable the PHY loopback mode: normal mode */
820 tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
821 }
822 /* Update the PHY control register with the new configuration */
823 if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
824 {
825 return ETH_SUCCESS;
826 }
827 else
828 {
829 /* Return SUCCESS */
830 return ETH_ERROR;
831 }
832 }
833  
834 /*--------------------------------- MAC ------------------------------------*/
835 /**
836 * @brief Enables or disables the MAC transmission.
837 * @param NewState: new state of the MAC transmission.
838 * This parameter can be: ENABLE or DISABLE.
839 * @retval : None
840 */
841 void ETH_MACTransmissionCmd(FunctionalState NewState)
842 {
843 /* Check the parameters */
844 assert_param(IS_FUNCTIONAL_STATE(NewState));
845  
846 if (NewState != DISABLE)
847 {
848 /* Enable the MAC transmission */
849 ETH->MACCR |= ETH_MACCR_TE;
850 }
851 else
852 {
853 /* Disable the MAC transmission */
854 ETH->MACCR &= ~ETH_MACCR_TE;
855 }
856 }
857  
858 /**
859 * @brief Enables or disables the MAC reception.
860 * @param NewState: new state of the MAC reception.
861 * This parameter can be: ENABLE or DISABLE.
862 * @retval : None
863 */
864 void ETH_MACReceptionCmd(FunctionalState NewState)
865 {
866 /* Check the parameters */
867 assert_param(IS_FUNCTIONAL_STATE(NewState));
868  
869 if (NewState != DISABLE)
870 {
871 /* Enable the MAC reception */
872 ETH->MACCR |= ETH_MACCR_RE;
873 }
874 else
875 {
876 /* Disable the MAC reception */
877 ETH->MACCR &= ~ETH_MACCR_RE;
878 }
879 }
880  
881 /**
882 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
883 * @param None
884 * @retval : The new state of flow control busy status bit (SET or RESET).
885 */
886 FlagStatus ETH_GetFlowControlBusyStatus(void)
887 {
888 FlagStatus bitstatus = RESET;
889 /* The Flow Control register should not be written to until this bit is cleared */
890 if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
891 {
892 bitstatus = SET;
893 }
894 else
895 {
896 bitstatus = RESET;
897 }
898 return bitstatus;
899 }
900  
901 /**
902 * @brief Initiate a Pause Control Frame (Full-duplex only).
903 * @param None
904 * @retval : None
905 */
906 void ETH_InitiatePauseControlFrame(void)
907 {
908 /* When Set In full duplex MAC initiates pause control frame */
909 ETH->MACFCR |= ETH_MACFCR_FCBBPA;
910 }
911  
912 /**
913 * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only).
914 * @param NewState: new state of the MAC BackPressure operation activation.
915 * This parameter can be: ENABLE or DISABLE.
916 * @retval : None
917 */
918 void ETH_BackPressureActivationCmd(FunctionalState NewState)
919 {
920 /* Check the parameters */
921 assert_param(IS_FUNCTIONAL_STATE(NewState));
922  
923 if (NewState != DISABLE)
924 {
925 /* Activate the MAC BackPressure operation */
926 /* In Half duplex: during backpressure, when the MAC receives a new frame,
927 the transmitter starts sending a JAM pattern resulting in a collision */
928 ETH->MACFCR |= ETH_MACFCR_FCBBPA;
929 }
930 else
931 {
932 /* Desactivate the MAC BackPressure operation */
933 ETH->MACFCR &= ~ETH_MACFCR_FCBBPA;
934 }
935 }
936  
937 /**
938 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
939 * @param ETH_MAC_FLAG: specifies the flag to check.
940 * This parameter can be one of the following values:
941 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
942 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
943 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
944 * @arg ETH_MAC_FLAG_MMC : MMC flag
945 * @arg ETH_MAC_FLAG_PMT : PMT flag
946 * @retval : The new state of ETHERNET MAC flag (SET or RESET).
947 */
948 FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
949 {
950 FlagStatus bitstatus = RESET;
951 /* Check the parameters */
952 assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));
953 if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
954 {
955 bitstatus = SET;
956 }
957 else
958 {
959 bitstatus = RESET;
960 }
961 return bitstatus;
962 }
963  
964 /**
965 * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not.
966 * @param ETH_MAC_IT: specifies the interrupt source to check.
967 * This parameter can be one of the following values:
968 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
969 * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt
970 * @arg ETH_MAC_IT_MMCR : MMC receive interrupt
971 * @arg ETH_MAC_IT_MMC : MMC interrupt
972 * @arg ETH_MAC_IT_PMT : PMT interrupt
973 * @retval : The new state of ETHERNET MAC interrupt (SET or RESET).
974 */
975 ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
976 {
977 ITStatus bitstatus = RESET;
978 /* Check the parameters */
979 assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));
980 if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
981 {
982 bitstatus = SET;
983 }
984 else
985 {
986 bitstatus = RESET;
987 }
988 return bitstatus;
989 }
990  
991 /**
992 * @brief Enables or disables the specified ETHERNET MAC interrupts.
993 * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
994 * enabled or disabled.
995 * This parameter can be any combination of the following values:
996 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
997 * @arg ETH_MAC_IT_PMT : PMT interrupt
998 * @param NewState: new state of the specified ETHERNET MAC interrupts.
999 * This parameter can be: ENABLE or DISABLE.
1000 * @retval : None
1001 */
1002 void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
1003 {
1004 /* Check the parameters */
1005 assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
1006 assert_param(IS_FUNCTIONAL_STATE(NewState));
1007  
1008 if (NewState != DISABLE)
1009 {
1010 /* Enable the selected ETHERNET MAC interrupts */
1011 ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
1012 }
1013 else
1014 {
1015 /* Disable the selected ETHERNET MAC interrupts */
1016 ETH->MACIMR |= ETH_MAC_IT;
1017 }
1018 }
1019  
1020 /**
1021 * @brief Configures the selected MAC address.
1022 * @param MacAddr: The MAC addres to configure.
1023 * This parameter can be one of the following values:
1024 * @arg ETH_MAC_Address0 : MAC Address0
1025 * @arg ETH_MAC_Address1 : MAC Address1
1026 * @arg ETH_MAC_Address2 : MAC Address2
1027 * @arg ETH_MAC_Address3 : MAC Address3
1028 * @param Addr: Pointer on MAC address buffer data (6 bytes).
1029 * @retval : None
1030 */
1031 void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
1032 {
1033 uint32_t tmpreg;
1034 /* Check the parameters */
1035 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1036  
1037 /* Calculate the selectecd MAC address high register */
1038 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
1039 /* Load the selectecd MAC address high register */
1040 (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg;
1041 /* Calculate the selectecd MAC address low register */
1042 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
1043  
1044 /* Load the selectecd MAC address low register */
1045 (*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg;
1046 }
1047  
1048 /**
1049 * @brief Get the selected MAC address.
1050 * @param MacAddr: The MAC addres to return.
1051 * This parameter can be one of the following values:
1052 * @arg ETH_MAC_Address0 : MAC Address0
1053 * @arg ETH_MAC_Address1 : MAC Address1
1054 * @arg ETH_MAC_Address2 : MAC Address2
1055 * @arg ETH_MAC_Address3 : MAC Address3
1056 * @param Addr: Pointer on MAC address buffer data (6 bytes).
1057 * @retval : None
1058 */
1059 void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
1060 {
1061 uint32_t tmpreg;
1062 /* Check the parameters */
1063 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
1064  
1065 /* Get the selectecd MAC address high register */
1066 tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr));
1067  
1068 /* Calculate the selectecd MAC address buffer */
1069 Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
1070 Addr[4] = (tmpreg & (uint8_t)0xFF);
1071 /* Load the selectecd MAC address low register */
1072 tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr));
1073 /* Calculate the selectecd MAC address buffer */
1074 Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
1075 Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
1076 Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
1077 Addr[0] = (tmpreg & (uint8_t)0xFF);
1078 }
1079  
1080 /**
1081 * @brief Enables or disables the Address filter module uses the specified
1082 * ETHERNET MAC address for perfect filtering
1083 * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
1084 * This parameter can be one of the following values:
1085 * @arg ETH_MAC_Address1 : MAC Address1
1086 * @arg ETH_MAC_Address2 : MAC Address2
1087 * @arg ETH_MAC_Address3 : MAC Address3
1088 * @param NewState: new state of the specified ETHERNET MAC address use.
1089 * This parameter can be: ENABLE or DISABLE.
1090 * @retval : None
1091 */
1092 void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
1093 {
1094 /* Check the parameters */
1095 assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1096 assert_param(IS_FUNCTIONAL_STATE(NewState));
1097  
1098 if (NewState != DISABLE)
1099 {
1100 /* Enable the selected ETHERNET MAC address for perfect filtering */
1101 (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE;
1102 }
1103 else
1104 {
1105 /* Disable the selected ETHERNET MAC address for perfect filtering */
1106 (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);
1107 }
1108 }
1109  
1110 /**
1111 * @brief Set the filter type for the specified ETHERNET MAC address
1112 * @param MacAddr: specifies the ETHERNET MAC address
1113 * This parameter can be one of the following values:
1114 * @arg ETH_MAC_Address1 : MAC Address1
1115 * @arg ETH_MAC_Address2 : MAC Address2
1116 * @arg ETH_MAC_Address3 : MAC Address3
1117 * @param Filter: specifies the used frame received field for comparaison
1118 * This parameter can be one of the following values:
1119 * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare
1120 * with the SA fields of the received frame.
1121 * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare
1122 * with the DA fields of the received frame.
1123 * @retval : None
1124 */
1125 void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
1126 {
1127 /* Check the parameters */
1128 assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1129 assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
1130  
1131 if (Filter != ETH_MAC_AddressFilter_DA)
1132 {
1133 /* The selected ETHERNET MAC address is used to compare with the SA fields of the
1134 received frame. */
1135 (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA;
1136 }
1137 else
1138 {
1139 /* The selected ETHERNET MAC address is used to compare with the DA fields of the
1140 received frame. */
1141 (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);
1142 }
1143 }
1144  
1145 /**
1146 * @brief Set the filter type for the specified ETHERNET MAC address
1147 * @param MacAddr: specifies the ETHERNET MAC address
1148 * This parameter can be one of the following values:
1149 * @arg ETH_MAC_Address1 : MAC Address1
1150 * @arg ETH_MAC_Address2 : MAC Address2
1151 * @arg ETH_MAC_Address3 : MAC Address3
1152 * @param MaskByte: specifies the used address bytes for comparaison
1153 * This parameter can be any combination of the following values:
1154 * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
1155 * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
1156 * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
1157 * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
1158 * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
1159 * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
1160 * @retval : None
1161 */
1162 void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
1163 {
1164 /* Check the parameters */
1165 assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
1166 assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
1167  
1168 /* Clear MBC bits in the selected MAC address high register */
1169 (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);
1170 /* Set the selected Filetr mask bytes */
1171 (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte;
1172 }
1173 /*------------------------ DMA Tx/Rx Desciptors -----------------------------*/
1174  
1175 /**
1176 * @brief Initializes the DMA Tx descriptors in chain mode.
1177 * @param DMATxDescTab: Pointer on the first Tx desc list
1178 * @param TxBuff: Pointer on the first TxBuffer list
1179 * @param TxBuffCount: Number of the used Tx desc in the list
1180 * @retval : None
1181 */
1182 void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
1183 {
1184 uint32_t i = 0;
1185 ETH_DMADESCTypeDef *DMATxDesc;
1186  
1187 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
1188 DMATxDescToSet = DMATxDescTab;
1189 /* Fill each DMATxDesc descriptor with the right values */
1190 for(i=0; i < TxBuffCount; i++)
1191 {
1192 /* Get the pointer on the ith member of the Tx Desc list */
1193 DMATxDesc = DMATxDescTab + i;
1194 /* Set Second Address Chained bit */
1195 DMATxDesc->Status = ETH_DMATxDesc_TCH;
1196  
1197 /* Set Buffer1 address pointer */
1198 DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
1199  
1200 /* Initialize the next descriptor with the Next Desciptor Polling Enable */
1201 if(i < (TxBuffCount-1))
1202 {
1203 /* Set next descriptor address register with next descriptor base address */
1204 DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
1205 }
1206 else
1207 {
1208 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
1209 DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
1210 }
1211 }
1212  
1213 /* Set Transmit Desciptor List Address Register */
1214 ETH->DMATDLAR = (uint32_t) DMATxDescTab;
1215 }
1216  
1217 /**
1218 * @brief Initializes the DMA Tx descriptors in ring mode.
1219 * @param DMATxDescTab: Pointer on the first Tx desc list
1220 * @param TxBuff1: Pointer on the first TxBuffer1 list
1221 * @param TxBuff2: Pointer on the first TxBuffer2 list
1222 * @param TxBuffCount: Number of the used Tx desc in the list
1223 * Note: see decriptor skip length defined in ETH_DMA_InitStruct
1224 * for the number of Words to skip between two unchained descriptors.
1225 * @retval : None
1226 */
1227 void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)
1228 {
1229 uint32_t i = 0;
1230 ETH_DMADESCTypeDef *DMATxDesc;
1231  
1232 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
1233 DMATxDescToSet = DMATxDescTab;
1234 /* Fill each DMATxDesc descriptor with the right values */
1235 for(i=0; i < TxBuffCount; i++)
1236 {
1237 /* Get the pointer on the ith member of the Tx Desc list */
1238 DMATxDesc = DMATxDescTab + i;
1239 /* Set Buffer1 address pointer */
1240 DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
1241  
1242 /* Set Buffer2 address pointer */
1243 DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
1244  
1245 /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
1246 address of the list, creating a Desciptor Ring */
1247 if(i == (TxBuffCount-1))
1248 {
1249 /* Set Transmit End of Ring bit */
1250 DMATxDesc->Status = ETH_DMATxDesc_TER;
1251 }
1252 }
1253  
1254 /* Set Transmit Desciptor List Address Register */
1255 ETH->DMATDLAR = (uint32_t) DMATxDescTab;
1256 }
1257  
1258 /**
1259 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1260 * @param DMATxDesc: pointer on a DMA Tx descriptor
1261 * @param ETH_DMATxDescFlag: specifies the flag to check.
1262 * This parameter can be one of the following values:
1263 * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
1264 * @arg ETH_DMATxDesc_IC : Interrupt on completetion
1265 * @arg ETH_DMATxDesc_LS : Last Segment
1266 * @arg ETH_DMATxDesc_FS : First Segment
1267 * @arg ETH_DMATxDesc_DC : Disable CRC
1268 * @arg ETH_DMATxDesc_DP : Disable Pad
1269 * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
1270 * @arg ETH_DMATxDesc_TER : Transmit End of Ring
1271 * @arg ETH_DMATxDesc_TCH : Second Address Chained
1272 * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
1273 * @arg ETH_DMATxDesc_IHE : IP Header Error
1274 * @arg ETH_DMATxDesc_ES : Error summary
1275 * @arg ETH_DMATxDesc_JT : Jabber Timeout
1276 * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush
1277 * @arg ETH_DMATxDesc_PCE : Payload Checksum Error
1278 * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
1279 * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver
1280 * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
1281 * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions
1282 * @arg ETH_DMATxDesc_VF : VLAN Frame
1283 * @arg ETH_DMATxDesc_CC : Collision Count
1284 * @arg ETH_DMATxDesc_ED : Excessive Deferral
1285 * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory
1286 * @arg ETH_DMATxDesc_DB : Deferred Bit
1287 * @retval : The new state of ETH_DMATxDescFlag (SET or RESET).
1288 */
1289 FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
1290 {
1291 FlagStatus bitstatus = RESET;
1292 /* Check the parameters */
1293 assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
1294  
1295 if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
1296 {
1297 bitstatus = SET;
1298 }
1299 else
1300 {
1301 bitstatus = RESET;
1302 }
1303 return bitstatus;
1304 }
1305  
1306 /**
1307 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
1308 * @param DMATxDesc: pointer on a DMA Tx descriptor
1309 * @retval : The Transmit descriptor collision counter value.
1310 */
1311 uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
1312 {
1313 /* Return the Receive descriptor frame length */
1314 return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift);
1315 }
1316  
1317 /**
1318 * @brief Set the specified DMA Tx Desc Own bit.
1319 * @param DMATxDesc: Pointer on a Tx desc
1320 * @retval : None
1321 */
1322 void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
1323 {
1324 /* Set the DMA Tx Desc Own bit */
1325 DMATxDesc->Status |= ETH_DMATxDesc_OWN;
1326 }
1327  
1328 /**
1329 * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.
1330 * @param DMATxDesc: Pointer on a Tx desc
1331 * @param NewState: new state of the DMA Tx Desc transmit interrupt.
1332 * This parameter can be: ENABLE or DISABLE.
1333 * @retval : None
1334 */
1335 void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1336 {
1337 /* Check the parameters */
1338 assert_param(IS_FUNCTIONAL_STATE(NewState));
1339  
1340 if (NewState != DISABLE)
1341 {
1342 /* Enable the DMA Tx Desc Transmit interrupt */
1343 DMATxDesc->Status |= ETH_DMATxDesc_IC;
1344 }
1345 else
1346 {
1347 /* Disable the DMA Tx Desc Transmit interrupt */
1348 DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
1349 }
1350 }
1351  
1352 /**
1353 * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.
1354 * @param DMATxDesc: Pointer on a Tx desc
1355 * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
1356 * This parameter can be one of the following values:
1357 * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment
1358 * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment
1359 * @retval : None
1360 */
1361 void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
1362 {
1363 /* Check the parameters */
1364 assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
1365  
1366 /* Selects the DMA Tx Desc Frame segment */
1367 DMATxDesc->Status |= DMATxDesc_FrameSegment;
1368 }
1369  
1370 /**
1371 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1372 * @param DMATxDesc: pointer on a DMA Tx descriptor
1373 * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
1374 * This parameter can be one of the following values:
1375 * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
1376 * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
1377 * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1378 * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1379 * @retval : None
1380 */
1381 void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
1382 {
1383 /* Check the parameters */
1384 assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
1385  
1386 /* Set the selected DMA Tx desc checksum insertion control */
1387 DMATxDesc->Status |= DMATxDesc_Checksum;
1388 }
1389  
1390 /**
1391 * @brief Enables or disables the DMA Tx Desc CRC.
1392 * @param DMATxDesc: pointer on a DMA Tx descriptor
1393 * @param NewState: new state of the specified DMA Tx Desc CRC.
1394 * This parameter can be: ENABLE or DISABLE.
1395 * @retval : None
1396 */
1397 void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1398 {
1399 /* Check the parameters */
1400 assert_param(IS_FUNCTIONAL_STATE(NewState));
1401  
1402 if (NewState != DISABLE)
1403 {
1404 /* Enable the selected DMA Tx Desc CRC */
1405 DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
1406 }
1407 else
1408 {
1409 /* Disable the selected DMA Tx Desc CRC */
1410 DMATxDesc->Status |= ETH_DMATxDesc_DC;
1411 }
1412 }
1413  
1414 /**
1415 * @brief Enables or disables the DMA Tx Desc end of ring.
1416 * @param DMATxDesc: pointer on a DMA Tx descriptor
1417 * @param NewState: new state of the specified DMA Tx Desc end of ring.
1418 * This parameter can be: ENABLE or DISABLE.
1419 * @retval : None
1420 */
1421 void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1422 {
1423 /* Check the parameters */
1424 assert_param(IS_FUNCTIONAL_STATE(NewState));
1425  
1426 if (NewState != DISABLE)
1427 {
1428 /* Enable the selected DMA Tx Desc end of ring */
1429 DMATxDesc->Status |= ETH_DMATxDesc_TER;
1430 }
1431 else
1432 {
1433 /* Disable the selected DMA Tx Desc end of ring */
1434 DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER);
1435 }
1436 }
1437  
1438 /**
1439 * @brief Enables or disables the DMA Tx Desc second address chained.
1440 * @param DMATxDesc: pointer on a DMA Tx descriptor
1441 * @param NewState: new state of the specified DMA Tx Desc second address chained.
1442 * This parameter can be: ENABLE or DISABLE.
1443 * @retval : None
1444 */
1445 void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1446 {
1447 /* Check the parameters */
1448 assert_param(IS_FUNCTIONAL_STATE(NewState));
1449  
1450 if (NewState != DISABLE)
1451 {
1452 /* Enable the selected DMA Tx Desc second address chained */
1453 DMATxDesc->Status |= ETH_DMATxDesc_TCH;
1454 }
1455 else
1456 {
1457 /* Disable the selected DMA Tx Desc second address chained */
1458 DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH);
1459 }
1460 }
1461  
1462 /**
1463 * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1464 * @param DMATxDesc: pointer on a DMA Tx descriptor
1465 * @param NewState: new state of the specified DMA Tx Desc padding for
1466 * frame shorter than 64 bytes.
1467 * This parameter can be: ENABLE or DISABLE.
1468 * @retval : None
1469 */
1470 void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1471 {
1472 /* Check the parameters */
1473 assert_param(IS_FUNCTIONAL_STATE(NewState));
1474  
1475 if (NewState != DISABLE)
1476 {
1477 /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
1478 DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
1479 }
1480 else
1481 {
1482 /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
1483 DMATxDesc->Status |= ETH_DMATxDesc_DP;
1484 }
1485 }
1486  
1487 /**
1488 * @brief Enables or disables the DMA Tx Desc time stamp.
1489 * @param DMATxDesc: pointer on a DMA Tx descriptor
1490 * @param NewState: new state of the specified DMA Tx Desc time stamp.
1491 * This parameter can be: ENABLE or DISABLE.
1492 * @retval : None
1493 */
1494 void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
1495 {
1496 /* Check the parameters */
1497 assert_param(IS_FUNCTIONAL_STATE(NewState));
1498  
1499 if (NewState != DISABLE)
1500 {
1501 /* Enable the selected DMA Tx Desc time stamp */
1502 DMATxDesc->Status |= ETH_DMATxDesc_TTSE;
1503 }
1504 else
1505 {
1506 /* Disable the selected DMA Tx Desc time stamp */
1507 DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE);
1508 }
1509 }
1510  
1511 /**
1512 * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
1513 * @param DMATxDesc: Pointer on a Tx desc
1514 * @param BufferSize1: specifies the Tx desc buffer1 size.
1515 * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
1516 * @retval : None
1517 */
1518 void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
1519 {
1520 /* Check the parameters */
1521 assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
1522 assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
1523  
1524 /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
1525 DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift));
1526 }
1527  
1528 /**
1529 * @brief Initializes the DMA Rx descriptors in chain mode.
1530 * @param DMARxDescTab: Pointer on the first Rx desc list
1531 * @param RxBuff: Pointer on the first RxBuffer list
1532 * @param RxBuffCount: Number of the used Rx desc in the list
1533 * @retval : None
1534 */
1535 void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
1536 {
1537 uint32_t i = 0;
1538 ETH_DMADESCTypeDef *DMARxDesc;
1539  
1540 /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
1541 DMARxDescToGet = DMARxDescTab;
1542 /* Fill each DMARxDesc descriptor with the right values */
1543 for(i=0; i < RxBuffCount; i++)
1544 {
1545 /* Get the pointer on the ith member of the Rx Desc list */
1546 DMARxDesc = DMARxDescTab+i;
1547 /* Set Own bit of the Rx descriptor Status */
1548 DMARxDesc->Status = ETH_DMARxDesc_OWN;
1549  
1550 /* Set Buffer1 size and Second Address Chained bit */
1551 DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
1552 /* Set Buffer1 address pointer */
1553 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
1554  
1555 /* Initialize the next descriptor with the Next Desciptor Polling Enable */
1556 if(i < (RxBuffCount-1))
1557 {
1558 /* Set next descriptor address register with next descriptor base address */
1559 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
1560 }
1561 else
1562 {
1563 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
1564 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
1565 }
1566 }
1567  
1568 /* Set Receive Desciptor List Address Register */
1569 ETH->DMARDLAR = (uint32_t) DMARxDescTab;
1570 }
1571  
1572 /**
1573 * @brief Initializes the DMA Rx descriptors in ring mode.
1574 * @param DMARxDescTab: Pointer on the first Rx desc list
1575 * @param RxBuff1: Pointer on the first RxBuffer1 list
1576 * @param RxBuff2: Pointer on the first RxBuffer2 list
1577 * @param RxBuffCount: Number of the used Rx desc in the list
1578 * Note: see decriptor skip length defined in ETH_DMA_InitStruct
1579 * for the number of Words to skip between two unchained descriptors.
1580 * @retval : None
1581 */
1582 void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)
1583 {
1584 uint32_t i = 0;
1585 ETH_DMADESCTypeDef *DMARxDesc;
1586 /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
1587 DMARxDescToGet = DMARxDescTab;
1588 /* Fill each DMARxDesc descriptor with the right values */
1589 for(i=0; i < RxBuffCount; i++)
1590 {
1591 /* Get the pointer on the ith member of the Rx Desc list */
1592 DMARxDesc = DMARxDescTab+i;
1593 /* Set Own bit of the Rx descriptor Status */
1594 DMARxDesc->Status = ETH_DMARxDesc_OWN;
1595 /* Set Buffer1 size */
1596 DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;
1597 /* Set Buffer1 address pointer */
1598 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]);
1599  
1600 /* Set Buffer2 address pointer */
1601 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]);
1602  
1603 /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
1604 address of the list, creating a Desciptor Ring */
1605 if(i == (RxBuffCount-1))
1606 {
1607 /* Set Receive End of Ring bit */
1608 DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
1609 }
1610 }
1611  
1612 /* Set Receive Desciptor List Address Register */
1613 ETH->DMARDLAR = (uint32_t) DMARxDescTab;
1614 }
1615  
1616 /**
1617 * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not.
1618 * @param DMARxDesc: pointer on a DMA Rx descriptor
1619 * @param ETH_DMARxDescFlag: specifies the flag to check.
1620 * This parameter can be one of the following values:
1621 * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine
1622 * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame
1623 * @arg ETH_DMARxDesc_ES: Error summary
1624 * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame
1625 * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame
1626 * @arg ETH_DMARxDesc_LE: Frame size not matching with length field
1627 * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow
1628 * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame
1629 * @arg ETH_DMARxDesc_FS: First descriptor of the frame
1630 * @arg ETH_DMARxDesc_LS: Last descriptor of the frame
1631 * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
1632 * @arg ETH_DMARxDesc_LC: Late collision occurred during reception
1633 * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3
1634 * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception
1635 * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface
1636 * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits
1637 * @arg ETH_DMARxDesc_CE: CRC error
1638 * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
1639 * @retval : The new state of ETH_DMARxDescFlag (SET or RESET).
1640 */
1641 FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
1642 {
1643 FlagStatus bitstatus = RESET;
1644 /* Check the parameters */
1645 assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
1646 if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
1647 {
1648 bitstatus = SET;
1649 }
1650 else
1651 {
1652 bitstatus = RESET;
1653 }
1654 return bitstatus;
1655 }
1656  
1657 /**
1658 * @brief Set the specified DMA Rx Desc Own bit.
1659 * @param DMARxDesc: Pointer on a Rx desc
1660 * @retval : None
1661 */
1662 void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
1663 {
1664 /* Set the DMA Rx Desc Own bit */
1665 DMARxDesc->Status |= ETH_DMARxDesc_OWN;
1666 }
1667  
1668 /**
1669 * @brief Returns the specified DMA Rx Desc frame length.
1670 * @param DMARxDesc: pointer on a DMA Rx descriptor
1671 * @retval : The Rx descriptor received frame length.
1672 */
1673 uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
1674 {
1675 /* Return the Receive descriptor frame length */
1676 return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift);
1677 }
1678  
1679 /**
1680 * @brief Enables or disables the specified DMA Rx Desc receive interrupt.
1681 * @param DMARxDesc: Pointer on a Rx desc
1682 * @param NewState: new state of the specified DMA Rx Desc interrupt.
1683 * This parameter can be: ENABLE or DISABLE.
1684 * @retval : None
1685 */
1686 void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1687 {
1688 /* Check the parameters */
1689 assert_param(IS_FUNCTIONAL_STATE(NewState));
1690  
1691 if (NewState != DISABLE)
1692 {
1693 /* Enable the DMA Rx Desc receive interrupt */
1694 DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
1695 }
1696 else
1697 {
1698 /* Disable the DMA Rx Desc receive interrupt */
1699 DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
1700 }
1701 }
1702  
1703 /**
1704 * @brief Enables or disables the DMA Rx Desc end of ring.
1705 * @param DMARxDesc: pointer on a DMA Rx descriptor
1706 * @param NewState: new state of the specified DMA Rx Desc end of ring.
1707 * This parameter can be: ENABLE or DISABLE.
1708 * @retval : None
1709 */
1710 void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1711 {
1712 /* Check the parameters */
1713 assert_param(IS_FUNCTIONAL_STATE(NewState));
1714  
1715 if (NewState != DISABLE)
1716 {
1717 /* Enable the selected DMA Rx Desc end of ring */
1718 DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
1719 }
1720 else
1721 {
1722 /* Disable the selected DMA Rx Desc end of ring */
1723 DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER);
1724 }
1725 }
1726  
1727 /**
1728 * @brief Enables or disables the DMA Rx Desc second address chained.
1729 * @param DMARxDesc: pointer on a DMA Rx descriptor
1730 * @param NewState: new state of the specified DMA Rx Desc second address chained.
1731 * This parameter can be: ENABLE or DISABLE.
1732 * @retval : None
1733 */
1734 void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
1735 {
1736 /* Check the parameters */
1737 assert_param(IS_FUNCTIONAL_STATE(NewState));
1738  
1739 if (NewState != DISABLE)
1740 {
1741 /* Enable the selected DMA Rx Desc second address chained */
1742 DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;
1743 }
1744 else
1745 {
1746 /* Disable the selected DMA Rx Desc second address chained */
1747 DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH);
1748 }
1749 }
1750  
1751 /**
1752 * @brief Returns the specified ETHERNET DMA Rx Desc buffer size.
1753 * @param DMARxDesc: pointer on a DMA Rx descriptor
1754 * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
1755 * This parameter can be any one of the following values:
1756 * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
1757 * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
1758 * @retval : The Receive descriptor frame length.
1759 */
1760 uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
1761 {
1762 /* Check the parameters */
1763 assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
1764  
1765 if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
1766 {
1767 /* Return the DMA Rx Desc buffer2 size */
1768 return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift);
1769 }
1770 else
1771 {
1772 /* Return the DMA Rx Desc buffer1 size */
1773 return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
1774 }
1775 }
1776  
1777 /*--------------------------------- DMA ------------------------------------*/
1778 /**
1779 * @brief Resets all MAC subsystem internal registers and logic.
1780 * @param None
1781 * @retval : None
1782 */
1783 void ETH_SoftwareReset(void)
1784 {
1785 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
1786 /* After reset all the registers holds their respective reset values */
1787 ETH->DMABMR |= ETH_DMABMR_SR;
1788 }
1789  
1790 /**
1791 * @brief Checks whether the ETHERNET software reset bit is set or not.
1792 * @param None
1793 * @retval : The new state of DMA Bus Mode register SR bit (SET or RESET).
1794 */
1795 FlagStatus ETH_GetSoftwareResetStatus(void)
1796 {
1797 FlagStatus bitstatus = RESET;
1798 if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
1799 {
1800 bitstatus = SET;
1801 }
1802 else
1803 {
1804 bitstatus = RESET;
1805 }
1806 return bitstatus;
1807 }
1808  
1809 /**
1810 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1811 * @param ETH_DMA_FLAG: specifies the flag to check.
1812 * This parameter can be one of the following values:
1813 * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
1814 * @arg ETH_DMA_FLAG_PMT : PMT flag
1815 * @arg ETH_DMA_FLAG_MMC : MMC flag
1816 * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
1817 * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr
1818 * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA
1819 * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
1820 * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
1821 * @arg ETH_DMA_FLAG_ER : Early receive flag
1822 * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
1823 * @arg ETH_DMA_FLAG_ET : Early transmit flag
1824 * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
1825 * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
1826 * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
1827 * @arg ETH_DMA_FLAG_R : Receive flag
1828 * @arg ETH_DMA_FLAG_TU : Underflow flag
1829 * @arg ETH_DMA_FLAG_RO : Overflow flag
1830 * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
1831 * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
1832 * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
1833 * @arg ETH_DMA_FLAG_T : Transmit flag
1834 * @retval : The new state of ETH_DMA_FLAG (SET or RESET).
1835 */
1836 FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
1837 {
1838 FlagStatus bitstatus = RESET;
1839 /* Check the parameters */
1840 assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
1841 if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
1842 {
1843 bitstatus = SET;
1844 }
1845 else
1846 {
1847 bitstatus = RESET;
1848 }
1849 return bitstatus;
1850 }
1851  
1852 /**
1853 * @brief Clears the ETHERNET’s DMA pending flag.
1854 * @param ETH_DMA_FLAG: specifies the flag to clear.
1855 * This parameter can be any combination of the following values:
1856 * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
1857 * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
1858 * @arg ETH_DMA_FLAG_ER : Early receive flag
1859 * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
1860 * @arg ETH_DMA_FLAG_ETI : Early transmit flag
1861 * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
1862 * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
1863 * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
1864 * @arg ETH_DMA_FLAG_R : Receive flag
1865 * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag
1866 * @arg ETH_DMA_FLAG_RO : Receive Overflow flag
1867 * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
1868 * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
1869 * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
1870 * @arg ETH_DMA_FLAG_T : Transmit flag
1871 * @retval : None
1872 */
1873 void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
1874 {
1875 /* Check the parameters */
1876 assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
1877  
1878 /* Clear the selected ETHERNET DMA FLAG */
1879 ETH->DMASR = (uint32_t) ETH_DMA_FLAG;
1880 }
1881  
1882 /**
1883 * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not.
1884 * @param ETH_DMA_IT: specifies the interrupt source to check.
1885 * This parameter can be one of the following values:
1886 * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt
1887 * @arg ETH_DMA_IT_PMT : PMT interrupt
1888 * @arg ETH_DMA_IT_MMC : MMC interrupt
1889 * @arg ETH_DMA_IT_NIS : Normal interrupt summary
1890 * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
1891 * @arg ETH_DMA_IT_ER : Early receive interrupt
1892 * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
1893 * @arg ETH_DMA_IT_ET : Early transmit interrupt
1894 * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
1895 * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
1896 * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
1897 * @arg ETH_DMA_IT_R : Receive interrupt
1898 * @arg ETH_DMA_IT_TU : Underflow interrupt
1899 * @arg ETH_DMA_IT_RO : Overflow interrupt
1900 * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
1901 * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
1902 * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
1903 * @arg ETH_DMA_IT_T : Transmit interrupt
1904 * @retval : The new state of ETH_DMA_IT (SET or RESET).
1905 */
1906 ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
1907 {
1908 ITStatus bitstatus = RESET;
1909 /* Check the parameters */
1910 assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
1911 if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
1912 {
1913 bitstatus = SET;
1914 }
1915 else
1916 {
1917 bitstatus = RESET;
1918 }
1919 return bitstatus;
1920 }
1921  
1922 /**
1923 * @brief Clears the ETHERNET’s DMA IT pending bit.
1924 * @param ETH_DMA_IT: specifies the interrupt pending bit to clear.
1925 * This parameter can be any combination of the following values:
1926 * @arg ETH_DMA_IT_NIS : Normal interrupt summary
1927 * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
1928 * @arg ETH_DMA_IT_ER : Early receive interrupt
1929 * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
1930 * @arg ETH_DMA_IT_ETI : Early transmit interrupt
1931 * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
1932 * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
1933 * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
1934 * @arg ETH_DMA_IT_R : Receive interrupt
1935 * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt
1936 * @arg ETH_DMA_IT_RO : Receive Overflow interrupt
1937 * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
1938 * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
1939 * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
1940 * @arg ETH_DMA_IT_T : Transmit interrupt
1941 * @retval : None
1942 */
1943 void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
1944 {
1945 /* Check the parameters */
1946 assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
1947  
1948 /* Clear the selected ETHERNET DMA IT */
1949 ETH->DMASR = (uint32_t) ETH_DMA_IT;
1950 }
1951  
1952 /**
1953 * @brief Returns the ETHERNET DMA Transmit Process State.
1954 * @param None
1955 * @retval : The new ETHERNET DMA Transmit Process State:
1956 * This can be one of the following values:
1957 * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued
1958 * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor
1959 * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status
1960 * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory
1961 * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
1962 * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor
1963 */
1964 uint32_t ETH_GetTransmitProcessState(void)
1965 {
1966 return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS));
1967 }
1968  
1969 /**
1970 * @brief Returns the ETHERNET DMA Receive Process State.
1971 * @param None
1972 * @retval : The new ETHERNET DMA Receive Process State:
1973 * This can be one of the following values:
1974 * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued
1975 * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor
1976 * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet
1977 * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
1978 * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor
1979 * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory
1980 */
1981 uint32_t ETH_GetReceiveProcessState(void)
1982 {
1983 return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS));
1984 }
1985  
1986 /**
1987 * @brief Clears the ETHERNET transmit FIFO.
1988 * @param None
1989 * @retval : None
1990 */
1991 void ETH_FlushTransmitFIFO(void)
1992 {
1993 /* Set the Flush Transmit FIFO bit */
1994 ETH->DMAOMR |= ETH_DMAOMR_FTF;
1995 }
1996  
1997 /**
1998 * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not.
1999 * @param None
2000 * @retval : The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
2001 */
2002 FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
2003 {
2004 FlagStatus bitstatus = RESET;
2005 if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
2006 {
2007 bitstatus = SET;
2008 }
2009 else
2010 {
2011 bitstatus = RESET;
2012 }
2013 return bitstatus;
2014 }
2015  
2016 /**
2017 * @brief Enables or disables the DMA transmission.
2018 * @param NewState: new state of the DMA transmission.
2019 * This parameter can be: ENABLE or DISABLE.
2020 * @retval : None
2021 */
2022 void ETH_DMATransmissionCmd(FunctionalState NewState)
2023 {
2024 /* Check the parameters */
2025 assert_param(IS_FUNCTIONAL_STATE(NewState));
2026  
2027 if (NewState != DISABLE)
2028 {
2029 /* Enable the DMA transmission */
2030 ETH->DMAOMR |= ETH_DMAOMR_ST;
2031 }
2032 else
2033 {
2034 /* Disable the DMA transmission */
2035 ETH->DMAOMR &= ~ETH_DMAOMR_ST;
2036 }
2037 }
2038  
2039 /**
2040 * @brief Enables or disables the DMA reception.
2041 * @param NewState: new state of the DMA reception.
2042 * This parameter can be: ENABLE or DISABLE.
2043 * @retval : None
2044 */
2045 void ETH_DMAReceptionCmd(FunctionalState NewState)
2046 {
2047 /* Check the parameters */
2048 assert_param(IS_FUNCTIONAL_STATE(NewState));
2049  
2050 if (NewState != DISABLE)
2051 {
2052 /* Enable the DMA reception */
2053 ETH->DMAOMR |= ETH_DMAOMR_SR;
2054 }
2055 else
2056 {
2057 /* Disable the DMA reception */
2058 ETH->DMAOMR &= ~ETH_DMAOMR_SR;
2059 }
2060 }
2061  
2062 /**
2063 * @brief Enables or disables the specified ETHERNET DMA interrupts.
2064 * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
2065 * enabled or disabled.
2066 * This parameter can be any combination of the following values:
2067 * @arg ETH_DMA_IT_NIS : Normal interrupt summary
2068 * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
2069 * @arg ETH_DMA_IT_ER : Early receive interrupt
2070 * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
2071 * @arg ETH_DMA_IT_ET : Early transmit interrupt
2072 * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
2073 * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
2074 * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
2075 * @arg ETH_DMA_IT_R : Receive interrupt
2076 * @arg ETH_DMA_IT_TU : Underflow interrupt
2077 * @arg ETH_DMA_IT_RO : Overflow interrupt
2078 * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
2079 * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
2080 * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
2081 * @arg ETH_DMA_IT_T : Transmit interrupt
2082 * @param NewState: new state of the specified ETHERNET DMA interrupts.
2083 * This parameter can be: ENABLE or DISABLE.
2084 * @retval : None
2085 */
2086 void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
2087 {
2088 /* Check the parameters */
2089 assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
2090 assert_param(IS_FUNCTIONAL_STATE(NewState));
2091  
2092 if (NewState != DISABLE)
2093 {
2094 /* Enable the selected ETHERNET DMA interrupts */
2095 ETH->DMAIER |= ETH_DMA_IT;
2096 }
2097 else
2098 {
2099 /* Disable the selected ETHERNET DMA interrupts */
2100 ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
2101 }
2102 }
2103  
2104 /**
2105 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
2106 * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check.
2107 * This parameter can be one of the following values:
2108 * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
2109 * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
2110 * @retval : The new state of ETHERNET DMA overflow Flag (SET or RESET).
2111 */
2112 FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
2113 {
2114 FlagStatus bitstatus = RESET;
2115 /* Check the parameters */
2116 assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
2117  
2118 if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
2119 {
2120 bitstatus = SET;
2121 }
2122 else
2123 {
2124 bitstatus = RESET;
2125 }
2126 return bitstatus;
2127 }
2128  
2129 /**
2130 * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
2131 * @param None
2132 * @retval : The value of Rx overflow Missed Frame Counter.
2133 */
2134 uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
2135 {
2136 return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift));
2137 }
2138  
2139 /**
2140 * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
2141 * @param None
2142 * @retval : The value of Buffer unavailable Missed Frame Counter.
2143 */
2144 uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
2145 {
2146 return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
2147 }
2148  
2149 /**
2150 * @brief Get the ETHERNET DMA DMACHTDR register value.
2151 * @param None
2152 * @retval : The value of the current Tx desc start address.
2153 */
2154 uint32_t ETH_GetCurrentTxDescStartAddress(void)
2155 {
2156 return ((uint32_t)(ETH->DMACHTDR));
2157 }
2158  
2159 /**
2160 * @brief Get the ETHERNET DMA DMACHRDR register value.
2161 * @param None
2162 * @retval : The value of the current Rx desc start address.
2163 */
2164 uint32_t ETH_GetCurrentRxDescStartAddress(void)
2165 {
2166 return ((uint32_t)(ETH->DMACHRDR));
2167 }
2168  
2169 /**
2170 * @brief Get the ETHERNET DMA DMACHTBAR register value.
2171 * @param None
2172 * @retval : The value of the current Tx desc buffer address.
2173 */
2174 uint32_t ETH_GetCurrentTxBufferAddress(void)
2175 {
2176 return ((uint32_t)(ETH->DMACHTBAR));
2177 }
2178  
2179 /**
2180 * @brief Get the ETHERNET DMA DMACHRBAR register value.
2181 * @param None
2182 * @retval : The value of the current Rx desc buffer address.
2183 */
2184 uint32_t ETH_GetCurrentRxBufferAddress(void)
2185 {
2186 return ((uint32_t)(ETH->DMACHRBAR));
2187 }
2188  
2189 /**
2190 * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand
2191 * register: (the data written could be anything). This forces
2192 * the DMA to resume transmission.
2193 * @param None
2194 * @retval : None.
2195 */
2196 void ETH_ResumeDMATransmission(void)
2197 {
2198 ETH->DMATPDR = 0;
2199 }
2200  
2201 /**
2202 * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand
2203 * register: (the data written could be anything). This forces
2204 * the DMA to resume reception.
2205 * @param None
2206 * @retval : None.
2207 */
2208 void ETH_ResumeDMAReception(void)
2209 {
2210 ETH->DMARPDR = 0;
2211 }
2212  
2213 /*--------------------------------- PMT ------------------------------------*/
2214 /**
2215 * @brief Reset Wakeup frame filter register pointer.
2216 * @param None
2217 * @retval : None
2218 */
2219 void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
2220 {
2221 /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
2222 ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
2223 }
2224  
2225 /**
2226 * @brief Populates the remote wakeup frame registers.
2227 * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer
2228 * data (8 words).
2229 * @retval : None
2230 */
2231 void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
2232 {
2233 uint32_t i = 0;
2234  
2235 /* Fill Remote Wake-up Frame Filter register with Buffer data */
2236 for(i =0; i<ETH_WakeupRegisterLength; i++)
2237 {
2238 /* Write each time to the same register */
2239 ETH->MACRWUFFR = Buffer[i];
2240 }
2241 }
2242  
2243 /**
2244 * @brief Enables or disables any unicast packet filtered by the MAC
2245 * (DAF) address recognition to be a wake-up frame.
2246 * @param NewState: new state of the MAC Global Unicast Wake-Up.
2247 * This parameter can be: ENABLE or DISABLE.
2248 * @retval : None
2249 */
2250 void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
2251 {
2252 /* Check the parameters */
2253 assert_param(IS_FUNCTIONAL_STATE(NewState));
2254  
2255 if (NewState != DISABLE)
2256 {
2257 /* Enable the MAC Global Unicast Wake-Up */
2258 ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;
2259 }
2260 else
2261 {
2262 /* Disable the MAC Global Unicast Wake-Up */
2263 ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
2264 }
2265 }
2266  
2267 /**
2268 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
2269 * @param ETH_PMT_FLAG: specifies the flag to check.
2270 * This parameter can be one of the following values:
2271 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset
2272 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
2273 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
2274 * @retval : The new state of ETHERNET PMT Flag (SET or RESET).
2275 */
2276 FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
2277 {
2278 FlagStatus bitstatus = RESET;
2279 /* Check the parameters */
2280 assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
2281  
2282 if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
2283 {
2284 bitstatus = SET;
2285 }
2286 else
2287 {
2288 bitstatus = RESET;
2289 }
2290 return bitstatus;
2291 }
2292  
2293 /**
2294 * @brief Enables or disables the MAC Wake-Up Frame Detection.
2295 * @param NewState: new state of the MAC Wake-Up Frame Detection.
2296 * This parameter can be: ENABLE or DISABLE.
2297 * @retval : None
2298 */
2299 void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
2300 {
2301 /* Check the parameters */
2302 assert_param(IS_FUNCTIONAL_STATE(NewState));
2303  
2304 if (NewState != DISABLE)
2305 {
2306 /* Enable the MAC Wake-Up Frame Detection */
2307 ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;
2308 }
2309 else
2310 {
2311 /* Disable the MAC Wake-Up Frame Detection */
2312 ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
2313 }
2314 }
2315  
2316 /**
2317 * @brief Enables or disables the MAC Magic Packet Detection.
2318 * @param NewState: new state of the MAC Magic Packet Detection.
2319 * This parameter can be: ENABLE or DISABLE.
2320 * @retval : None
2321 */
2322 void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
2323 {
2324 /* Check the parameters */
2325 assert_param(IS_FUNCTIONAL_STATE(NewState));
2326  
2327 if (NewState != DISABLE)
2328 {
2329 /* Enable the MAC Magic Packet Detection */
2330 ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;
2331 }
2332 else
2333 {
2334 /* Disable the MAC Magic Packet Detection */
2335 ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
2336 }
2337 }
2338  
2339 /**
2340 * @brief Enables or disables the MAC Power Down.
2341 * @param NewState: new state of the MAC Power Down.
2342 * This parameter can be: ENABLE or DISABLE.
2343 * @retval : None
2344 */
2345 void ETH_PowerDownCmd(FunctionalState NewState)
2346 {
2347 /* Check the parameters */
2348 assert_param(IS_FUNCTIONAL_STATE(NewState));
2349  
2350 if (NewState != DISABLE)
2351 {
2352 /* Enable the MAC Power Down */
2353 /* This puts the MAC in power down mode */
2354 ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;
2355 }
2356 else
2357 {
2358 /* Disable the MAC Power Down */
2359 ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
2360 }
2361 }
2362  
2363 /*--------------------------------- MMC ------------------------------------*/
2364 /**
2365 * @brief Enables or disables the MMC Counter Freeze.
2366 * @param NewState: new state of the MMC Counter Freeze.
2367 * This parameter can be: ENABLE or DISABLE.
2368 * @retval : None
2369 */
2370 void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
2371 {
2372 /* Check the parameters */
2373 assert_param(IS_FUNCTIONAL_STATE(NewState));
2374  
2375 if (NewState != DISABLE)
2376 {
2377 /* Enable the MMC Counter Freeze */
2378 ETH->MMCCR |= ETH_MMCCR_MCF;
2379 }
2380 else
2381 {
2382 /* Disable the MMC Counter Freeze */
2383 ETH->MMCCR &= ~ETH_MMCCR_MCF;
2384 }
2385 }
2386  
2387 /**
2388 * @brief Enables or disables the MMC Reset On Read.
2389 * @param NewState: new state of the MMC Reset On Read.
2390 * This parameter can be: ENABLE or DISABLE.
2391 * @retval : None
2392 */
2393 void ETH_MMCResetOnReadCmd(FunctionalState NewState)
2394 {
2395 /* Check the parameters */
2396 assert_param(IS_FUNCTIONAL_STATE(NewState));
2397  
2398 if (NewState != DISABLE)
2399 {
2400 /* Enable the MMC Counter reset on read */
2401 ETH->MMCCR |= ETH_MMCCR_ROR;
2402 }
2403 else
2404 {
2405 /* Disable the MMC Counter reset on read */
2406 ETH->MMCCR &= ~ETH_MMCCR_ROR;
2407 }
2408 }
2409  
2410 /**
2411 * @brief Enables or disables the MMC Counter Stop Rollover.
2412 * @param NewState: new state of the MMC Counter Stop Rollover.
2413 * This parameter can be: ENABLE or DISABLE.
2414 * @retval : None
2415 */
2416 void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
2417 {
2418 /* Check the parameters */
2419 assert_param(IS_FUNCTIONAL_STATE(NewState));
2420  
2421 if (NewState != DISABLE)
2422 {
2423 /* Disable the MMC Counter Stop Rollover */
2424 ETH->MMCCR &= ~ETH_MMCCR_CSR;
2425 }
2426 else
2427 {
2428 /* Enable the MMC Counter Stop Rollover */
2429 ETH->MMCCR |= ETH_MMCCR_CSR;
2430 }
2431 }
2432  
2433 /**
2434 * @brief Resets the MMC Counters.
2435 * @param None
2436 * @retval : None
2437 */
2438 void ETH_MMCCountersReset(void)
2439 {
2440 /* Resets the MMC Counters */
2441 ETH->MMCCR |= ETH_MMCCR_CR;
2442 }
2443  
2444 /**
2445 * @brief Enables or disables the specified ETHERNET MMC interrupts.
2446 * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt
2447 * sources to be enabled or disabled.
2448 * This parameter can be any combination of Tx interrupt or
2449 * any combination of Rx interrupt (but not both)of the following values:
2450 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2451 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2452 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2453 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2454 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2455 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2456 * @param NewState: new state of the specified ETHERNET MMC interrupts.
2457 * This parameter can be: ENABLE or DISABLE.
2458 * @retval : None
2459 */
2460 void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
2461 {
2462 /* Check the parameters */
2463 assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));
2464 assert_param(IS_FUNCTIONAL_STATE(NewState));
2465  
2466 if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
2467 {
2468 /* Remove egister mak from IT */
2469 ETH_MMC_IT &= 0xEFFFFFFF;
2470  
2471 /* ETHERNET MMC Rx interrupts selected */
2472 if (NewState != DISABLE)
2473 {
2474 /* Enable the selected ETHERNET MMC interrupts */
2475 ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);
2476 }
2477 else
2478 {
2479 /* Disable the selected ETHERNET MMC interrupts */
2480 ETH->MMCRIMR |= ETH_MMC_IT;
2481 }
2482 }
2483 else
2484 {
2485 /* ETHERNET MMC Tx interrupts selected */
2486 if (NewState != DISABLE)
2487 {
2488 /* Enable the selected ETHERNET MMC interrupts */
2489 ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);
2490 }
2491 else
2492 {
2493 /* Disable the selected ETHERNET MMC interrupts */
2494 ETH->MMCTIMR |= ETH_MMC_IT;
2495 }
2496 }
2497 }
2498  
2499 /**
2500 * @brief Checks whether the specified ETHERNET MMC IT is set or not.
2501 * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
2502 * This parameter can be one of the following values:
2503 * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value
2504 * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value
2505 * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value
2506 * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value
2507 * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value
2508 * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value
2509 * @retval : The value of ETHERNET MMC IT (SET or RESET).
2510 */
2511 ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
2512 {
2513 ITStatus bitstatus = RESET;
2514 /* Check the parameters */
2515 assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));
2516  
2517 if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
2518 {
2519 /* ETHERNET MMC Rx interrupts selected */
2520 /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */
2521 if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
2522 {
2523 bitstatus = SET;
2524 }
2525 else
2526 {
2527 bitstatus = RESET;
2528 }
2529 }
2530 else
2531 {
2532 /* ETHERNET MMC Tx interrupts selected */
2533 /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */
2534 if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
2535 {
2536 bitstatus = SET;
2537 }
2538 else
2539 {
2540 bitstatus = RESET;
2541 }
2542 }
2543  
2544 return bitstatus;
2545 }
2546  
2547 /**
2548 * @brief Get the specified ETHERNET MMC register value.
2549 * @param ETH_MMCReg: specifies the ETHERNET MMC register.
2550 * This parameter can be one of the following values:
2551 * @arg ETH_MMCCR : MMC CR register
2552 * @arg ETH_MMCRIR : MMC RIR register
2553 * @arg ETH_MMCTIR : MMC TIR register
2554 * @arg ETH_MMCRIMR : MMC RIMR register
2555 * @arg ETH_MMCTIMR : MMC TIMR register
2556 * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register
2557 * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register
2558 * @arg ETH_MMCTGFCR : MMC TGFCR register
2559 * @arg ETH_MMCRFCECR : MMC RFCECR register
2560 * @arg ETH_MMCRFAECR : MMC RFAECR register
2561 * @arg ETH_MMCRGUFCR : MMC RGUFCRregister
2562 * @retval : The value of ETHERNET MMC Register value.
2563 */
2564 uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
2565 {
2566 /* Check the parameters */
2567 assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
2568  
2569 /* Return the selected register value */
2570 return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
2571 }
2572 /*--------------------------------- PTP ------------------------------------*/
2573  
2574 /**
2575 * @brief Updated the PTP block for fine correction with the Time Stamp
2576 * Addend register value.
2577 * @param None
2578 * @retval : None
2579 */
2580 void ETH_EnablePTPTimeStampAddend(void)
2581 {
2582 /* Enable the PTP block update with the Time Stamp Addend register value */
2583 ETH->PTPTSCR |= ETH_PTPTSCR_TSARU;
2584 }
2585  
2586 /**
2587 * @brief Enable the PTP Time Stamp interrupt trigger
2588 * @param None
2589 * @retval : None
2590 */
2591 void ETH_EnablePTPTimeStampInterruptTrigger(void)
2592 {
2593 /* Enable the PTP target time interrupt */
2594 ETH->PTPTSCR |= ETH_PTPTSCR_TSITE;
2595 }
2596  
2597 /**
2598 * @brief Updated the PTP system time with the Time Stamp Update register
2599 * value.
2600 * @param None
2601 * @retval : None
2602 */
2603 void ETH_EnablePTPTimeStampUpdate(void)
2604 {
2605 /* Enable the PTP system time update with the Time Stamp Update register value */
2606 ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU;
2607 }
2608  
2609 /**
2610 * @brief Initialize the PTP Time Stamp
2611 * @param None
2612 * @retval : None
2613 */
2614 void ETH_InitializePTPTimeStamp(void)
2615 {
2616 /* Initialize the PTP Time Stamp */
2617 ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI;
2618 }
2619  
2620 /**
2621 * @brief Selects the PTP Update method
2622 * @param UpdateMethod: the PTP Update method
2623 * This parameter can be one of the following values:
2624 * @arg ETH_PTP_FineUpdate : Fine Update method
2625 * @arg ETH_PTP_CoarseUpdate : Coarse Update method
2626 * @retval : None
2627 */
2628 void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)
2629 {
2630 /* Check the parameters */
2631 assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
2632  
2633 if (UpdateMethod != ETH_PTP_CoarseUpdate)
2634 {
2635 /* Enable the PTP Fine Update method */
2636 ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;
2637 }
2638 else
2639 {
2640 /* Disable the PTP Coarse Update method */
2641 ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);
2642 }
2643 }
2644  
2645 /**
2646 * @brief Enables or disables the PTP time stamp for transmit and receive frames.
2647 * @param NewState: new state of the PTP time stamp for transmit and receive frames
2648 * This parameter can be: ENABLE or DISABLE.
2649 * @retval : None
2650 */
2651 void ETH_PTPTimeStampCmd(FunctionalState NewState)
2652 {
2653 /* Check the parameters */
2654 assert_param(IS_FUNCTIONAL_STATE(NewState));
2655  
2656 if (NewState != DISABLE)
2657 {
2658 /* Enable the PTP time stamp for transmit and receive frames */
2659 ETH->PTPTSCR |= ETH_PTPTSCR_TSE;
2660 }
2661 else
2662 {
2663 /* Disable the PTP time stamp for transmit and receive frames */
2664 ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);
2665 }
2666 }
2667  
2668 /**
2669 * @brief Checks whether the specified ETHERNET PTP flag is set or not.
2670 * @param ETH_PTP_FLAG: specifies the flag to check.
2671 * This parameter can be one of the following values:
2672 * @arg ETH_PTP_FLAG_TSARU : Addend Register Update
2673 * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable
2674 * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update
2675 * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize
2676 * @retval : The new state of ETHERNET PTP Flag (SET or RESET).
2677 */
2678 FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)
2679 {
2680 FlagStatus bitstatus = RESET;
2681 /* Check the parameters */
2682 assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
2683  
2684 if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET)
2685 {
2686 bitstatus = SET;
2687 }
2688 else
2689 {
2690 bitstatus = RESET;
2691 }
2692 return bitstatus;
2693 }
2694  
2695 /**
2696 * @brief Sets the system time Sub-Second Increment value.
2697 * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value.
2698 * @retval : None
2699 */
2700 void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)
2701 {
2702 /* Check the parameters */
2703 assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
2704 /* Set the PTP Sub-Second Increment Register */
2705 ETH->PTPSSIR = SubSecondValue;
2706 }
2707  
2708 /**
2709 * @brief Sets the Time Stamp update sign and values.
2710 * @param Sign: specifies the PTP Time update value sign.
2711 * This parameter can be one of the following values:
2712 * @arg ETH_PTP_PositiveTime : positive time value.
2713 * @arg ETH_PTP_NegativeTime : negative time value.
2714 * @param SecondValue: specifies the PTP Time update second value.
2715 * @param SubSecondValue: specifies the PTP Time update sub-second value.
2716 * this is a 31 bit value. bit32 correspond to the sign.
2717 * @retval : None
2718 */
2719 void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
2720 {
2721 /* Check the parameters */
2722 assert_param(IS_ETH_PTP_TIME_SIGN(Sign));
2723 assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue));
2724 /* Set the PTP Time Update High Register */
2725 ETH->PTPTSHUR = SecondValue;
2726  
2727 /* Set the PTP Time Update Low Register with sign */
2728 ETH->PTPTSLUR = Sign | SubSecondValue;
2729 }
2730  
2731 /**
2732 * @brief Sets the Time Stamp Addend value.
2733 * @param Value: specifies the PTP Time Stamp Addend Register value.
2734 * @retval : None
2735 */
2736 void ETH_SetPTPTimeStampAddend(uint32_t Value)
2737 {
2738 /* Set the PTP Time Stamp Addend Register */
2739 ETH->PTPTSAR = Value;
2740 }
2741  
2742 /**
2743 * @brief Sets the Target Time registers values.
2744 * @param HighValue: specifies the PTP Target Time High Register value.
2745 * @param LowValue: specifies the PTP Target Time Low Register value.
2746 * @retval : None
2747 */
2748 void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)
2749 {
2750 /* Set the PTP Target Time High Register */
2751 ETH->PTPTTHR = HighValue;
2752 /* Set the PTP Target Time Low Register */
2753 ETH->PTPTTLR = LowValue;
2754 }
2755  
2756 /**
2757 * @brief Get the specified ETHERNET PTP register value.
2758 * @param ETH_PTPReg: specifies the ETHERNET PTP register.
2759 * This parameter can be one of the following values:
2760 * @arg ETH_PTPTSCR : Sub-Second Increment Register
2761 * @arg ETH_PTPSSIR : Sub-Second Increment Register
2762 * @arg ETH_PTPTSHR : Time Stamp High Register
2763 * @arg ETH_PTPTSLR : Time Stamp Low Register
2764 * @arg ETH_PTPTSHUR : Time Stamp High Update Register
2765 * @arg ETH_PTPTSLUR : Time Stamp Low Update Register
2766 * @arg ETH_PTPTSAR : Time Stamp Addend Register
2767 * @arg ETH_PTPTTHR : Target Time High Register
2768 * @arg ETH_PTPTTLR : Target Time Low Register
2769 * @retval : The value of ETHERNET PTP Register value.
2770 */
2771 uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)
2772 {
2773 /* Check the parameters */
2774 assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
2775  
2776 /* Return the selected register value */
2777 return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));
2778 }
2779  
2780 /**
2781 * @brief Initializes the DMA Tx descriptors in chain mode with PTP.
2782 * @param DMATxDescTab: Pointer on the first Tx desc list
2783 * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
2784 * @param TxBuff: Pointer on the first TxBuffer list
2785 * @param TxBuffCount: Number of the used Tx desc in the list
2786 * @retval : None
2787 */
2788 void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
2789 {
2790 uint32_t i = 0;
2791 ETH_DMADESCTypeDef *DMATxDesc;
2792  
2793 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
2794 DMATxDescToSet = DMATxDescTab;
2795 DMAPTPTxDescToSet = DMAPTPTxDescTab;
2796 /* Fill each DMATxDesc descriptor with the right values */
2797 for(i=0; i < TxBuffCount; i++)
2798 {
2799 /* Get the pointer on the ith member of the Tx Desc list */
2800 DMATxDesc = DMATxDescTab+i;
2801 /* Set Second Address Chained bit and enable PTP */
2802 DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;
2803  
2804 /* Set Buffer1 address pointer */
2805 DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
2806  
2807 /* Initialize the next descriptor with the Next Desciptor Polling Enable */
2808 if(i < (TxBuffCount-1))
2809 {
2810 /* Set next descriptor address register with next descriptor base address */
2811 DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
2812 }
2813 else
2814 {
2815 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
2816 DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
2817 }
2818 /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
2819 (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
2820 (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
2821 }
2822 /* Store on the last DMAPTPTxDescTab desc status record the first list address */
2823 (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab;
2824  
2825 /* Set Transmit Desciptor List Address Register */
2826 ETH->DMATDLAR = (uint32_t) DMATxDescTab;
2827 }
2828  
2829 /**
2830 * @brief Initializes the DMA Rx descriptors in chain mode.
2831 * @param DMARxDescTab: Pointer on the first Rx desc list
2832 * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
2833 * @param RxBuff: Pointer on the first RxBuffer list
2834 * @param RxBuffCount: Number of the used Rx desc in the list
2835 * @retval : None
2836 */
2837 void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
2838 {
2839 uint32_t i = 0;
2840 ETH_DMADESCTypeDef *DMARxDesc;
2841  
2842 /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
2843 DMARxDescToGet = DMARxDescTab;
2844 DMAPTPRxDescToGet = DMAPTPRxDescTab;
2845 /* Fill each DMARxDesc descriptor with the right values */
2846 for(i=0; i < RxBuffCount; i++)
2847 {
2848 /* Get the pointer on the ith member of the Rx Desc list */
2849 DMARxDesc = DMARxDescTab+i;
2850 /* Set Own bit of the Rx descriptor Status */
2851 DMARxDesc->Status = ETH_DMARxDesc_OWN;
2852  
2853 /* Set Buffer1 size and Second Address Chained bit */
2854 DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
2855 /* Set Buffer1 address pointer */
2856 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
2857  
2858 /* Initialize the next descriptor with the Next Desciptor Polling Enable */
2859 if(i < (RxBuffCount-1))
2860 {
2861 /* Set next descriptor address register with next descriptor base address */
2862 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
2863 }
2864 else
2865 {
2866 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
2867 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
2868 }
2869 /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
2870 (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
2871 (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
2872 }
2873 /* Store on the last DMAPTPRxDescTab desc status record the first list address */
2874 (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab;
2875  
2876 /* Set Receive Desciptor List Address Register */
2877 ETH->DMARDLAR = (uint32_t) DMARxDescTab;
2878 }
2879  
2880 /**
2881 * @brief Transmits a packet, from application buffer, pointed by ppkt with
2882 * Time Stamp values.
2883 * @param ppkt: pointer to application packet buffer to transmit.
2884 * @param FrameLength: Tx Packet size.
2885 * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
2886 * @retval : ETH_ERROR: in case of Tx desc owned by DMA
2887 * ETH_SUCCESS: for correct transmission
2888 */
2889 uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)
2890 {
2891 uint32_t offset = 0, timeout = 0;
2892 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
2893 if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
2894 {
2895 /* Return ERROR: OWN bit set */
2896 return ETH_ERROR;
2897 }
2898 /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
2899 for(offset=0; offset<FrameLength; offset++)
2900 {
2901 (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
2902 }
2903 /* Setting the Frame Length: bits[12:0] */
2904 DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);
2905 /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
2906 DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
2907 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
2908 DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
2909 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
2910 if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
2911 {
2912 /* Clear TBUS ETHERNET DMA flag */
2913 ETH->DMASR = ETH_DMASR_TBUS;
2914 /* Resume DMA transmission*/
2915 ETH->DMATPDR = 0;
2916 }
2917 /* Wait for ETH_DMATxDesc_TTSS flag to be set */
2918 do
2919 {
2920 timeout++;
2921 } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
2922 /* Return ERROR in case of timeout */
2923 if(timeout == PHY_READ_TO)
2924 {
2925 return ETH_ERROR;
2926 }
2927 /* Clear the DMATxDescToSet status register TTSS flag */
2928 DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
2929 *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
2930 *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
2931 /* Update the ENET DMA current descriptor */
2932 /* Chained Mode */
2933 if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
2934 {
2935 /* Selects the next DMA Tx descriptor list for next buffer read */
2936 DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
2937 if(DMAPTPTxDescToSet->Status != 0)
2938 {
2939 DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
2940 }
2941 else
2942 {
2943 DMAPTPTxDescToSet++;
2944 }
2945 }
2946 else /* Ring Mode */
2947 {
2948 if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
2949 {
2950 /* Selects the next DMA Tx descriptor list for next buffer read: this will
2951 be the first Tx descriptor in this case */
2952 DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
2953 DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
2954 }
2955 else
2956 {
2957 /* Selects the next DMA Tx descriptor list for next buffer read */
2958 DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
2959 DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
2960 }
2961 }
2962 /* Return SUCCESS */
2963 return ETH_SUCCESS;
2964 }
2965  
2966 /**
2967 * @brief Receives a packet and copies it to memory pointed by ppkt with
2968 * Time Stamp values.
2969 * @param ppkt: pointer to application packet receive buffer.
2970 * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
2971 * @retval : ETH_ERROR: if there is error in reception
2972 * framelength: received packet size if packet reception is correct
2973 */
2974 uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
2975 {
2976 uint32_t offset = 0, framelength = 0;
2977 /* Check if the descriptor is owned by the ENET or CPU */
2978 if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
2979 {
2980 /* Return error: OWN bit set */
2981 return ETH_ERROR;
2982 }
2983 if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
2984 ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
2985 ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
2986 {
2987 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
2988 framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
2989 /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
2990 for(offset=0; offset<framelength; offset++)
2991 {
2992 (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
2993 }
2994 }
2995 else
2996 {
2997 /* Return ERROR */
2998 framelength = ETH_ERROR;
2999 }
3000 /* When Rx Buffer unavailable flag is set: clear it and resume reception */
3001 if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
3002 {
3003 /* Clear RBUS ETHERNET DMA flag */
3004 ETH->DMASR = ETH_DMASR_RBUS;
3005 /* Resume DMA reception */
3006 ETH->DMARPDR = 0;
3007 }
3008 *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
3009 *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
3010 /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
3011 DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
3012 /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
3013 /* Chained Mode */
3014 if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
3015 {
3016 /* Selects the next DMA Rx descriptor list for next buffer read */
3017 DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
3018 if(DMAPTPRxDescToGet->Status != 0)
3019 {
3020 DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
3021 }
3022 else
3023 {
3024 DMAPTPRxDescToGet++;
3025 }
3026 }
3027 else /* Ring Mode */
3028 {
3029 if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
3030 {
3031 /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
3032 DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
3033 }
3034 else
3035 {
3036 /* Selects the next DMA Rx descriptor list for next buffer to read */
3037 DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
3038 }
3039 }
3040 /* Return Frame Length/ERROR */
3041 return (framelength);
3042 }
3043 /**
3044 * @}
3045 */
3046  
3047 /**
3048 * @}
3049 */
3050  
3051 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/