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-- Company: |
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-- Engineer: |
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-- |
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-- Create Date: 19:30:17 01/21/2011 |
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-- Design Name: |
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-- Module Name: jtagkey - Behavioral |
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-- Project Name: |
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-- Target Devices: |
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-- Tool versions: |
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-- Description: |
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-- |
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-- Dependencies: |
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-- |
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-- Revision: |
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-- Revision 0.01 - File Created |
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-- Additional Comments: |
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-- |
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library IEEE; |
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use IEEE.STD_LOGIC_1164.ALL; |
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-- Uncomment the following library declaration if using |
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-- arithmetic functions with Signed or Unsigned values |
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--use IEEE.NUMERIC_STD.ALL; |
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-- Uncomment the following library declaration if instantiating |
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-- any Xilinx primitives in this code. |
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--library UNISIM; |
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--use UNISIM.VComponents.all; |
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entity jtagkey is |
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Port ( FT_JTAG_OE : in STD_LOGIC; |
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FT_TDO : out STD_LOGIC; |
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FT_TDI : in STD_LOGIC; |
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FT_TCK : in STD_LOGIC; |
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FT_RTCK : in STD_LOGIC; |
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FT_TMS : in STD_LOGIC; |
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FT_DBGRQ : in STD_LOGIC; |
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FT_DBGACK : out STD_LOGIC; |
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FT_nSRST_OE : in STD_LOGIC; |
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FT_nSRST_IN : out STD_LOGIC; |
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FT_nSRST_OUT : in STD_LOGIC; |
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FT_nTRST_OE : in STD_LOGIC; |
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FT_nTRST_OUT : in STD_LOGIC; |
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RTCK : out STD_LOGIC; |
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TDO : in STD_LOGIC; |
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TCK : out STD_LOGIC; |
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TDI : out STD_LOGIC; |
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TMS : out STD_LOGIC; |
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nSRST : inout STD_LOGIC; |
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nTRST : inout STD_LOGIC; |
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DBGACK : in STD_LOGIC; |
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DBGRQ : out STD_LOGIC; |
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FT_TARGET_PRESENT : out STD_LOGIC; |
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TARGET_PRESENT : in STD_LOGIC |
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); |
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end jtagkey; |
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architecture Behavioral of jtagkey is |
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begin |
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-- buffer controlled by FT_JTAG_OE |
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TDI <= FT_TDI when FT_JTAG_OE = '0' else 'Z'; |
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TMS <= FT_TMS when FT_JTAG_OE = '0' else 'Z'; |
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TCK <= FT_TCK when FT_JTAG_OE = '0' else 'Z'; |
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RTCK <= FT_RTCK when FT_JTAG_OE = '0' else 'Z'; |
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DBGRQ <= FT_DBGRQ when FT_JTAG_OE = '0' else 'Z'; |
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-- srst |
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FT_nSRST_IN <= nSRST; |
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nSRST <= FT_nSRST_OUT when FT_nSRST_OE = '0' else 'Z'; |
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-- trst |
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nTRST <= FT_nTRST_OUT when FT_nTRST_OE = '0' else 'Z'; |
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-- inputs |
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FT_TDO <= TDO; |
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FT_DBGACK <= DBGACK; |
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FT_TARGET_PRESENT <= TARGET_PRESENT; |
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end Behavioral; |
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