4499 |
kaklik |
1 |
(kicad_pcb (version 4) (host pcbnew "(2015-04-05 BZR 5577)-product") |
|
|
2 |
|
|
|
3 |
(general |
|
|
4 |
(links 0) |
|
|
5 |
(no_connects 0) |
|
|
6 |
(area 0 0 0 0) |
|
|
7 |
(thickness 1.6) |
|
|
8 |
(drawings 0) |
|
|
9 |
(tracks 0) |
|
|
10 |
(zones 0) |
|
|
11 |
(modules 0) |
|
|
12 |
(nets 1) |
|
|
13 |
) |
|
|
14 |
|
|
|
15 |
(page A4) |
|
|
16 |
(title_block |
|
|
17 |
(title NAME) |
|
|
18 |
(date "%d. %m. %Y") |
|
|
19 |
(rev REV) |
|
|
20 |
(company "Mlab www.mlab.cz") |
|
|
21 |
(comment 1 VERSION) |
|
|
22 |
(comment 2 "Short description\\nTwo lines are maximum") |
|
|
23 |
(comment 3 "nickname <email@example.com>") |
|
|
24 |
) |
|
|
25 |
|
|
|
26 |
(layers |
|
|
27 |
(0 F.Cu signal) |
|
|
28 |
(31 B.Cu signal) |
|
|
29 |
(32 B.Adhes user) |
|
|
30 |
(33 F.Adhes user) |
|
|
31 |
(34 B.Paste user) |
|
|
32 |
(35 F.Paste user) |
|
|
33 |
(36 B.SilkS user) |
|
|
34 |
(37 F.SilkS user) |
|
|
35 |
(38 B.Mask user) |
|
|
36 |
(39 F.Mask user) |
|
|
37 |
(40 Dwgs.User user) |
|
|
38 |
(41 Cmts.User user) |
|
|
39 |
(42 Eco1.User user) |
|
|
40 |
(43 Eco2.User user) |
|
|
41 |
(44 Edge.Cuts user) |
|
|
42 |
(45 Margin user) |
|
|
43 |
(46 B.CrtYd user) |
|
|
44 |
(47 F.CrtYd user) |
|
|
45 |
(48 B.Fab user) |
|
|
46 |
(49 F.Fab user) |
|
|
47 |
) |
|
|
48 |
|
|
|
49 |
(setup |
|
|
50 |
(last_trace_width 0.25) |
|
|
51 |
(trace_clearance 0.2) |
|
|
52 |
(zone_clearance 0.508) |
|
|
53 |
(zone_45_only no) |
|
|
54 |
(trace_min 0.2) |
|
|
55 |
(segment_width 0.2) |
|
|
56 |
(edge_width 0.15) |
|
|
57 |
(via_size 0.6) |
|
|
58 |
(via_drill 0.4) |
|
|
59 |
(via_min_size 0.4) |
|
|
60 |
(via_min_drill 0.3) |
|
|
61 |
(uvia_size 0.3) |
|
|
62 |
(uvia_drill 0.1) |
|
|
63 |
(uvias_allowed no) |
|
|
64 |
(uvia_min_size 0.2) |
|
|
65 |
(uvia_min_drill 0.1) |
|
|
66 |
(pcb_text_width 0.3) |
|
|
67 |
(pcb_text_size 1.5 1.5) |
|
|
68 |
(mod_edge_width 0.15) |
|
|
69 |
(mod_text_size 1 1) |
|
|
70 |
(mod_text_width 0.15) |
|
|
71 |
(pad_size 1.524 1.524) |
|
|
72 |
(pad_drill 0.762) |
|
|
73 |
(pad_to_mask_clearance 0.2) |
|
|
74 |
(aux_axis_origin 0 0) |
|
|
75 |
(visible_elements FFFFFF7F) |
|
|
76 |
(pcbplotparams |
|
|
77 |
(layerselection 0x00030_80000001) |
|
|
78 |
(usegerberextensions false) |
|
|
79 |
(excludeedgelayer true) |
|
|
80 |
(linewidth 0.150000) |
|
|
81 |
(plotframeref false) |
|
|
82 |
(viasonmask false) |
|
|
83 |
(mode 1) |
|
|
84 |
(useauxorigin false) |
|
|
85 |
(hpglpennumber 1) |
|
|
86 |
(hpglpenspeed 20) |
|
|
87 |
(hpglpendiameter 15) |
|
|
88 |
(hpglpenoverlay 2) |
|
|
89 |
(psnegative false) |
|
|
90 |
(psa4output false) |
|
|
91 |
(plotreference true) |
|
|
92 |
(plotvalue true) |
|
|
93 |
(plotinvisibletext false) |
|
|
94 |
(padsonsilk false) |
|
|
95 |
(subtractmaskfromsilk false) |
|
|
96 |
(outputformat 1) |
|
|
97 |
(mirror false) |
|
|
98 |
(drillshape 1) |
|
|
99 |
(scaleselection 1) |
|
|
100 |
(outputdirectory "")) |
|
|
101 |
) |
|
|
102 |
|
|
|
103 |
(net 0 "") |
|
|
104 |
|
|
|
105 |
(net_class Default "This is the default net class." |
|
|
106 |
(clearance 0.2) |
|
|
107 |
(trace_width 0.25) |
|
|
108 |
(via_dia 0.6) |
|
|
109 |
(via_drill 0.4) |
|
|
110 |
(uvia_dia 0.3) |
|
|
111 |
(uvia_drill 0.1) |
|
|
112 |
) |
|
|
113 |
|
|
|
114 |
) |