| 4002 |
kaklik |
1 |
(kicad_pcb (version 4) (host pcbnew 0.201503251001+5534~22~ubuntu14.04.1-product) |
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3 |
(general |
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(links 43) |
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(no_connects 3) |
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(area -1.651 -45.014 28.923429 3.429001) |
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(thickness 1.6) |
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(drawings 21) |
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(tracks 125) |
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(zones 0) |
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(modules 19) |
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(nets 9) |
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) |
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(page A4) |
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(layers |
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17 |
(0 F.Cu signal) |
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18 |
(31 B.Cu signal) |
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19 |
(32 B.Adhes user) |
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20 |
(33 F.Adhes user) |
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(34 B.Paste user) |
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22 |
(35 F.Paste user) |
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(36 B.SilkS user) |
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(37 F.SilkS user) |
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(38 B.Mask user) |
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(39 F.Mask user) |
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(40 Dwgs.User user) |
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(41 Cmts.User user) |
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(42 Eco1.User user) |
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30 |
(43 Eco2.User user) |
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31 |
(44 Edge.Cuts user) |
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(45 Margin user) |
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33 |
(46 B.CrtYd user) |
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(47 F.CrtYd user) |
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(48 B.Fab user) |
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(49 F.Fab user) |
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) |
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38 |
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39 |
(setup |
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40 |
(last_trace_width 0.4) |
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(user_trace_width 0.3) |
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42 |
(user_trace_width 0.4) |
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(user_trace_width 0.5) |
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(user_trace_width 0.6) |
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(user_trace_width 0.7) |
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(trace_clearance 0.254) |
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(zone_clearance 0.508) |
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(zone_45_only no) |
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(trace_min 0.254) |
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(segment_width 0.2) |
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(edge_width 0.1) |
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(via_size 0.889) |
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(via_drill 0.635) |
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(via_min_size 0.889) |
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(via_min_drill 0.508) |
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(uvia_size 0.508) |
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(uvia_drill 0.127) |
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(uvias_allowed no) |
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(uvia_min_size 0.508) |
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(uvia_min_drill 0.127) |
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(pcb_text_width 0.3) |
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(pcb_text_size 1.5 1.5) |
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(mod_edge_width 0.15) |
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(mod_text_size 1 1) |
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65 |
(mod_text_width 0.15) |
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66 |
(pad_size 4 4) |
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67 |
(pad_drill 4) |
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68 |
(pad_to_mask_clearance 0) |
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69 |
(aux_axis_origin 0 0) |
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70 |
(visible_elements 7FFFFF7F) |
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71 |
(pcbplotparams |
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(layerselection 0x010e0_80000001) |
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(usegerberextensions false) |
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(excludeedgelayer true) |
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(linewidth 0.100000) |
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(plotframeref false) |
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(viasonmask false) |
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(mode 1) |
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(useauxorigin false) |
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(hpglpennumber 1) |
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(hpglpenspeed 20) |
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(hpglpendiameter 15) |
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(hpglpenoverlay 2) |
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(psnegative false) |
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(psa4output false) |
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(plotreference true) |
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(plotvalue true) |
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(plotinvisibletext false) |
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(padsonsilk false) |
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(subtractmaskfromsilk false) |
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91 |
(outputformat 1) |
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92 |
(mirror false) |
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93 |
(drillshape 0) |
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94 |
(scaleselection 1) |
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95 |
(outputdirectory ../CAM_PROFI/)) |
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96 |
) |
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97 |
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98 |
(net 0 "") |
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99 |
(net 1 "Net-(C1-Pad1)") |
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100 |
(net 2 GND) |
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101 |
(net 3 VDD) |
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102 |
(net 4 /SCL) |
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103 |
(net 5 /SDA) |
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104 |
(net 6 /PWM) |
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105 |
(net 7 /A2) |
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106 |
(net 8 /A1) |
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107 |
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108 |
(net_class Default "Toto je výchozí třída sítě." |
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109 |
(clearance 0.254) |
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110 |
(trace_width 0.3) |
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111 |
(via_dia 0.889) |
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112 |
(via_drill 0.635) |
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113 |
(uvia_dia 0.508) |
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114 |
(uvia_drill 0.127) |
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115 |
(add_net /A1) |
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116 |
(add_net /A2) |
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117 |
(add_net /PWM) |
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118 |
(add_net /SCL) |
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119 |
(add_net /SDA) |
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120 |
(add_net "Net-(C1-Pad1)") |
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121 |
) |
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122 |
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123 |
(net_class Power "" |
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124 |
(clearance 0.254) |
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125 |
(trace_width 0.5) |
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126 |
(via_dia 0.889) |
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127 |
(via_drill 0.635) |
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128 |
(uvia_dia 0.508) |
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129 |
(uvia_drill 0.127) |
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130 |
(add_net GND) |
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131 |
(add_net VDD) |
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132 |
) |
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133 |
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134 |
(module Housings_SSOP:TSSOP-14_4.4x5mm_Pitch0.65mm (layer B.Cu) (tedit 55132E3D) (tstamp 55125207) |
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135 |
(at 10.16 -15.24 180) |
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136 |
(descr "14-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") |
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137 |
(tags "SSOP 0.65") |
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138 |
(path /547DEEB9) |
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139 |
(attr smd) |
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140 |
(fp_text reference U1 (at 0 0 180) (layer B.SilkS) |
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141 |
(effects (font (size 1 1) (thickness 0.15)) (justify mirror)) |
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142 |
) |
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143 |
(fp_text value AS5048B (at -0.381 -0.127 270) (layer B.SilkS) hide |
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144 |
(effects (font (size 1 1) (thickness 0.15)) (justify mirror)) |
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145 |
) |
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146 |
(fp_line (start -3.95 2.8) (end -3.95 -2.8) (layer B.CrtYd) (width 0.05)) |
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147 |
(fp_line (start 3.95 2.8) (end 3.95 -2.8) (layer B.CrtYd) (width 0.05)) |
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148 |
(fp_line (start -3.95 2.8) (end 3.95 2.8) (layer B.CrtYd) (width 0.05)) |
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149 |
(fp_line (start -3.95 -2.8) (end 3.95 -2.8) (layer B.CrtYd) (width 0.05)) |
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150 |
(fp_line (start -2.325 2.625) (end -2.325 2.4) (layer B.SilkS) (width 0.15)) |
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151 |
(fp_line (start 2.325 2.625) (end 2.325 2.4) (layer B.SilkS) (width 0.15)) |
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152 |
(fp_line (start 2.325 -2.625) (end 2.325 -2.4) (layer B.SilkS) (width 0.15)) |
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153 |
(fp_line (start -2.325 -2.625) (end -2.325 -2.4) (layer B.SilkS) (width 0.15)) |
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154 |
(fp_line (start -2.325 2.625) (end 2.325 2.625) (layer B.SilkS) (width 0.15)) |
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155 |
(fp_line (start -2.325 -2.625) (end 2.325 -2.625) (layer B.SilkS) (width 0.15)) |
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156 |
(fp_line (start -2.325 2.4) (end -3.675 2.4) (layer B.SilkS) (width 0.15)) |
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157 |
(pad 1 smd rect (at -2.95 1.95 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask) |
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158 |
(net 5 /SDA)) |
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159 |
(pad 2 smd rect (at -2.95 1.3 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask) |
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160 |
(net 4 /SCL)) |
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161 |
(pad 3 smd rect (at -2.95 0.65 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask) |
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162 |
(net 7 /A2)) |
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163 |
(pad 4 smd rect (at -2.95 0 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask) |
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164 |
(net 8 /A1)) |
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165 |
(pad 5 smd rect (at -2.95 -0.65 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask)) |
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166 |
(pad 6 smd rect (at -2.95 -1.3 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask)) |
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167 |
(pad 7 smd rect (at -2.95 -1.95 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask)) |
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168 |
(pad 8 smd rect (at 2.95 -1.95 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask)) |
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169 |
(pad 9 smd rect (at 2.95 -1.3 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask)) |
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170 |
(pad 10 smd rect (at 2.95 -0.65 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask)) |
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171 |
(pad 11 smd rect (at 2.95 0 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask) |
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172 |
(net 3 VDD)) |
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173 |
(pad 12 smd rect (at 2.95 0.65 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask) |
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174 |
(net 1 "Net-(C1-Pad1)")) |
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175 |
(pad 13 smd rect (at 2.95 1.3 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask) |
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176 |
(net 2 GND)) |
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177 |
(pad 14 smd rect (at 2.95 1.95 180) (size 1.45 0.45) (layers B.Cu B.Paste B.Mask) |
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178 |
(net 6 /PWM)) |
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179 |
(pad "" np_thru_hole circle (at 0 0 180) (size 4 4) (drill 4) (layers *.Cu)) |
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180 |
(model Housings_SSOP/TSSOP-14_4.4x5mm_Pitch0.65mm.wrl |
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181 |
(at (xyz 0 0 0)) |
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182 |
(scale (xyz 1 1 1)) |
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183 |
(rotate (xyz 0 0 0)) |
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184 |
) |
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185 |
) |
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186 |
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187 |
(module MLAB_R:SMD-0805 (layer B.Cu) (tedit 54799E0C) (tstamp 547EC927) |
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188 |
(at 4.191 -15.113 90) |
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189 |
(path /547DF05B) |
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190 |
(attr smd) |
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191 |
(fp_text reference C1 (at 0 0.3175 90) (layer B.SilkS) |
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192 |
(effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror)) |
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193 |
) |
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194 |
(fp_text value 10uF (at 0.127 -0.381 90) (layer B.SilkS) |
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195 |
(effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror)) |
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196 |
) |
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197 |
(fp_circle (center -1.651 -0.762) (end -1.651 -0.635) (layer B.SilkS) (width 0.15)) |
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198 |
(fp_line (start -0.508 -0.762) (end -1.524 -0.762) (layer B.SilkS) (width 0.15)) |
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199 |
(fp_line (start -1.524 -0.762) (end -1.524 0.762) (layer B.SilkS) (width 0.15)) |
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200 |
(fp_line (start -1.524 0.762) (end -0.508 0.762) (layer B.SilkS) (width 0.15)) |
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201 |
(fp_line (start 0.508 0.762) (end 1.524 0.762) (layer B.SilkS) (width 0.15)) |
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202 |
(fp_line (start 1.524 0.762) (end 1.524 -0.762) (layer B.SilkS) (width 0.15)) |
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203 |
(fp_line (start 1.524 -0.762) (end 0.508 -0.762) (layer B.SilkS) (width 0.15)) |
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204 |
(pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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205 |
(net 1 "Net-(C1-Pad1)")) |
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206 |
(pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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207 |
(net 2 GND)) |
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208 |
(model MLAB_3D/Resistors/chip_cms.wrl |
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209 |
(at (xyz 0 0 0)) |
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210 |
(scale (xyz 0.1 0.1 0.1)) |
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211 |
(rotate (xyz 0 0 0)) |
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212 |
) |
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213 |
) |
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214 |
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215 |
(module MLAB_R:SMD-0805 (layer B.Cu) (tedit 54799E0C) (tstamp 547EC934) |
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216 |
(at 2.54 -15.113 90) |
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217 |
(path /547DEF58) |
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218 |
(attr smd) |
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219 |
(fp_text reference C2 (at 0 0.3175 90) (layer B.SilkS) |
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220 |
(effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror)) |
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221 |
) |
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222 |
(fp_text value 100nF (at 0.127 -0.381 90) (layer B.SilkS) |
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223 |
(effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror)) |
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224 |
) |
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225 |
(fp_circle (center -1.651 -0.762) (end -1.651 -0.635) (layer B.SilkS) (width 0.15)) |
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226 |
(fp_line (start -0.508 -0.762) (end -1.524 -0.762) (layer B.SilkS) (width 0.15)) |
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227 |
(fp_line (start -1.524 -0.762) (end -1.524 0.762) (layer B.SilkS) (width 0.15)) |
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228 |
(fp_line (start -1.524 0.762) (end -0.508 0.762) (layer B.SilkS) (width 0.15)) |
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229 |
(fp_line (start 0.508 0.762) (end 1.524 0.762) (layer B.SilkS) (width 0.15)) |
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230 |
(fp_line (start 1.524 0.762) (end 1.524 -0.762) (layer B.SilkS) (width 0.15)) |
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231 |
(fp_line (start 1.524 -0.762) (end 0.508 -0.762) (layer B.SilkS) (width 0.15)) |
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232 |
(pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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233 |
(net 3 VDD)) |
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234 |
(pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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235 |
(net 2 GND)) |
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236 |
(model MLAB_3D/Resistors/chip_cms.wrl |
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237 |
(at (xyz 0 0 0)) |
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238 |
(scale (xyz 0.1 0.1 0.1)) |
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(rotate (xyz 0 0 0)) |
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) |
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) |
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242 |
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243 |
(module Hrebinky:Pin_Header_Straight_2x05 placed (layer F.Cu) (tedit 55125659) (tstamp 547EC957) |
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244 |
(at 8.89 -37.084 180) |
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245 |
(descr "1 pin") |
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246 |
(tags "CONN DEV") |
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247 |
(path /547DF2B1) |
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248 |
(fp_text reference J1 (at 0 -3.81 180) (layer F.SilkS) hide |
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249 |
(effects (font (size 1.27 1.27) (thickness 0.2032))) |
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250 |
) |
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251 |
(fp_text value JUMP_5X2 (at 1.27 0 180) (layer F.SilkS) hide |
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252 |
(effects (font (size 1.27 1.27) (thickness 0.2032))) |
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253 |
) |
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254 |
(fp_line (start -3.81 -2.54) (end -2.54 -2.54) (layer F.SilkS) (width 0.254)) |
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255 |
(fp_line (start -6.35 -2.54) (end -3.81 -2.54) (layer F.SilkS) (width 0.254)) |
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256 |
(fp_line (start 6.35 2.54) (end 6.35 -2.54) (layer F.SilkS) (width 0.254)) |
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257 |
(fp_line (start 3.81 -2.54) (end 6.35 -2.54) (layer F.SilkS) (width 0.254)) |
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258 |
(fp_line (start 3.81 2.54) (end 6.35 2.54) (layer F.SilkS) (width 0.254)) |
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259 |
(fp_line (start 3.81 2.54) (end 6.35 2.54) (layer F.SilkS) (width 0.254)) |
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260 |
(fp_line (start 3.81 -2.54) (end 6.35 -2.54) (layer F.SilkS) (width 0.254)) |
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261 |
(fp_line (start 6.35 2.54) (end 6.35 -2.54) (layer F.SilkS) (width 0.254)) |
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262 |
(fp_line (start 2.54 -2.54) (end 5.08 -2.54) (layer F.SilkS) (width 0.254)) |
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263 |
(fp_line (start -1.27 2.54) (end 1.27 2.54) (layer F.SilkS) (width 0.254)) |
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264 |
(fp_line (start -1.27 2.54) (end 1.27 2.54) (layer F.SilkS) (width 0.254)) |
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265 |
(fp_line (start 2.54 -2.54) (end 5.08 -2.54) (layer F.SilkS) (width 0.254)) |
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266 |
(fp_line (start 2.54 -2.54) (end 5.08 -2.54) (layer F.SilkS) (width 0.254)) |
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267 |
(fp_line (start 1.27 2.54) (end 3.81 2.54) (layer F.SilkS) (width 0.254)) |
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(fp_line (start 1.27 2.54) (end 3.81 2.54) (layer F.SilkS) (width 0.254)) |
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(fp_line (start 2.54 -2.54) (end 5.08 -2.54) (layer F.SilkS) (width 0.254)) |
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270 |
(fp_line (start -6.35 2.54) (end 1.27 2.54) (layer F.SilkS) (width 0.254)) |
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271 |
(fp_line (start 5.08 -2.54) (end 0 -2.54) (layer F.SilkS) (width 0.254)) |
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272 |
(fp_line (start -6.35 2.54) (end -6.35 0) (layer F.SilkS) (width 0.254)) |
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273 |
(fp_line (start -6.35 -2.54) (end -6.35 0) (layer F.SilkS) (width 0.254)) |
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274 |
(fp_line (start 0 -2.54) (end -2.54 -2.54) (layer F.SilkS) (width 0.254)) |
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275 |
(pad 9 thru_hole rect (at -2.54 -1.27 180) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.Mask F.SilkS) |
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276 |
(net 4 /SCL)) |
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277 |
(pad 5 thru_hole rect (at 5.08 1.27 180) (size 1.651 1.651) (drill 0.9) (layers *.Cu *.SilkS *.Mask) |
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278 |
(net 2 GND)) |
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279 |
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(net 3 VDD)) |
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(at (xyz 0 0 0)) |
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(scale (xyz 1 1 1)) |
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(rotate (xyz 0 0 0)) |
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) |
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(model Pin_Headers/Pin_Header_Straight_2x05.wrl |
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(at (xyz 0 0 0)) |
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(scale (xyz 1 1 1)) |
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(rotate (xyz 0 0 0)) |
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(at 16.51 -37.084) |
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(at 5.08 -5.08) |
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350 |
(at 15.24 -5.08) |
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(net 2 GND) (clearance 1) (zone_connect 2)) |
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(at 15.24 -25.4) |
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(rotate (xyz 0 0 0)) |
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(module MLAB_R:SMD-0805 (layer B.Cu) (tedit 54799E0C) (tstamp 547ED178) |
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538 |
(at 10.16 -20.447 90) |
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(path /547ED127) |
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(net 3 VDD)) |
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(model MLAB_3D/Resistors/chip_cms.wrl |
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(at (xyz 0 0 0)) |
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(scale (xyz 0.1 0.1 0.1)) |
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(rotate (xyz 0 0 0)) |
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(module MLAB_R:SMD-0805 (layer B.Cu) (tedit 54799E0C) (tstamp 547ED185) |
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566 |
(at 12.573 -20.447 90) |
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) |
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(fp_line (start -1.524 -0.762) (end -1.524 0.762) (layer B.SilkS) (width 0.15)) |
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(fp_line (start 1.524 -0.762) (end 0.508 -0.762) (layer B.SilkS) (width 0.15)) |
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(pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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(net 4 /SCL)) |
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(pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397) (layers B.Cu B.Paste B.Mask) |
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(net 3 VDD)) |
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(model MLAB_3D/Resistors/chip_cms.wrl |
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(at (xyz 0 0 0)) |
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(scale (xyz 0.1 0.1 0.1)) |
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(rotate (xyz 0 0 0)) |
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) |
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) |
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592 |
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(module Hrebinky:SMD_JUMP1X5 (layer B.Cu) (tedit 5512564D) (tstamp 547ED707) |
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594 |
(at 17.526 -15.494 180) |
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(path /547ED805) |
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(net 2 GND)) |
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(pad 2 smd rect (at 0 -2 180) (size 4 1.2) (layers B.Cu B.Paste B.Mask) |
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(net 3 VDD)) |
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(pad 3 smd rect (at 0 0 180) (size 4 1.2) (layers B.Cu B.Paste B.Mask) |
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(net 4 /SCL)) |
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(net 5 /SDA)) |
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(net 6 /PWM)) |
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) |
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613 |
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(module Mlab_C:TantalC_SizeB_Reflow (layer B.Cu) (tedit 54BBE393) (tstamp 55133735) |
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615 |
(at 6.5786 -32.004 180) |
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(descr "Tantal Cap. , Size B, EIA-3528, Reflow,") |
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(tags "Tantal Cap. , Size B, EIA-3528, Reflow,") |
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(net 3 VDD)) |
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(model MLAB_3D/Capacitors/c_tant_B.wrl |
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(at (xyz 0 0 0)) |
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(scale (xyz 1 1 1)) |
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(rotate (xyz 0 0 0)) |
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642 |
) |
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) |
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644 |
|
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645 |
(module Mlab_D:SMA_Standard (layer B.Cu) (tedit 54BBE0AF) (tstamp 55133746) |
|
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646 |
(at 12.41298 -32.004 180) |
|
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647 |
(descr "Diode SMA") |
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(tags "Diode SMA") |
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(net 3 VDD)) |
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(model MLAB_3D/Diodes/SMA.wrl |
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(scale (xyz 0.3937 0.3937 0.3937)) |
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