Rev Author Line No. Line
1757 kakl 1  
2 //struct {
1758 kakl 3 unsigned int8 firenum=TDC_FIRENUM_0;
4 unsigned int8 div_fire=TDC_DIV_FIRE_2;
5 unsigned int8 calresnum=TDC_CALPERIODS_2;
6 unsigned int8 clkhsdiv=TDC_CLKHSDIV_1;
7 unsigned int8 start_clkhs=TDC_CLKHS_ON;
8 unsigned int1 portnum=TDC_TPORTNUM_4;
9 unsigned int1 Tcycle=TDC_TCYCLE_SHORT;
10 unsigned int1 fakenum=TDC_TFAKENUM_2;
11 unsigned int1 selclkT=TDC_TSELCLK_128HS;
12 unsigned int1 calibrate=TDC_CALIBRATE_EN;
13 unsigned int1 disautocal=TDC_AUTOCAL_EN;
14 unsigned int1 MRange=TDC_MRANGE2;
15 unsigned int1 neg_stop2=TDC_NEG_STOP2;
16 unsigned int1 neg_stop1=TDC_NEG_STOP1;
17 unsigned int1 neg_start=TDC_NEG_START;
1757 kakl 18 //}reg0;
19  
20 //struct {
1758 kakl 21 unsigned int hit2=TDC_MRANGE1_HIT2_NOAC;
22 unsigned int hit1=TDC_MRANGE1_HIT1_NOAC;
23 unsigned int1 fast_init=TDC_FAST_INIT_DIS;
24 unsigned int hitin2=TDC_HITIN2_0;
25 unsigned int hitin1=TDC_HITIN1_0;
1757 kakl 26 //}reg1;
27  
28 //struct {
1758 kakl 29 unsigned int en_int=TDC_INT_ALU;
30 unsigned int1 rfedge2=TDC_CH2EDGE_RIS;
31 unsigned int1 rfedge1=TDC_CH1EDGE_RIS;
32 unsigned int32 delval1=0;
1757 kakl 33 //}reg2;
34  
35 //struct {
1758 kakl 36 unsigned int1 en_err_val=TDC_ERRVAL_DIS;
37 unsigned int tim0_mr2=TDC_TIM0MR2_16384CLKHS;
38 unsigned int32 delval2=0;
1757 kakl 39 //}reg3;
40  
1758 kakl 41 //reg4
42 unsigned int32 delval3=0;
43  
44 //reg5
45 unsigned int conf_fire=0;
46 unsigned int1 en_startnoise=TDC_STARTNOISE_DIS;
47 unsigned int1 dis_phasenoise=TDC_PHASENOISE_DIS;
48 unsigned int repeat_fire=TDC_REPEAT_FIRE_0;
1775 kaklik 49 unsigned int16 phase_fire=0;
1758 kakl 50  
1757 kakl 51 //}TDC_registers;
52  
53  
1744 kakl 54 void TDC_init()
55 {
1745 kakl 56 output_low(TDC_ENABLE);
1759 kakl 57 spi_xfer(TDC_stream,0x70,8);
1745 kakl 58 output_high(TDC_ENABLE);
1744 kakl 59 }
60  
61 void TDC_reset()
62 {
1745 kakl 63 output_low(TDC_ENABLE);
1759 kakl 64 spi_xfer(TDC_stream,0x50,8);
1745 kakl 65 output_high(TDC_ENABLE);
1744 kakl 66 }
67  
68 void TDC_start_cycle()
69 {
1745 kakl 70 output_low(TDC_ENABLE);
1759 kakl 71 spi_xfer(TDC_stream,0x01,8);
1745 kakl 72 output_high(TDC_ENABLE);
1744 kakl 73 }
74  
75 void TDC_start_temp()
76 {
1745 kakl 77 output_low(TDC_ENABLE);
1759 kakl 78 spi_xfer(TDC_stream,0x02,8);
1745 kakl 79 output_high(TDC_ENABLE);
1744 kakl 80 }
81  
82 void TDC_start_cal_resonator()
83 {
1745 kakl 84 output_low(TDC_ENABLE);
1759 kakl 85 spi_xfer(TDC_stream,0x03,8);
1745 kakl 86 output_high(TDC_ENABLE);
1744 kakl 87 }
88  
89 void TDC_start_cal()
90 {
1745 kakl 91 output_low(TDC_ENABLE);
1759 kakl 92 spi_xfer(TDC_stream,0x04,8);
1745 kakl 93 output_high(TDC_ENABLE);
1744 kakl 94 }
95  
96 unsigned int32 TDC_get_measurement(int num)
97 {
1745 kakl 98 unsigned int32 ret;
99  
100 output_low(TDC_ENABLE);
1966 kaklik 101 spi_xfer(TDC_stream,0xB0 + num, 8);
1745 kakl 102 ret=spi_xfer(TDC_stream,0,32);
103 output_high(TDC_ENABLE);
104 return ret;
1744 kakl 105 }
106  
107 unsigned int16 TDC_get_status()
108 {
1745 kakl 109 unsigned int16 ret;
110  
111 output_low(TDC_ENABLE);
112 spi_xfer(TDC_stream,0xB4,8);
113 ret=spi_xfer(TDC_stream,0,16);
114 output_high(TDC_ENABLE);
115 return ret;
1744 kakl 116 }
117  
118 unsigned int8 TDC_get_reg1()
119 {
1745 kakl 120 unsigned int8 ret;
121  
122 output_low(TDC_ENABLE);
123 spi_xfer(TDC_stream,0xB5,8);
124 ret=spi_xfer(TDC_stream,0,8);
125 output_high(TDC_ENABLE);
126 return ret;
1744 kakl 127 }
128  
1965 kaklik 129 void TDC_update_reg1() // updates reg1 only
130 {
131 output_low(TDC_ENABLE);
132 spi_xfer(TDC_stream,0x81,8);
133 spi_xfer(TDC_stream,hit2,4);
134 spi_xfer(TDC_stream,hit1,4);
135 spi_xfer(TDC_stream,fast_init,1);
136 spi_xfer(TDC_stream,1,1);
137 spi_xfer(TDC_stream,hitin2,3);
138 spi_xfer(TDC_stream,hitin1,3);
139 spi_xfer(TDC_stream,0,8);
140 output_high(TDC_ENABLE);
141 }
142  
1757 kakl 143 void TDC_update_registers()
1744 kakl 144 {
1758 kakl 145 //update reg0
1745 kakl 146 output_low(TDC_ENABLE);
1758 kakl 147 spi_xfer(TDC_stream,0x80,8);
148 spi_xfer(TDC_stream,firenum,4);
149 spi_xfer(TDC_stream,div_fire,4);
150 spi_xfer(TDC_stream,calresnum,2);
151 spi_xfer(TDC_stream,clkhsdiv,2);
152 spi_xfer(TDC_stream,start_clkhs,2);
153 spi_xfer(TDC_stream,portnum,1);
154 spi_xfer(TDC_stream,Tcycle,1);
155 spi_xfer(TDC_stream,fakenum,1);
156 spi_xfer(TDC_stream,selclkT,1);
157 spi_xfer(TDC_stream,calibrate,1);
158 spi_xfer(TDC_stream,disautocal,1);
159 spi_xfer(TDC_stream,MRange,1);
160 spi_xfer(TDC_stream,neg_stop2,1);
161 spi_xfer(TDC_stream,neg_stop1,1);
162 spi_xfer(TDC_stream,neg_start,1);
163 output_high(TDC_ENABLE);
164  
1965 kaklik 165 TDC_update_reg1(); // update reg1
1744 kakl 166  
1758 kakl 167 // update reg2
168 output_low(TDC_ENABLE);
169 spi_xfer(TDC_stream,0x82);
170 spi_xfer(TDC_stream,en_int,3);
171 spi_xfer(TDC_stream,rfedge2,1);
172 spi_xfer(TDC_stream,rfedge1,1);
173 spi_xfer(TDC_stream,delval1,19);
1745 kakl 174 output_high(TDC_ENABLE);
1744 kakl 175  
1758 kakl 176 // update reg3
1745 kakl 177 output_low(TDC_ENABLE);
1758 kakl 178 spi_xfer(TDC_stream,0x83);
179 spi_xfer(TDC_stream,0,2);
180 spi_xfer(TDC_stream,en_err_val,1);
181 spi_xfer(TDC_stream,tim0_mr2,2);
182 spi_xfer(TDC_stream,delval2,19);
1745 kakl 183 output_high(TDC_ENABLE);
1744 kakl 184  
1758 kakl 185 // update reg4
1745 kakl 186 output_low(TDC_ENABLE);
1758 kakl 187 spi_xfer(TDC_stream,0x84);
188 spi_xfer(TDC_stream,0b00100,5);
189 spi_xfer(TDC_stream,delval3,19);
1745 kakl 190 output_high(TDC_ENABLE);
1744 kakl 191  
1758 kakl 192 // update reg5
1745 kakl 193 output_low(TDC_ENABLE);
1758 kakl 194 spi_xfer(TDC_stream,0x85);
195 spi_xfer(TDC_stream,conf_fire,3);
196 spi_xfer(TDC_stream,en_startnoise,1);
197 spi_xfer(TDC_stream,dis_phasenoise,1);
198 spi_xfer(TDC_stream,repeat_fire,3);
199 spi_xfer(TDC_stream,phase_fire,16);
200 output_high(TDC_ENABLE);
1744 kakl 201 }
1757 kakl 202  
1965 kaklik 203 float TDC_mrange2_get_time(unsigned int shot)
204 {
1966 kaklik 205 unsigned int32 measurement;
206 float time;
207  
208 switch (shot)
209 {
210 case 1:
1965 kaklik 211 hit2=TDC_MRANGE2_HIT2_1CH1;
212 break;
213  
1966 kaklik 214 case 2:
1965 kaklik 215 hit2=TDC_MRANGE2_HIT2_2CH1;
216 break;
217  
1966 kaklik 218 case 3:
1965 kaklik 219 hit2=TDC_MRANGE2_HIT2_3CH1;
220 break;
1966 kaklik 221 }
222 TDC_update_reg1(); // tell to ALU which shot period must be computed
223  
224 Delay_ms(50); // wait to computing of result
225  
226 measurement=TDC_get_measurement(7&TDC_get_status()); // read computed value on pointer result register address
227  
228  
229 switch (clkhsdiv)
230 {
231 case TDC_CLKHSDIV_1:
232 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS;
233 break;
234  
235 case TDC_CLKHSDIV_2:
236 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 2.0;
237 break;
238  
239 case TDC_CLKHSDIV_4:
240 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 4.0;
241 break;
242 case TDC_CLKHSDIV_8:
243 time=(measurement/65536.0) * 1.0e6/TDC_CLKHS * 8.0;
244 break;
245 }
246 return time;
1965 kaklik 247 }